WO2021142716A1 - 一种高压倒装半导体发光元件 - Google Patents

一种高压倒装半导体发光元件 Download PDF

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WO2021142716A1
WO2021142716A1 PCT/CN2020/072489 CN2020072489W WO2021142716A1 WO 2021142716 A1 WO2021142716 A1 WO 2021142716A1 CN 2020072489 W CN2020072489 W CN 2020072489W WO 2021142716 A1 WO2021142716 A1 WO 2021142716A1
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layer
semiconductor light
emitting
transparent
transparent conductive
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PCT/CN2020/072489
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English (en)
French (fr)
Inventor
刘士伟
郑高林
何安和
王庆
洪灵愿
彭康伟
林素慧
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厦门三安光电有限公司
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Priority to PCT/CN2020/072489 priority Critical patent/WO2021142716A1/zh
Priority to KR1020227005057A priority patent/KR20220032110A/ko
Priority to CN202080002682.3A priority patent/CN112154540A/zh
Publication of WO2021142716A1 publication Critical patent/WO2021142716A1/zh
Priority to US17/857,741 priority patent/US20220344311A1/en

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    • H—ELECTRICITY
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • It relates to a high-voltage flip-chip semiconductor light-emitting element, in particular to a semiconductor light-emitting element used in backlight display and RGB display.
  • high-voltage flip chips With good heat dissipation performance, high-voltage flip chips have been used in high-power fields such as lighting, backlighting, and RGB display screens. In recent years, with the rise of RGB display screens and backlight Local Dimming fields, high-voltage flip chips have increasingly focused on small currents. The light effect and brightness uniformity.
  • the existing high-voltage flip chip is shown in Figures 1 to 2.
  • the chip manufacturing process mainly includes firstly forming an isolation groove (ISO) by etching through an etching process and two or more independent semiconductor light emitting sequences as sub-light emitting units, and then in the isolation groove (ISO)
  • the bottom and the top and sidewalls of the semiconductor light-emitting sequence are sequentially covered with a transparent isolation layer 105, and then a transparent conductive layer 106 (such as ITO) is covered on the top of each sub-light-emitting unit including a transparent isolation layer 105 and annealed to An ohmic contact is formed, the interconnection line 107 that electrically connects each sub-light-emitting unit and the first electrode 108 and the second electrode 109 are vapor-deposited, the Bragg reflective layer 110 covering each sub-light-emitting unit is formed, and the first electrode pad 111 and the first electrode pad 111 and the second electrode are fabricated.
  • ISO isolation groove
  • the transparent isolation layer 105 includes covering between the interconnection wiring 107 and the sidewall of the sub-light-emitting unit to form an insulating isolation region.
  • the transparent isolation layer 105 also includes a portion under the transparent conductive layer to form a local current blocking area to prevent vertical current transmission between the interconnection line and the top surface of the sub-light-emitting unit and promote current expansion of the transparent conductive layer. The process is simple, the cost is controllable, and under the drive of normal working current, the brightness is uniform and high brightness can be achieved.
  • a high-voltage flip-chip semiconductor light-emitting element that can ensure the brightness uniformity under low current (less than 1 mA) and the relative improvement of VF4 is provided, including: a transparent substrate, including a first surface and a second surface Surface, the second surface is the main light-emitting surface;
  • At least two semiconductor light emitting sequences including: a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer stacked sequentially from bottom to top on the first surface of the substrate;
  • An isolation groove is located between two adjacent semiconductor light emitting sequences, and the bottom is the first surface of the substrate; a transparent conductive layer covering the surface of the second conductive semiconductor layer;
  • a transparent isolation layer covering and contacting the sidewalls of the semiconductor light emitting sequence, the sidewalls of the transparent conductive layer, and the upper surface of a part of the transparent conductive layer;
  • the interconnection line is located on the surface of the transparent isolation layer, electrically connects two adjacent semiconductor light emitting sequences, and contacts the transparent conductive layer of the semiconductor light emitting sequence through the first opening;
  • Bragg reflective layer covering interconnection lines and transparent isolation layer.
  • the transparent isolation layer has an opening on the transparent transparent conductive layer, part of the surface of the transparent conductive layer through the opening is exposed and contact with the interconnection line, and the remaining surface of the transparent conductive layer is covered by the transparent isolation layer .
  • the second conductivity type semiconductor layer is contacted.
  • the transparent isolation layer has an opening area above the current blocking layer, and a part of the surface of the transparent conductive layer is exposed through the plurality of openings and is in contact with the interconnection line.
  • the first transparent insulation covers the entire surface of the transparent conductive layer except under the interconnection lines and covers the sidewalls of the entire semiconductor light-emitting sequence.
  • it further includes a current blocking layer formed only between the transparent conductive layer and the second conductive type semiconductor layer, and the current blocking layer blocks current transmission in the longitudinal direction between the interconnection line and the second conductive type semiconductor layer.
  • the current blocking layer is one piece or multiple scattered pieces.
  • the transparent isolation layer has an open area above the current blocking layer, and a part of the surface of the transparent conductive layer through the pattern is exposed and is in contact with the interconnection line.
  • the transparent isolation layer covers the isolation grooves of adjacent semiconductor light-emitting sequences.
  • the Bragg reflective layer is obtained by an ion source-assisted coating process.
  • the transparent isolation layer is obtained by a PECVD process.
  • the Bragg reflective layer is directly formed on the surface of the transparent isolation layer and the interconnection lines through an ion source-assisted coating process.
  • the density of the transparent isolation layer is higher than the density of each layer of the Bragg reflective layer in the ion source-assisted coating process.
  • the thickness of the transparent isolation layer is higher than the thickness of each layer of the Bragg reflective layer in the ion source-assisted coating process.
  • the Bragg reflective layer is a multilayer formed by repeatedly stacking two insulating layers with different refractive indexes.
  • the thickness of the transparent isolation layer is 100-1000 nm.
  • the thickness of the transparent conductive layer is 10-200 nm.
  • the first conductive type semiconductor layer has a first mesa
  • the transparent isolation layer has an opening at the first mesa
  • two adjacent semiconductor light-emitting elements are connected in series via an interconnection line.
  • it further includes a first electrode and a second electrode, the second electrode is in contact with the transparent conductive layer of a semiconductor light emitting sequence, the first electrode is in direct contact with the first conductivity type semiconductor layer of another semiconductor light emitting sequence, and the interconnection line It is used to connect two adjacent semiconductor light-emitting sequences, one part is in direct contact with the first conductivity type semiconductor layer of one semiconductor light-emitting sequence, and the other part is in contact with the transparent conductive layer of another semiconductor light-emitting sequence.
  • the semiconductor light emitting element includes a first pad electrode and a second pad electrode
  • the Bragg reflective layer has a first opening and a second opening
  • the first pad electrode and the second pad electrode are respectively The first electrode and the second electrode are electrically connected through the first opening and the second opening of the Bragg reflective layer.
  • the present invention also provides a backlight display module, which includes the aforementioned high-voltage flip-chip semiconductor light-emitting element.
  • the present invention also provides a backlight display device, which includes the aforementioned backlight display module, wherein the display device implements local dimming through a LOCAL DIMMING backlight driving circuit.
  • the present invention also provides an RGB display device, which includes the aforementioned high-voltage flip-chip semiconductor light-emitting element.
  • the high-voltage flip-chip structure of the present invention can solve the problems of uneven brightness and low VF4 that occur under small current in the traditional structure by changing the positional relationship between the transparent conductive layer and the transparent isolation layer.
  • FIG. 1 is a top plan view of the high-voltage flip-chip light-emitting diode mentioned in the background art.
  • Fig. 2 is a schematic diagram of a longitudinal cross-sectional structure along the dashed line AA' in Fig. 1.
  • FIG. 3 is a top plan view of the high-voltage flip-chip light emitting diode mentioned in the first embodiment.
  • Fig. 4 is a schematic diagram of a longitudinal cross-sectional structure along the dashed line AA' in Fig. 3.
  • 5 to 13 are schematic diagrams of the intermediate structure of the manufacturing process of the high-voltage flip-chip light-emitting diode mentioned in the first embodiment.
  • FIG. 14 shows the distribution of the VF4 value of the structure of the first embodiment and the structure of the background art respectively through the 1 microampere lighting test.
  • FIG. 15 is a photomicrograph of the structure of the first embodiment and the structure of the background art when a single element passes 1 microampere for a light-up test.
  • FIG. 16 is a schematic diagram of the structure of the Bragg reflective layer of the second embodiment.
  • FIG. 17 is a schematic plan view of the high-voltage flip-chip LED mentioned in the embodiment.
  • FIG. 18 is a schematic diagram of a longitudinal cross-sectional structure along the dashed line AA' in FIG. 17.
  • 19 is a schematic plan view of an intermediate structure forming a transparent isolation layer in the third embodiment.
  • FIG. 20 is a schematic plan view of the intermediate structure for forming the interconnection line mentioned in the third embodiment.
  • 21 is a top plan view of the high-voltage flip-chip light emitting diode mentioned in the fourth embodiment.
  • FIG. 22 is a schematic diagram of a longitudinal cross-sectional structure along the dashed line AA' in FIG. 21.
  • FIG. 22 is a schematic diagram of a longitudinal cross-sectional structure along the dashed line AA' in FIG. 21.
  • FIG. 23 is a schematic plan view of the intermediate structure for forming the current blocking layer mentioned in the fourth embodiment.
  • 24 is a schematic plan view of the intermediate structure for forming the transparent isolation layer mentioned in the fourth embodiment.
  • FIG. 25 is a schematic plan view of the intermediate structure for forming interconnection lines mentioned in the fourth embodiment.
  • 100 substrate; 101: substrate pattern; 102: first conductivity type semiconductor layer; 1021: first mesa; 103: light-emitting layer, 104: second conductivity type semiconductor layer; 105: transparent isolation layer, 1051: first Opening; 1052: second opening; 106: transparent conductive layer; 107: interconnection line; 108: first electrode; 109: second electrode; 110: Bragg reflective layer; 1101: lowermost layer; 1102: first insulating material 1102: the second insulating material; 1103: the uppermost layer; 111: the first pad electrode; 112: the second pad electrode.
  • the present invention discloses a high-voltage flip-chip light-emitting diode device structure.
  • the illustrations provided in this embodiment only illustrate the basic idea of the present invention in a schematic manner.
  • the figures only show the components related to the present invention instead of the number, shape, and shape of the components in actual implementation.
  • the type, quantity, and proportion of each component can be changed at will during actual implementation, and the component layout type may also be more complicated.
  • the light-emitting diode structure of this embodiment is described below in conjunction with the manufacturing method.
  • Figures 3 to 4 are plan views and cross-sectional views of the high-voltage flip-chip light-emitting diode structure of Embodiment 1
  • Figures 5 to 11 are the method steps for obtaining the structure of Embodiment 1.
  • the light-emitting diode structure includes: a substrate 100; and a plurality of semiconductor light-emitting sequences arranged on the substrate, and the plurality of semiconductor light-emitting sequences pass through the isolation groove ISO The areas are separated to form several light-emitting units.
  • the substrate 100 is transparent, such as sapphire, gallium arsenide, glass or other transparent materials.
  • the substrate 100 includes a first surface. And the second surface, the second surface is the main light-emitting surface.
  • the first surface of the substrate 100 may include a substrate pattern 101.
  • the first surface of the substrate 100 includes a semiconductor light emitting sequence.
  • the semiconductor light emitting sequence includes at least a first conductivity type semiconductor layer 102, a light emitting layer 103, and a second conductivity type semiconductor layer 104, wherein the N type and P type are the first conductivity type and One of the second conductivity types.
  • the semiconductor light-emitting sequence may be formed on the substrate 100 by MOCVD growth, or the semiconductor light-emitting sequence may be transferred to the transparent substrate 100 by a transfer process.
  • the semiconductor layer 102 includes at least a first mesa 1021 for subsequent contact with one end of the interconnection line and forming electrical connections, or preferably, a second mesa, wherein the height of the first mesa is lower than the height of the second mesa.
  • the light emitting layer 103 and the second conductive type semiconductor layer 104 are located on the second mesa.
  • the isolation trench ISO is further formed by an etching process.
  • the bottom of the isolation trench ISO is the surface of the substrate 100, and the sidewalls of the semiconductor light-emitting sequence may be partially inclined. For example, only part of the side surface may be inclined, or all the semiconductor light-emitting sequences may form an inclined surface.
  • Those skilled in the art can also perform the following optional steps in the semiconductor light emitting sequence as needed to further improve the light emitting effect of the light emitting diode structure: forming a buffer layer (Buffer), forming an electron blocking layer (EBL), and so on.
  • Buffer buffer layer
  • EBL electron blocking layer
  • a transparent conductive layer 106 is formed to cover the surface of the second conductive type semiconductor layer 104, and the entire surface of the transparent conductive layer 106 contacts the surface of the second conductive type semiconductor layer 105.
  • the transparent conductive layer 106 is selected from indium tin oxide (ITO) or zinc oxide (ZnO) or cadmium tin oxide (CTO) or indium oxide (InO) or indium (In) doped with zinc oxide (ZnO) or aluminum (Al).
  • ITO indium tin oxide
  • ZnO zinc oxide
  • Ga gallium
  • ITO indium tin oxide
  • the coverage area of the transparent conductive layer 106 on the surface of the second conductive type semiconductor layer is at least 80% or more or more than 90%.
  • the transparent conductive layer 106 can be formed by a sputtering plating process, and different patterns can also be etched as needed. And after sputtering plating, a high-temperature annealing treatment is performed to achieve a good ohmic contact between the transparent conductive layer 106 and the second conductive type semiconductor layer 104.
  • the temperature range of the high-temperature annealing treatment of the transparent conductive layer 106 is 500° C. or more.
  • a transparent isolation layer 105 is formed, which completely covers the bottom of the isolation trench, the sidewalls of the semiconductor light-emitting sequence, the sidewalls of the transparent conductive layer, and the upper surface of the transparent conductive layer 106, and has a first opening 1051 exposed part
  • the transparent isolation layer 105 is deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering and other techniques.
  • the material of the transparent isolation layer 105 is insulating, preferably, for example, silicon oxide (SiO 2 ), silicon nitride or the like.
  • the transparent isolation layer is light-transmissive to the light radiated by the light-emitting layer, and preferably, the light transmittance is higher than 80%.
  • the transparent isolation layer 105 can be patterned on the surface of the transparent conductive layer 106 through processes such as etching and stripping.
  • the pattern has at least one area exposing the transparent conductive layer 106, preferably the pattern is a first opening 1051 or a plurality of first openings 1051 to expose the transparent conductive layer 106.
  • the transparent isolation layer forms a plurality of first openings between the interconnection lines and the transparent conductive layer, and the interconnection lines contact the transparent conductive layer through the plurality of first openings.
  • the specific shape of the first opening 1051 or the plurality of first openings 1051 can be designed according to usage requirements, and the first opening 1051 exposes the surface of the transparent conductive layer 106 away from the substrate.
  • the transparent isolation layer 105 does not cover the first mesa of the first conductive type semiconductor layer 102 at the same time, and a second opening 1052 may be formed on the first mesa, so that the first mesa 106 is exposed and contacts one end of the interconnection line.
  • the thickness of the transparent isolation layer 105 is preferably 100-1000 nm.
  • an interconnection line 107, a first electrode 108 and a second electrode 109 are formed, and the sub-light-emitting units are electrically connected through the interconnection line 107, such as series or parallel.
  • this embodiment provides a series connection mode.
  • the specific interconnection line 107 is formed on the transparent isolation layer 105, straddles the bottom of the isolation groove ISO, the sidewall of the sub-light-emitting unit, and one end contacts the sub-light-emitting unit.
  • the first mesa 1021 of the first conductivity type semiconductor layer 102 covers one or more first openings 1051 of the insulating layer of the adjacent sub-light-emitting unit to contact the transparent conductive layer 106 of the sub-light-emitting unit, and the interconnection line 107 is adjacent An electrical interconnection is formed between the sub-light-emitting units.
  • the transparent isolation layer 105 has a plurality of first openings 1051, and one end of the interconnection line 107 passes through the transparent isolation layer 105 to form an ohmic contact between the plurality of first openings 1051 and the transparent conductive layer 106 to promote current flow in the transparent conductive layer 106.
  • the lateral expansion of the upper side blocks the vertical current transmission between the interconnection line 107 and the second conductivity type semiconductor layer 104.
  • the first electrode 108 is formed on the first mesa of the sub-light-emitting unit to directly contact and electrically connect with the first conductive type semiconductor layer 102, and the second electrode 109 is formed on the top surface of a sub-light-emitting unit, covering the opening of the transparent isolation layer 105 An ohmic contact is formed with the transparent conductive layer 106.
  • the interconnection line 107, the first electrode 108 and the second electrode 109 are selected from a metal layer, for example, a metal layer with a reflection function and or an ohmic contact function, preferably in a strip shape or a block shape.
  • the interconnection line 107, the first electrode 108 and the second electrode 109 are formed by an evaporation process.
  • a Bragg reflective layer 110 is formed to cover the surface and sidewalls of the isolation groove and the sub-light-emitting unit. Specifically, the Bragg reflective layer is formed on the surface of the transparent isolation layer 105 and the interconnection line 107. In addition, the Bragg reflective layer 110 is provided with a first opening and a second opening at positions corresponding to the first electrode 108 and the second electrode 109.
  • the Bragg reflective layer 110 can be made by processes such as deposition and etching. As shown in FIG.
  • the Bragg reflective layer 110 may be formed by repeatedly stacking a first insulating material 1102 with a relatively high refractive index and a second insulating material 1103 with a relatively low refractive index, and theoretically corresponds to or is close to the light-emitting layer.
  • the optical thickness of a quarter of the center wavelength of the radiated light, the Bragg reflection layer 110 is made of, for example, alternately laminated silicon oxide film layers and titanium oxide film layers.
  • the thickness of the repeatedly stacked film of the Bragg reflective layer 110 is 2 micrometers or more, such as 4 to 5 micrometers, for example, 4 to 20 pairs (pairs), and preferably, the Bragg reflective layer 110 It is formed by an ion source assisted coating process.
  • the uppermost layer 1104 of the Bragg reflective layer 110 that is closest to the outside world may be formed of SiNx.
  • the layer formed of SiNx has excellent moisture resistance and can protect the light-emitting diode chip from moisture.
  • the Bragg reflective layer 110 can reflect a high proportion of the light radiated to the surface of the light-emitting layer, thereby increasing the proportion of light radiated from the second surface of the transparent substrate 110, improving the brightness and improving the light-emitting effect.
  • the lowermost layer 1101 of the Bragg reflective layer 110 can function as a bottom layer or interface layer that can improve the film quality of the distributed Bragg reflective layer.
  • the lowermost layer 1101 is preferably a PECVD deposition method to obtain a denser film layer, and the thickness of the film layer is about 0.2 ⁇ m to 1.0 ⁇ m thick.
  • the Bragg reflective layer 110 may include an interface layer formed of SiO 2 with a thickness of 0.2 ⁇ m to 1.0 ⁇ m, and a TiO 2 layer/SiO 2 layer is repeatedly laminated on the interface layer at a specific cycle.
  • the Bragg reflective layer 110 may have high visible light reflectivity.
  • the Bragg reflective layer 110 forms an entire reflective interface above the sub-light-emitting unit, around the sidewalls, and above the isolation groove, so as to ensure the reflection efficiency as much as possible.
  • the distributed Bragg reflection layer 110 can be designed in the following manner: the incident angle is 0-60°, and the reflectance of light with a wavelength of 400-700 nm is 90% or more.
  • the first pad electrode 111 and the second pad electrode 112 are located on the Bragg reflective layer 110, the first pad electrode 111 contacts the first electrode 108 through the first opening, and the second pad electrode 112 passes through the The two openings contact the second electrode 109.
  • a gap of a certain width is reserved between the first pad electrode 111 and the second pad electrode 112, and an insulating isolation is formed through the gap.
  • the first pad electrode 111 and the second pad electrode 112 may be connected to other application-type substrates, such as package substrates, through solder paste or conductive silver paste through reflow soldering or high-temperature processing.
  • a 4-inch wafer includes several high-voltage flip-chip semiconductor light-emitting device structures as shown in FIG. 3 as an embodiment, and each high-voltage flip-chip The semiconductor light-emitting element includes 6 sub-light-emitting units connected in series.
  • FIG. 1 On another wafer, several high-voltage flip-chip semiconductor light-emitting elements as shown in FIG. 1 described in the background art are obtained as a comparative example.
  • Each high-voltage flip-chip semiconductor light-emitting element is the same Including 6 sub-light-emitting units connected in series, the statistical table in Figure 13 shows the VF4 distribution of several components on the wafers of the embodiment and the comparative example.
  • FIG. 14 shows the result of a microscope photograph of a component of the structure of the embodiment and the comparative example driven by a current of 1 microampere.
  • the high-voltage flip-chip light-emitting diode of the present invention can be used in backlight display, preferably in a backlight display driven by local dimming, or can be used in an RGB display screen, and can ensure brightness uniformity under low current and a higher VF4 value.
  • the periodic reflective film layer is ion source-assisted coating to obtain high The first insulating material 1102 and the second insulating material 1103 with reflectivity.
  • the lowermost layer 1101 completely covers the sidewalls of the semiconductor light-emitting sequence, the surface of the transparent conductive layer and the surface of the interconnection line, and can protect the side of the semiconductor layer. The surface of the wall and the transparent conductive layer will not be damaged by the ion source-assisted coating process.
  • the improvement of this embodiment is that the transparent isolation layer 105 covers the entire sidewall of the semiconductor light-emitting stack to form protection, and covers the upper surface of the transparent conductive layer 106 to protect the transparent conductive layer. . Therefore, the transparent isolation layer 105 can be directly used as an ion source to assist the plating of the lowermost layer of the periodic reflective film layer, completely covering the sidewalls of the semiconductor light-emitting sequence and the upper surface of the transparent conductive layer, forming a dense protective effect.
  • the transparent isolation layer 105 forms a patterned area, such as an opening, on the upper surface of the transparent conductive layer and a position under the interconnection line 107 to provide contact between the interconnection line and the transparent conductive layer.
  • the transparent isolation layer is preferably obtained by a PECVD growth process, and its compactness is higher than the compactness of the relatively high first insulating material 1102 and the relatively low refractive index second insulating material 1103 obtained by the ion source-assisted coating process.
  • the surface of the transparent isolation layer protects the sidewalls of the semiconductor layer of the semiconductor light-emitting sequence and the transparent conductive layer will not be damaged by the ion source-assisted coating and plating ion source, so the surface of the transparent isolation layer can directly form periodic reflections through the ion source-assisted coating
  • the film layer does not lead to increased VF or poor ESD, and can play a role in improving the film quality of the Bragg reflective layer (Bragg reflective layer) 110.
  • the thickness of the transparent isolation layer 105 is 100-1000 nm.
  • the first aspect can solve the uneven brightness of the sub-light-emitting unit that occurs under low current caused by the traditional structure.
  • the insulating isolation layer may have multiple first openings on the transparent conductive layer, and multiple ohmic contacts are formed between the transparent conductive layer and the interconnection line, which is conducive to the flow of current on the transparent conductive layer
  • the transparent isolation layer completely covers the sidewalls of the semiconductor light-emitting sequence and the top surface of the transparent conductive layer, which can serve as the lowermost layer of the Bragg reflective layer to protect the semiconductor light-emitting sequence and the transparent conductive layer from being
  • the ion source assists the destruction of the coating process, eliminating the need for the lowermost layer of the DBR structure made by PECVD in the traditional process, the process is simpler, the manufacturing process can be simplified, and the production cost can be reduced.
  • the difference from the second embodiment is that when viewed from the side of the first pad electrode 111 and the second pad electrode 112, a transparent isolation layer partially covers the upper surface of the transparent conductive layer 106,
  • the shape of the transparent isolation layer 105 on the surface of the layer 106 is roughly the same as the shape of the interconnection line 107 on the transparent conductive layer 106 and the position is corresponding to form a local current blocking effect.
  • the transparent isolation layer 105 is in a block shape, and the transparent conductive layer has a pattern area, such as a plurality of first openings, and the interconnection line 107 forms an ohmic contact with the transparent conductive layer 106 through the plurality of first openings of the transparent isolation layer 105.
  • the first transparent transparent isolation layer 105 is dispersed in multiple segments on the transparent conductive layer, and the interconnection line 107 forms an ohmic contact with the transparent conductive layer 106 through the gaps of the multiple segments of the first transparent transparent isolation layer 105.
  • the transparent isolation layer 105 covers the bottom of the isolation trench, and optionally, partially or completely covers the sidewall of the semiconductor light-emitting sequence, for insulating and isolating the interconnection line 107 from the sidewall of the semiconductor light-emitting sequence.
  • FIG. 23 shows the intermediate structure obtained by forming the transparent isolation layer 105 on the transparent conductive layer
  • FIG. 24 shows the intermediate structure obtained on the interconnection line 107 and the first electrode and the second electrode on the transparent isolation layer 105.
  • the laminated structure of the Bragg reflective layer 110 is shown in FIG.
  • the Bragg reflective layer 110 covers the interconnection line 107, the transparent conductive layer 106, the bottom of the isolation trench and the side and sidewalls of the sub-light emitting unit away from the substrate.
  • the Bragg reflective layer 110 is provided with openings at positions corresponding to the first electrode 108 and the second electrode 109.
  • the Bragg reflective layer 110 may be formed by repeatedly stacking a first insulating material with a relatively high refractive index and a second insulating material with a relatively low refractive index, and theoretically corresponds to or is close to four quarters of the central wavelength of the light radiated by the light-emitting layer.
  • the Bragg reflective layer 110 is made of, for example, alternately laminated silicon oxide film layers and titanium oxide film layers.
  • the other transparent isolation layer is preferably silicon oxide, and the other transparent isolation layer is used as the lowermost layer to cover the sidewalls of the isolation groove, the sub-light-emitting unit and the side away from the substrate to prevent the use of ion source-assisted coating to make the Bragg reflective layer At 110 hours, the transparent conductive layer or the light-emitting layer is destroyed, resulting in increased VF or poor ESD.
  • the structure of this embodiment is a structure obtained by first fabricating a transparent conductive layer, and then fabricating a transparent isolation layer between the interconnection line and the sidewall of the semiconductor light-emitting sequence, which can also solve the uneven brightness of the traditional structure under low current.
  • VF4 The problem is low, but the transparent isolation layer 105 and the lowermost layer 1101 of the Bragg reflective layer require a two-step manufacturing process. Compared with the structure of the second embodiment, the manufacturing process is more complicated.
  • the structural feature that is different from the first embodiment is that before the transparent conductive layer 105 is fabricated, the current blocking layer 113 is partially covered on the surface of the second conductive type semiconductor layer 104 of the sub-light-emitting unit.
  • the current blocking layer 113 blocks the interconnection line 107 and the second electrode 109 from forming a vertical current flow between the transparent conductive layer 106 and the second conductive type semiconductor layer 107, and promotes the lateral expansion of current through the transparent conductive layer 106.
  • the position and shape of the current blocking layer 113, the interconnection line 107 and the second electrode 109 on the surface of the second conductive type semiconductor layer 104 are substantially the same.
  • the deposition process of the current blocking layer 113 on the second conductivity type semiconductor layer 104 may be a combination of photomask patterning and chemical deposition.
  • the thickness of the current blocking layer 113 is 10-500 nm.
  • the current blocking layer 113 may be a transparent dielectric layer such as silicon oxide or silicon nitride.
  • FIG. 23 shows an intermediate structure in which the current blocking layer 113 is formed on the top surface of the sub-light-emitting unit.
  • the current blocking layer 113 is preferably in the shape of a block, and its coverage area on the second conductivity type semiconductor layer 104 may be slightly larger than the coverage area of the interconnection line 107 on the second conductivity type semiconductor layer 104 to ensure better
  • the current blocking effect is to block the longitudinal transmission of current between the interconnection line 107 and the second conductivity type semiconductor layer 104, promote the diffusion of current through the transparent conductive layer, and improve the brightness of the light-emitting area. As shown in FIG.
  • the intermediate structure obtained after the transparent conductive layer 106 and the transparent isolation layer 105 are formed on the current blocking layer 113, wherein the transparent conductive layer 106 is only formed on the top of the semiconductor light emitting sequence and covers the current blocking layer 113.
  • the transparent isolation layer 105 covers the bottom of the isolation trench, the sidewalls of the sub-light-emitting unit sequence and the transparent conductive layer on the top of the sub-light-emitting unit, and one or more first openings 1051 are formed at the position of the current blocking layer 113, A second opening 1052 is formed on the first mesa of the conductive type semiconductor layer 102.
  • an intermediate structure obtained by forming an interconnection line, a first electrode and a second electrode on the surface of the transparent isolation layer 105, the interconnection line 107 is formed at the first opening 1051 and is connected to the top surface of a semiconductor light emitting sequence.
  • the transparent conductive layer 106 is in contact with the first mesa 1021 of the first conductive type semiconductor layer 102 at the second opening 1052.
  • the current blocking layer 113 is only formed on the surface of the second conductive type semiconductor layer 104. If the current blocking layer simultaneously covers the sidewalls of the transparent conductive layer, the same as the structure of the background art, the VF value increases and the brightness is uneven. Therefore, preferably, the current blocking layer 113 is formed only on the surface of the second conductivity type semiconductor layer 104, and is located only under the interconnection line, which is the same as the pattern shape of the interconnection line.
  • the high-voltage flip-chip light-emitting diode of the present invention can be applied to backlight display.
  • This embodiment provides a backlight module with high contrast between each light-emitting area, which includes a substrate, and a plurality of the aforementioned substrates arranged in sequence on the substrate.
  • the high-voltage flip-chip light-emitting diode and the fluorescent material film of the embodiment are examples of the high-voltage flip-chip light-emitting diode and the fluorescent material film of the embodiment.
  • the backlight module of the present invention further includes a driving circuit and/or at least a part of the control circuit integrated on the backlight module, wherein the control circuit may include but is not limited to a local dimming circuit, that is, the integration is controlled by the backlight board.
  • the circuit adjusts the duty cycle (Pulse Width Modulation, PWM) to adjust the brightness of the panel images in each area.
  • each backlight partition By dividing the display area into multiple backlight partitions, the backlight brightness value of each backlight partition can be adjusted independently to improve the contrast of the image.
  • Each high-voltage flip-chip light-emitting diode can emit blue light to its corresponding light-emitting area.
  • the wavelength of blue light can range from 440 nanometers to 450 nanometers.
  • the substrate is a PCB board, the PCB board has a circuit and the driving circuit can drive a plurality of LED chips 200, which can be driven in different areas.
  • the high-voltage flip-chip semiconductor light-emitting element realizes the first pad electrode and the second pad electrode to be die-bonded on the substrate through a die-bonding process.
  • a red fluorescent material and a green fluorescent material are arranged on the fluorescent film, which can emit red light and green light in various directions under the excitation of blue light, so that each light emitting area emits light of three colors of red, green and blue.
  • An embodiment of the present invention also provides a backlight display device, which includes the above-mentioned backlight module and a liquid crystal display panel, and the backlight module can be used to provide a backlight for the liquid crystal display panel.
  • the display device can be any product or component with display function, such as liquid crystal display device, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.

Abstract

一种高压倒装半导体发光元件，包括：透明衬底（100），包括第一表面和第二表面，第二表面为主要出光面；至少两个半导体发光序列，包括：自衬底（100）的第一表面由下至上依次堆叠的第一导电类型半导体层（102）、发光层（103）、第二导电类型半导体层（104）；隔离槽，位于相邻两个半导体发光序列之间，且底部为该衬底（100）的第一表面；透明导电层（106），覆盖第二导电类型半导体层（104）的表面；透明隔离层（105），覆盖并接触半导体发光序列的侧壁、透明导电层（106）的侧壁以及部分透明导电层（106）的上表面；互连线（107），位于透明隔离层（105）表面，电连接相邻两个半导体发光序列，并接触透明导电层（106）；布拉格反射层（110），覆盖互连线（107）和透明隔离层（105）。

Description

一种高压倒装半导体发光元件 技术领域
涉及一种高压倒装半导体发光元件，具体的涉及一种运用于背光显示、RGB显示的半导体发光元件。
背景技术
高压倒装芯片凭借良好的散热性能一直应用于照明、背光、RGB显屏等大功率领域，近年来随着RGB显屏、背光Local Dimming领域的兴起，高压倒装芯片愈发关注在小电流下的光效以及亮度均匀性。
现有的高压倒装芯片如图1～2所示，其芯片制程主要包括首先通过蚀刻工艺蚀刻形成隔离槽(ISO)和两个以上的独立的半导体发光序列作为子发光单元、接着在隔离槽(ISO)底部和半导体发光序列的顶部以及侧壁依次覆盖透明隔离层105、然后在每一个子发光单元的顶部包括透明隔离层105上覆盖一透明导电层106(如ITO)并做退火处理以形成欧姆接触、蒸镀电连接每一个子发光单元的互连线107以及第一电极108和第二电极109、覆盖每个子发光单元布拉格反射层反射层110以及制作第一电极焊盘111和第二电极焊盘112，两个电极焊盘透过反射层的开口接触第一电极108和第二电极109，用于外部电性连接。其中透明隔离层105包括覆盖互连接线107与子发光单元的侧壁之间，形成绝缘隔离区域。透明隔离层105同时包括位于透明导电层下方的部分，形成局部的电流阻挡区域，以阻止互连线与子发光单元的顶表面之间垂直方向的电流传输，促进透明导电层电流扩展。该工艺制程简单，成本可控，并且在正常工作电流的驱动下，亮度均匀，且能够实现高亮度。
然而在小电流下测试时，发现这类高压倒装芯片亮暗不均匀，无法满足例如RBG显屏以及背光local dimming驱动控制下光均匀性需求。经研究发现，小电流驱动下高压倒装芯片的单颗子发光单元的VF4相较于常规的单颗倒装发光二极管(仅一个发光单元)降低明显，并且亮度不均。
发明概述
技术问题
问题的解决方案
技术解决方案
基于本发明的目的，提供一种能够保证小电流(低于1mA)下的亮度均匀性以及VF4相对提升的一种高压倒装半导体发光元件，包括：透明衬底，包括第一表面和第二表面，第二表面为主要出光面；
至少两个半导体发光序列，包括：自衬底的第一表面上由下至上依次堆叠的第一导电类型半导体层、发光层、第二导电类型半导体层；
隔离槽，位于相邻两个半导体发光序列之间，且底部为所述衬底的第一表面；透明导电层，覆盖第二导电半导体层的表面；
透明隔离层，覆盖并接触半导体发光序列的侧壁、透明导电层的侧壁以及部分透明导电层的上表面；
互连线，位于透明隔离层表面，电连接相邻两个半导体发光序列，通过第一开口接触半导体发光序列的透明导电层；
布拉格反射层，覆盖互连线和透明隔离层。
优选地，所述透明隔离层在透明透明导电层上具有开口，通过所述开口透明导电层的部分表面被暴露并与互连线接触，透明导电层其余表面均被所述的透明隔离层覆盖。
优选地，接触第二导电类型半导体层。
优选地，所述的透明隔离层在电流阻挡层的上方具有开口区域，通过所述多个开口透明导电层的部分表面被暴露并与互连线接触。
优选地，所述的第一透明绝缘覆盖互连线下方以外的整个透明导电层表面以及覆盖整个半导体发光序列的侧壁。
优选地，还包括电流阻挡层，仅形成在透明导电层与第二导电类型半导体层之间，电流阻挡层阻挡电流自互连线与第二导电类型半导体层之间纵向方向的电流传输。
优选地，所述的电流阻挡层为一块或分散的多块。
优选地，所述的透明隔离层在电流阻挡层的上方具有开口区域，通过所述图形 透明导电层的部分表面被暴露并与互连线接触。
优选地，所述的互连线与半导体发光序列侧壁之间仅有透明隔离层。
优选地，所述透明隔离层覆盖在相邻半导体发光序列的隔离槽上。
优选地，所述的布拉格反射层通过离子源辅助镀膜工艺获得。
优选地，所述透明隔离层通过PECVD的工艺获得。
优选地，在所述透明隔离层以及互连线的表面直接通过离子源辅助镀膜工艺形成所述的布拉格反射层。
优选地，所述的透明隔离层的致密性高于离子源辅助镀膜工艺所述的布拉格反射层的每一层致密性。
优选地，所述的透明隔离层的厚度高于离子源辅助镀膜工艺所述的布拉格反射层的每一层厚度。
优选地，所述的布拉格反射层为两层折射率不同的绝缘层重复堆叠形成的多层。
优选地，所述的透明隔离层的厚度为100～1000nm。
优选地，所述的透明导电层的厚度为10～200nm。
优选地，第一导电类型半导体层具有一个第一台面，透明隔离层在第一台面处具有一个开口。
优选地，相邻两个半导体发光元件之间通过互连线进行串联。
优选地，还包括一个第一电极、第二电极，第二电极与一个半导体发光序列的透明导电层接触，第一电极与另外一个半导体发光序列的第一导电类型半导体层直接接触，互连线用于连接两个相邻半导体发光序列，一部分与一个半导体发光序列的第一导电类型半导体层直接接触，另一部分与另外一个半导体发光序列的透明导电层接触。
优选地，所述的半导体发光元件包括第一焊盘电极和第二焊盘电极，所述的布拉格反射层层具有第一开口和第二开口，第一焊盘电极和第二焊盘电极分别通过布拉格反射层层具有的第一开口和第二开口电连接所述的第一电极和第二电极。
本发明同时提供一种背光显示模组，其包括前述的高压倒装半导体发光元件。
本发明同时提供一种背光显示装置，其包括前述的背光显示模组，其中所述显示装置通过LOCAL DIMMING背光驱动电路实现局部调光。
本发明同时提供一种RGB显示装置，其包括前述的高压倒装半导体发光元件。发明的有益效果
有益效果
本发明的高压倒装结构通过改变透明导电层与透明隔离层的位置关系，能够解决传统的结构小电流下出现的出光亮度不均，VF4低的问题。
对附图的简要说明
附图说明
图1是背景技术中提及的高压倒装发光二极管的俯视平面图。
图2是沿着图1中AA’虚线位置的纵向剖面结构示意图。
图3是实施例一提及的高压倒装发光二极管的俯视平面图。
图4是沿着图3中AA’虚线位置的纵向剖面结构示意图。
图5～13是实施例一提及的高压倒装发光二极管的制作工艺的中间结构示意图。
图14是实施例一的结构与背景技术的结构分别通入1微安点亮测试的VF4值分布情况。
图15是实施例一的结构与背景技术的结构单颗元件通入1微安点亮测试时的显微镜拍照图。
图16是实施例二的布拉格反射层的结构示意图。
图17是实施例提及的高压倒装发光三二极管的平面示意图。
图18是沿着图17中AA’虚线位置的纵向剖面结构示意图。
图19是实施例三中形成透明隔离层的中间结构平面示意图。
图20是实施例三中提及的形成互连线的中间结构平面示意图。
图21是实施例四提及的高压倒装发光二极管的俯视平面图。
图22是沿着图21中AA’虚线位置的纵向剖面结构示意图。
图23是实施例四提及的形成电流阻挡层的中间结构平面示意图。
图24是实施例四提及的形成透明隔离层的中间结构平面示意图。
图25是实施例四提及的形成互连线的中间结构平面示意图。
附图标记说明：
100：衬底；101：衬底图形；102：第一导电类型半导体层；1021：第一台面；103：发光层，104：第二导电类型半导体层；105：透明隔离层，1051：第一开口；1052：第二开口；106：透明导电层；107：互连线；108：第一电极；109：第二电极；110：布拉格反射层；1101：最下部层；1102：第一绝缘材料；1102：第二绝缘材料；1103：最上部层；111：第一焊盘电极；112：第二焊盘电极。
发明实施例
本发明的实施方式
本发明揭示一种高压倒装发光二极管元件结构，为了使本发明的叙述更加详尽与完备，请参照下列描述并配合附图以说明。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
下面结合制作方法来说明本实施例的发光二极管结构，其中图3～4为实施例一的高压倒装发光二极管结构的平面图和剖视图，图5～11为获得实施例一的结构的方法步骤获得的中间结构，如图3～4所示，所述发光二极管结构包括：一衬底100；以及设置于所述衬底上的若干个半导体发光序列，所述若干个半导体发光序列通过隔离槽ISO区域分隔，构成若干个发光单元。
如图5所示，为了获得所述半导体发光序列，首先选择一个衬底100，衬底100为透明的，例如为蓝宝石、砷化镓、玻璃或者其它的透明材料，衬底100包括第一表面和第二表面，第二表面为主要出光面。衬底100的第一表面可以包括衬底图形101。衬底100的第一表面包括半导体发光序列，半导体发光序列至少包括第一导电类型半导体层102、发光层103、第二导电类型半导体层104，其中N型和P型分别为第一导电类型和第二导电类型中的一种。其中半导体发光序列可以是通过MOCVD生长的方式形成在衬底100上，也可以是通过转移工艺将半导体发光序列转移至透明衬底100上。
如图6所示，通过刻蚀工艺，自所述半导体发光序列的第二导电类型半导体层104去除部分半导体发光序列，至所述第一导电类型半导体层部分表面裸露形成台阶，第一导电类型半导体层102至少包括第一台面1021用于后续接触互连线的一端并形成电连接，或者较佳的，还包括第二台面，其中第一台面的高度低于第二台面的高度，所述发光层103、第二导电类型半导体层104位于第二台面上。
进一步通过刻蚀工艺形成所述隔离槽ISO。隔离槽ISO的底部为衬底100的表面，半导体发光序列的侧壁可以是局部形成倾斜面，如只有部分侧面呈倾斜，也可以是全部的半导体发光序列形成倾斜面。本领域技术人员还可以根据需要在半导体发光序列中以下可选步骤以进一步改善发光二极管结构的发光效果：形成缓冲层(Buffer)、形成电子阻挡层(EBL)等等。
如图7所示，形成透明导电层106覆盖在第二导电类型半导体层104的表面，并且透明导电层106的整面接触第二导电类型半导体层105的表面。所述透明导电层106选用氧化铟锡(ITO)或氧化锌(ZnO)或氧化镉锡(CTO)或氧化铟(InO)或铟(In)掺杂氧化锌(ZnO)或铝(Al)掺杂氧化锌(ZnO)或镓(Ga)掺杂氧化锌(ZnO)中的一种或其组合，本实施例中优选为氧化铟锡(ITO)作为透明导电层106。透明导电层106在第二导电类型半导体层的表面的覆盖面积占比至少为80％以上或者进一步的为90％以上。
所述透明导电层106可以通过溅射镀工艺形成，且也可以根据需要蚀刻不同的图案。并且在溅射镀后，进行高温退火处理以实现透明导电层106与第二导电类型半导体层104之间形成良好的欧姆接触。透明导电层106的高温退火处理的温度范围为500℃以上。
如图8～9所示，形成透明隔离层105，完整覆盖隔离槽的底部、半导体发光序列的侧壁、透明导电层的侧壁以及透明导电层106上表面，并且具有第一开口1051暴露部分透明导电层106的上表面；具体的，透明隔离层105覆盖在隔离槽ISO的底部以及半导体发光序列的侧壁，用于后续形成的互连线与半导体发光序列的侧壁之间的绝缘隔离，以及覆盖透明导电层106表面以及侧壁。以化学气相沉积方式(CVD)、物理气相沉积方式(PVD)、溅镀(sputtering)等技术沉积形成透明 隔离层105。透明隔离层105的材质为绝缘的，较佳例如可以是氧化硅(SiO2)、氮化硅之类的材料。透明隔离层对发光层辐射的光是透光的，优选地，透光率高于80％。
所述透明隔离层105在透明导电层106的表面，可以通过蚀刻、剥离等工艺形成图形。所述的图形具有至少一个暴露所述透明导电层106的区域，优选地为图形为一个第一开口1051或者多个第一开口1051以暴露透明导电层106。优选地，所述的透明隔离层在互连线与透明导电层之间形成多个第一开口，所述的互连线通过所述多个第一开口与透明导电层接触。所述一个第一开口1051或者多个第一开口1051的具体形状可以根据使用需求设计，第一开口1051暴露出透明导电层106远离衬底的面。透明隔离层105同时未覆盖第一导电类型半导体层102的第一台面，可以在第一台面上形成第二开口1052，使第一台面106被暴露并与互联线的一端接触。
所述的透明隔离层105的厚度较佳的是100～1000nm。
如图10所示，形成互连线107、第一电极108和第二电极109，子发光单元之间通过互连线107进行电性连接，例如串联或并联。优选地，本实施例提供一种串联的方式，具体的互连线107形成在透明隔离层105上，跨过所述隔离槽ISO底部、子发光单元的侧壁，一端接触一子发光单元的第一导电类型半导体层102的第一台面1021，另一端覆盖相邻子发光单元的绝缘层的一个或多个第一开口1051接触子发光单元的透明导电层106，互连线107在相邻子发光单元之间形成电性互连。优选地，透明隔离层105具有多个第一开口1051，互连线107的一端通过透明隔离层105多个第一开口1051与透明导电层106之间形成欧姆接触，促进电流在透明导电层106上的横向扩展，阻挡互连线107与第二导电类型半导体层104之间的纵向电流传递。其中第一电极108形成在子发光单元的第一台面上与第一导电类型半导体层102直接接触并电连接，第二电极109形成在一个子发光单元的顶表面，覆盖透明隔离层105的开口与透明导电层106形成欧姆接触。
互连线107、第一电极108和第二电极109选用金属层，例如具有反射功能和或欧姆接触功能的金属层，优选地，为条状或块状。所述的互连线107、第一电极108和第二电极109通过蒸镀工艺形成。
如图11所示，形成布拉格反射层110覆盖所述隔离槽和子发光单元表面以及侧壁，具体的，布拉格反射层形成在透明隔离层105和互连线107的表面上。并且所述布拉格反射层110在所述第一电极108和所述第二电极109对应的位置开设有第一开口和第二开口。所述布拉格反射层110可以通过沉积、刻蚀等工艺制成。如图12所示，所述布拉格反射层110可以通过折射率相对高的第一绝缘材料1102和折射率相对低的第二绝缘材料1103重复堆叠而成，并且理论上对应于或者接近于发光层辐射的光的中心波长的四分之一的光学厚度，布拉格反射层110例如由氧化硅膜层和氧化钛膜层交替叠层制成。优选地，其中所述的布拉格反射层110的重复堆叠薄膜的厚度为2微米以上，例如4～5微米，例如4对至20对(pairs)，并且优选地，其中所述的布拉格发射层110通过离子源辅助镀膜工艺形成。布拉格反射层110与外界最临近的最上部层1104可由SiNx形成。由SiNx形成的层的防湿性优异，可保护发光二极管芯片免受湿气的影响。
通过所述布拉格反射层110能够对发光层辐射至其表面的光进行高比例的反射，从而提升光从透明衬底110的第二表面辐射出去的比例，提升亮度，提高发光效果。
在传统的高压倒装结构中，在布拉格反射层110包括重复堆叠薄膜的情况下，布拉格反射层110的最下部层1101，可发挥可提高分布布拉格反射层的膜质的底层或界面层的作用。其中该最下部层1101优选地为PECVD沉积的方法获得更致密的膜层，该膜层的厚度为约0.2μm至1.0μm厚。例如，布拉格反射层110可包括0.2μm至1.0μm厚度的由SiO 2形成的界面层、及在界面层上按照特定周期反复积层TiO 2层/SiO 2层而成。
所述布拉格反射层110可具有较高的可见光反射率。布拉格反射层110在子发光单元的上方、侧壁周围以及隔离槽上方以形成整面的反射界面，以尽量保证反射效率。所述分布布拉格反射层110能够以如下方式设计：入射角为0～60°，对波长为400～700nm的光具有90％以上的反射率。
如图13所示，第一焊垫电极111及第二焊垫电极112位于布拉格反射层110上，第一焊盘电极111通过第一开口接触第一电极108，第二焊盘电极112通过第二开口接触第二电极109。第一焊盘电极111与第二焊盘电极112之间保留一定宽度的 间隙，通过该间隙形成绝缘隔离。
第一焊盘电极111和第二焊盘电极112可通过锡膏或导电银浆之类的材料通过回流焊或高温处理工艺连接至其它的应用型基板，例如封装基板上。
通过本实施例的工艺以及传统的工艺分别获得两片晶圆，其中一片4寸晶圆上包括数颗如图3所示意的高压倒装半导体发光元件结构作为实施例，每一颗高压倒装半导体发光元件包括串联的6个子发光单元，另外一片晶圆上获得包括数颗背景技术所述的图1所示意的高压倒装半导体发光元件作为对比例，每一颗高压倒装半导体发光元件同样包括串联的6个子发光单元，图13的统计表分别是实施例和对比例的晶圆上数颗元件的VF4分布情况，可以看出实施例结构的VF4相对于对比例的结构的VF4有所提升。图14所示的是实施例与对比例的结构在1微安的电流驱动下1颗元件的显微镜拍照结果。
对数颗元件进行抽样统计小电流如1微安的VF4结果以及亮度均匀性结果，如表一所示，可以看出实施例的结构没有出现子发光单元亮暗不均，而对比例的结构VF4相对低，并且子发光单元亮暗不均。本发明的高压倒装结构通过改变透明导电层与透明隔离层的位置关系，能够解决传统的结构小电流下出现的出光亮度不均，VF4低的问题。
表一
Figure PCTCN2020072489-appb-000001
本发明的高压倒装发光二极管可以运用于背光显示，较佳的可以运用于local  dimming驱动的背光显示，或者可运用于RGB显屏，能够保证小电流下的亮度均匀性以及更高VF4值。
实施例二
由于实施例一提及的如图12所示的布拉格反射层叠层结构，包括最下部层1101作为周期反复膜层与半导体发光序列之间的层，周期反射膜层为离子源辅助镀膜以获得高反射率的第一绝缘材料1102和第二绝缘材料1103，所述的最下部层1101完全覆盖住半导体发光序列的侧壁、透明导电层的表面以及互连线的表面，能够保护半导体层的侧壁、透明导电层的表面不会被离子源辅助镀膜工艺破坏。
如图16所示，本实施例改进的是，所述的透明隔离层105为包覆整个半导体发光叠层的侧壁以形成保护，并覆盖在透明导电层106上表面对透明导电层形成保护。由此，透明隔离层105可直接作为离子源辅助镀覆周期性反射膜层的最下部层，对半导体发光序列的侧壁以及透明导电层上表面完整的覆盖，形成致密的保护作用。透明隔离层105在透明导电层上表面以及互连线107下方的位置形成图形区域，例如开口，提供互连线与透明导电层之间的接触。
透明隔离层优选地通过PECVD生长工艺获得，其致密性会高于离子源辅助镀膜工艺获得的相对高的第一绝缘材料1102与相对低的折射率的第二绝缘材料1103的致密性。透明隔离层表面保护半导体发光序列的半导体层的侧壁、透明导电层不会被离子源辅助镀膜镀离子源破坏，因此可实现所述的透明隔离层表面直接通过离子源辅助镀膜形成周期性反射膜层，不会导致VF升高或ESD较差，并且可发挥提高布拉格反射层(布拉格反射层层)110的膜质的作用。所述的透明隔离层105的厚度为100～1000nm。
通过先形成透明导电层再制作半导体发光序列与互连线之间起绝缘隔离作用的透明隔离层，第一方面，能够解决传统的结构导致的小电流下出现的子发光单元出光亮度不均，VF4低的问题；第二方面，绝缘隔离层在透明导电层上可具有多处的第一开口，透明导电层与互连线之间形成多处的欧姆接触，有利于电流在透明导电层上的横向扩展；第三方面，透明隔离层完整包覆半导体发光序列的侧壁以及透明导电层的顶表面，能够作为布拉格反射层的的最下部层，保护 半导体发光序列以及透明导电层不会被离子源辅助镀膜工艺破坏，省去传统的工艺中采用PECVD制作的DBR结构最下部层，工艺更简单，可以简化制程，降低生产成本。
实施例三
如图17～18所示，与实施例二的区别在于，从第一焊盘电极111和第二焊盘电极112侧俯视，透明隔离层局部覆盖在透明导电层106的上表面，在透明导电层106表面透明隔离层105的形状与互连线107在透明导电层106上形状大致一致并且位置对应，以形成局部电流阻挡效果。例如透明隔离层105为一块状，在透明导电层上具有图形区域，例如多个第一开口，互连线107通过多个透明隔离层105的第一开口与透明导电层106形成欧姆接触。或者第一透明透明隔离层105在透明导电层上为分散的多段，互连线107通过多段第一透明透明隔离层105的间隙与透明导电层106形成欧姆接触。
同时，所述的透明隔离层105覆盖隔离槽的底部，并且可选的，局部或完全覆盖半导体发光序列侧壁，用于互连线107与半导体发光序列侧壁之间绝缘隔离。图23所示的是在透明导电层上形成透明隔离层105获得的中间结构，图24所示的是在互连线107以及第一电极和第二电极在透明隔离层105上获得的中间结构。布拉格反射层110的叠层结构如图12所示，并且布拉格反射层110覆盖互连线107、透明导电层106、所述隔离槽底部和子发光单元远离衬底的一面以及侧壁。并且所述布拉格反射层110在所述第一电极108和所述第二电极109对应的位置开设有开口。
所述布拉格反射层110可以通过折射率相对高的第一绝缘材料和折射率相对低的第二绝缘材料重复堆叠而成，并且理论上对应于或者接近于发光层辐射的光的中心波长的四分之一的光学厚度，布拉格反射层110例如由氧化硅膜层和氧化钛膜层交替叠层制成。布拉格反射层110与外界最临近的最上部层1104。由于本实施例的布拉格反射层110与互连线107之间还设置一层最下部层，该最下部层1101优选为PECVD工艺制作的一层100～1000nm之间的另一透明隔离层，该另一透明隔离层优选地是氧化硅，该另一透明隔离层作为最下部层覆盖在隔离槽、子发光单元的侧壁以及远离衬底的一侧，防止用离子源辅助镀膜制作布拉格反 射层110时，破坏透明导电层或发光层，导致VF升高或ESD较差。
本实施例的结构为先制作透明导电层，再制作互连线与半导体发光序列侧壁之间的透明隔离层获得的结构，同样可以解决传统的结构小电流下出现的出光亮度不均，VF4低的问题，但是透明隔离层105与布拉格反射层的最下部层1101需要两步的制作工艺，相对于实施例二的结构，制作工艺更复杂。
实施例四
如图21～22所示，与实施例一区别的结构特征在于，在制作透明导电层105之前，还包括电流阻挡层113局部覆盖在子发光单元的第二导电类型半导体层104表面。电流阻挡层113为阻挡互连线107以及第二电极109通过透明导电层106与第二导电类型半导体层107之间形成垂直的电流流向，促进电流通过透明导电层106横向扩展。优选地，自焊盘电极一侧俯视，所述的电流阻挡层113与互连线107以及第二电极109在第二导电类型半导体层104表面的位置以及形状大致一致。
电流阻挡层113在第二导电类型半导体层104上的沉积工艺可以是光罩图形、化学沉积结合的工艺。所述的电流阻挡层113的厚度为10～500nm。所述的电流阻挡层113可以是氧化硅或氮化硅等透明介质层。
具体的，图23所示的是形成电流阻挡层113形成在子发光单元的顶表面的中间结构。电流阻挡层113优选地为一个块状，其在第二导电类型半导体层104上的覆盖区域的面积可略大于互连线107在第二导电类型半导体层104上的覆盖面积，以保证较好的电流阻挡效果，阻挡电流在互连线107与第二导电类型半导体层104之间的纵向传递，促进电流通过透明导电层扩散出去，提高发光区域的亮度。如图24所示的是在电流阻挡层113上制作透明导电层106以及透明隔离层105后获得的中间结构，其中透明导电层106仅形成在半导体发光序列的顶部，并且覆盖电流阻挡层113。透明隔离层105覆盖隔离槽的底部和子发光单元序列的侧壁以及子发光单元的顶部的透明导电层上，并且在电流阻挡层113的位置处形成一个或多个第一开口1051，在第一导电类型半导体层102的第一台面上形成第二开口1052。
如图25所示，在透明隔离层105的表面形成互连线、第一电极和第二电极获得的中间结构，互连线107在第一开口1051处形成与一个半导体发光序列的顶表面 的透明导电层106接触，在第二开口1052处与第一导电类型半导体层102的第一台面1021接触。
电流阻挡层113仅形成在第二导电类型半导体层104的表面，如果电流阻挡层同时覆盖透明导电层的侧壁，则与背景技术的结构一样，导致VF值上升以及亮度不均匀。因此，较佳的，电流阻挡层113仅形成在第二导电类型半导体层104的表面，并且仅位于互连线的下方，与互连线的图形形状一样。
实施例五
本发明的高压倒装发光二极管可运用于背光显示，本实施例提供了一种各个发光区域之间的对比度较高的背光模组，其包括：基板，以及依次设置在基板上的多个前述实施例的高压倒装发光二极管和荧光材料膜片。
由于随着显示技术的发展，人们对显示装置的显示效果的要求越来越高，若显示装置中背光模组的各个出光区域之间的对比度较高，则显示装置可以有较好的显示效果。因此，本发明的背光模组，还包括驱动电路和/或控制电路的至少一部分集成在背光模组上，其中控制电路可包括但不限于区域调整电路(local dimming)，即通过背光板控制集成电路调整脉冲调变(Pulse Width Modulation，PWM)占空比(duty cycle)以针对各个区域的面板画面进行不同亮度的调整。通过将显示区域划分为多个背光分区，每个背光分区的背光亮度值可以独立调节，用以提升图像的对比度。每个高压倒装发光二极管均可以向其对应的出光区域发出蓝光。蓝光的波长范围可以为440纳米～450纳米。
其中所述的基板为PCB板，PCB板上具有电路以及该驱动电路能够驱动多个LED芯片200，可以分区域驱动。高压倒装半导体发光元件通过固晶工艺实现第一焊盘电极和第二焊盘电极固晶在基板上。
荧光膜片上设置有红色荧光材料和绿色荧光材料，能够在蓝光的激发下向各个方向发出红光与绿光，使得每个出光区域发出红绿蓝三种颜色的光。
本发明实施例还提供了一种背光显示装置，该显示装置包括上述的背光模组和液晶显示面板，该背光模组可以用于为液晶显示面板提供背光。
该显示装置可以为：液晶显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (26)

  1. 一种高压倒装半导体发光元件，包括：透明衬底，包括第一表面和第二表面，第二表面为主要出光面；
    至少两个半导体发光序列，包括：自衬底的第一表面上由下至上依次堆叠的第一导电类型半导体层、发光层、第二导电类型半导体层；
    隔离槽，位于相邻两个半导体发光序列之间，且底部为所述衬底的第一表面；
    透明导电层，覆盖第二导电半导体层的表面；
    透明隔离层，覆盖并接触半导体发光序列的侧壁、透明导电层的侧壁以及部分透明导电层的上表面；
    互连线，位于透明隔离层上表面，电连接相邻两个半导体发光序列，并接触半导体发光序列的透明导电层；
    布拉格反射层，覆盖互连线和透明隔离层。
  2. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述透明隔离层在透明透明导电层上具有开口，通过所述开口透明导电层的部分表面被暴露并与互连线接触，透明导电层其余表面均被所述的透明隔离层覆盖。
  3. 根据权利要求1所述一种高压倒装半导体发光元件，其特征在于：所述透明导电层整面接触第二导电类型半导体层。
  4. 根据权利要求3所述一种高压倒装半导体发光元件，其特征在于：所述的透明隔离层在互连线与透明导电层之间具有多个开口区域，通过所述多个开口透明导电层的部分表面被暴露并与互连线接触，透明导电层其余表面均被所述的透明隔离层覆盖。
  5. 根据权利要求4所述一种高压倒装半导体发光元件，其特征在于：所述的第一透明绝缘覆盖互连线下方之外的整个透明导电层表面以及覆盖整个半导体发光序列的侧壁。
  6. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于 ：还包括电流阻挡层，仅形成在透明导电层与第二导电类型半导体层之间，电流阻挡层阻挡电流自互连线与第二导电类型半导体层之间纵向方向的电流传输。
  7. 根据权利要求6所述一种高压倒装半导体发光元件，其特征在于：所述的电流阻挡层为一块或分散的多块。
  8. 根据权利要求7所述的一种高压倒装半导体发光元件，其特征在于：所述的透明隔离层在电流阻挡层的上方具有开口区域，通过所述开口透明导电层的部分表面被暴露并与互连线接触。
  9. 根据权利要求1所述一种高压倒装半导体发光元件，其特征在于：所述的互连线与半导体发光序列侧壁之间仅有透明隔离层。
  10. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述透明隔离层完整覆盖在相邻半导体发光序列的隔离槽。
  11. 根据权利要求1所述一种高压倒装半导体发光元件，其特征在于：所述的布拉格反射层通过离子源辅助镀膜工艺获得。
  12. 根据权利要求1或11所述的一种高压倒装半导体发光元件，其特征在于：所述透明隔离层通过PECVD的工艺获得。
  13. 根据权利要求12所述的一种高压倒装半导体发光元件，其特征在于：在所述透明隔离层以及互连线的表面直接通过离子源辅助镀膜工艺形成所述的布拉格反射层。
  14. 根据权利要求13所述的一种高压倒装半导体发光元件，其特征在于：所述的透明隔离层的致密性高于离子源辅助镀膜工艺所述的布拉格反射层的每一层致密性。
  15. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述的透明隔离层的厚度高于离子源辅助镀膜工艺所述的布拉格反射层的每一层厚度。
  16. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述的布拉格反射层为两层折射率不同的绝缘层重复堆叠形成的多层。
  17. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述的透明隔离层的厚度为100～1000nm。
  18. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：所述的透明导电层的厚度为10～200nm。
  19. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：第一导电类型半导体层具有一个第一台面，互连线与第一导电类型半导体层在第一台面上形成接触。
  20. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：相邻两个半导体发光元件之间通过互连线进行串联。
  21. 根据权利要求1所述的一种高压倒装半导体发光元件，其特征在于：还包括一个第一电极、第二电极，第二电极与一个半导体发光序列的透明导电层接触，第一电极与另外一个半导体发光序列的第一导电类型半导体层直接接触，互连线用于连接两个相邻半导体发光序列，一部分与一个半导体发光序列的第一导电类型半导体层直接接触，另一部分与另外一个半导体发光序列的透明导电层接触。
  22. 根据权利要求21所述一种高压倒装半导体发光元件，其特征在于：所述的半导体发光元件包括第一焊盘电极和第二焊盘电极，所述的布拉格反射层层具有第一开口和第二开口，第一焊盘电极和第二焊盘电极分别通过布拉格反射层层具有的第一开口和第二开口电连接所述的第一电极和第二电极。
  23. 一种背光显示模组，其包括权利要求1～22中任意一种高压倒装半导体发光元件。
  24. 一种显示装置，其包括权利要求24所述的背光显示模组。
  25. 根据权利要求1所述的一种显示装置，其特征在于：所述显示装置通过LOCAL DIMMING背光驱动电路实现局部调光。
  26. 一种RGB显屏，其包括权利要求1～22任意一种高压倒装半导体发光元件。
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