CN116190539A - 显示装置 - Google Patents

显示装置 Download PDF

Info

Publication number
CN116190539A
CN116190539A CN202310358401.3A CN202310358401A CN116190539A CN 116190539 A CN116190539 A CN 116190539A CN 202310358401 A CN202310358401 A CN 202310358401A CN 116190539 A CN116190539 A CN 116190539A
Authority
CN
China
Prior art keywords
electrode
pad
light emitting
display device
circuit substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310358401.3A
Other languages
English (en)
Inventor
白佳蕙
曾文贤
郭建宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW111143172A external-priority patent/TW202420584A/zh
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Publication of CN116190539A publication Critical patent/CN116190539A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0568—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/05686—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8322—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/83224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9221—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/053—Oxides composed of metals from groups of the periodic table
    • H01L2924/0549—Oxides composed of metals from groups of the periodic table being a combination of two or more materials provided in the groups H01L2924/0531 - H01L2924/0546
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示装置，包括：电路基板、多个接垫组以及多个发光元件。多个接垫组设置于电路基板上，且各接垫组包括第一接垫以及围绕第一接垫的第二接垫。多个发光元件设置于电路基板之上，且各发光元件包括第一电极、第二电极以及位于第一电极与第二电极之间的发光叠层，其中第一电极电性连接第一接垫，第二电极电性连接第二接垫，且第二电极于电路基板的正投影重叠第一接垫于电路基板的正投影。

Description

显示装置
技术领域
本发明涉及一种显示装置。
背景技术
微型发光二极管(Micro-LED)显示装置具有省电、高效率、高亮度及反应时间快等优点。一般而言，Micro-LED依其两电极在发光叠层的同一侧或不同侧可区分为水平式(Lateral)及垂直式(Vertical)Micro-LED，其中垂直式Micro-LED因散热及发光效率较佳，有望成为未来的主流结构。
由于垂直式Micro-LED的高度较高，且其两电极位在发光叠层的上、下两侧，在巨量转移(Mass Transfer)至电路基板上且将其下电极连接至电路基板上的对应接垫之后，需先形成平坦层来填补地形段差，之后再通过导电层将其上电极连接至电路基板上的另一接垫。然而，在平坦层或导电层的形成过程中，用于将平坦层或导电层图案化的蚀刻液会破坏下电极与对应接垫的连接，导致Micro-LED显示装置的可靠度不佳。
发明内容
本发明提供一种显示装置，具有提高的可靠度。
本发明的一个实施例提出一种显示装置，包括：电路基板；多个接垫组，设置于电路基板上，且各接垫组包括：第一接垫；以及第二接垫，围绕第一接垫；以及多个发光元件，设置于电路基板上，且各发光元件包括第一电极、第二电极以及位于第一电极与第二电极之间的发光叠层，其中第一电极电性连接第一接垫，第二电极电性连接第二接垫，且第二电极于电路基板的正投影重叠第一接垫于电路基板的正投影。
在本发明的一实施例中，上述的第一电极位于第一接垫与发光叠层之间。
在本发明的一实施例中，上述的第二电极从发光叠层的远离第一电极的顶面延伸至发光叠层的侧壁。
在本发明的一实施例中，上述的第二电极为透明导电层。
在本发明的一实施例中，上述的第二电极围绕发光叠层的侧壁。
在本发明的一实施例中，上述的显示装置还包括连接件，设置于第二接垫上，且连接件电性连接第二电极与第二接垫。
在本发明的一实施例中，上述的显示装置还包括第一绝缘层，位于第二电极与发光叠层的侧壁之间。
在本发明的一实施例中，上述的发光元件的尺寸大于第二接垫的内径。
在本发明的一实施例中，上述的第二电极仅位于发光叠层的远离第一电极的顶面。
在本发明的一实施例中，上述的显示装置还包括透明导电层，电性连接第二电极与第二接垫。
在本发明的一实施例中，上述的透明导电层覆盖第二电极、发光叠层的侧壁以及第二接垫。
在本发明的一实施例中，上述的透明导电层还延伸至第二接垫的远离发光元件的一侧。
在本发明的一实施例中，上述的多个接垫组的第二接垫相互连接。
在本发明的一实施例中，上述的发光元件的尺寸大于、等于或小于第二接垫的内径。
在本发明的一实施例中，上述的多个发光元件于电路基板上的最大高度实质上相等。
在本发明的一实施例中，上述的显示装置还包括第二绝缘层，位于第二接垫与电路基板之间，且具有多个开口，其中多个接垫组的第一接垫分别位于多个开口中。
在本发明的一实施例中，上述的发光元件的尺寸不小于开口的口径。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合说明书附图作详细说明如下。
附图说明
图1A是依照本发明一实施例的显示装置10的俯视图。
图1B是图1A的显示装置10的多个子像素PXs的放大示意图。
图1C是沿图1A的剖面线A-A’所作的剖面示意图。
图1D是依照本发明一实施例的显示装置10的制造方法的步骤流程的局部剖面示意图。
图2A是依照本发明一实施例的显示装置20的局部俯视图。
图2B是沿图2A的剖面线B-B’所作的剖面示意图。
图3是依照本发明一实施例的显示装置30的局部俯视图。
图4是依照本发明一实施例的显示装置40的局部剖面示意图。
图5A是依照本发明一实施例的显示装置50的局部俯视图。
图5B是沿图5A的剖面线C-C’所作的剖面示意图。
图6是依照本发明一实施例的显示装置60的局部俯视图。
图7是依照本发明一实施例的显示装置70的局部俯视图。
附图标记说明：
10,20,30,40,50,60,70：显示装置
110：电路基板
120,720：接垫组
121：第一接垫
122,722：第二接垫
130,130A,130B,130C,430,530：发光元件
131,431：第一电极
132,532：第二电极
133：发光叠层
133B：底面
133S：侧壁
133T：顶面
134：绝缘层
140：连接件
140’：连接图案
140B,140C：连接段
150：平坦层
460：连接件
570,670：透明导电层
A-A’,B-B’,C-C’：剖面线
D3：口径
DC：驱动元件
DW：尺寸
EL：发光层
H1,H2：高度
Ha,Hb,Hc：最大高度
I1：绝缘层
ID：内径
MT：巨量转移工艺
O1,O2,O3,O4：开口
PS：间距
PXs：子像素
RW：环宽度
SL1,SL2：半导体层
具体实施方式
在附图中，为了清楚起见，放大了层、膜、面板、区域等的厚度。在整个说明书中，相同的附图标记表示相同的元件。应当理解，当诸如层、膜、区域或基板的元件被称为在另一元件“上”或“连接到”另一元件时，其可以直接在另一元件上或与另一元件连接，或者中间元件可以也存在。相反地，当元件被称为“直接在另一元件上”或“直接连接到”另一元件时，不存在中间元件。如本文所使用的，“连接”可以指物理及/或电性连接。再者，“电性连接”或“耦接”可为二元件间存在其它元件。
应当理解，尽管术语“第一”、“第二”、“第三”等在本文中可以用于描述各种元件、部件、区域、层及/或部分，但是这些元件、部件、区域、层及/或部分不应受这些术语的限制。这些术语仅用于将一个元件、部件、区域、层或部分与另一个元件、部件、区域、层或部分区分开。因此，下面讨论的第一“元件”、“部件”、“区域”、“层”或“部分”可以被称为第二元件、部件、区域、层或部分而不脱离本文的教导。
这里使用的术语仅仅是为了描述特定实施例的目的，而不是限制性的。如本文所使用的，除非内容清楚地指示，否则单数形式“一”、“一个”和“该”旨在包括复数形式，包括“至少一个”或表示“及/或”。如本文所使用的，术语“及/或”包括一个或多个相关所列项目的任何和所有组合。还应当理解，当在本说明书中使用时，术语“包含”及/或“包括”指定所述特征、区域、整体、步骤、操作、元件及/或部件的存在，但不排除一个或多个其它特征、区域、整体、步骤、操作、元件、部件及/或其组合的存在或添加。
此外，诸如“下”或“底部”和“上”或“顶部”的相对术语可在本文中用于描述一个元件与另一元件的关系，如图所示。应当理解，相对术语旨在包括除了图中所示的方位之外的装置的不同方位。例如，如果一个附图中的装置翻转，则被描述为在其他元件的“下”侧的元件将被定向在其他元件的“上”侧。因此，示例性术语“下”可以包括“下”和“上”的取向，取决于附图的特定取向。类似地，如果一个附图中的装置翻转，则被描述为在其它元件“下”或“下方”的元件将被定向为在其它元件“上方”。因此，示例性术语“下”或“下方”可以包括上方和下方的取向。
考虑到所讨论的测量和与测量相关的误差的特定数量(即，测量系统的限制)，本文使用的“约”、“近似”、或“实质上”包括所述值和在本领域普通技术人员确定的特定值的可接受的偏差范围内的平均值。例如，“约”可以表示在所述值的一个或多个标准偏差内，或±30％、±20％、±10％、±5％内。再者，本文使用的“约”、“近似”、或“实质上”可依光学性质、蚀刻性质或其它性质，来选择较可接受的偏差范围或标准偏差，而可不用一个标准偏差适用全部性质。
除非另有定义，本文使用的所有术语(包括技术和科学术语)具有与本发明所属领域的普通技术人员通常理解的相同的含义。将进一步理解的是，诸如在通常使用的字典中定义的那些术语应当被解释为具有与它们在相关技术和本发明的上下文中的含义一致的含义，并且将不被解释为理想化的或过度正式的意义，除非本文中明确地这样定义。
本文参考作为理想化实施例的示意图的截面图来描述示例性实施例。因此，可以预期到作为例如制造技术及/或公差的结果的图示的形状变化。因此，本文所述的实施例不应被解释为限于如本文所示的区域的特定形状，而是包括例如由制造导致的形状偏差。例如，示出或描述为平坦的区域通常可以具有粗糙及/或非线性特征。此外，所示的锐角可以是圆的。因此，图中所示的区域本质上是示意性的，并且它们的形状不是旨在示出区域的精确形状，并且不是旨在限制权利要求的范围。
图1A是依照本发明一实施例的显示装置10的俯视图。图1B是图1A的显示装置10的多个子像素PXs的放大示意图。图1C是沿图1A的剖面线A-A’所作的剖面示意图。为了使附图的表达较为简洁，图1A示意性示出显示装置10的基板110、发光元件130、子像素PXs以及驱动元件DC，并省略其他构件。
请参照图1A至图1C，显示装置10包括：电路基板110；多个接垫组120，设置于电路基板110上，且各接垫组120包括：第一接垫121；以及第二接垫122，围绕第一接垫121；以及多个发光元件130，设置于电路基板110上，且各发光元件130包括第一电极131、第二电极132以及位于第一电极131与第二电极132之间的发光叠层133，其中第一电极131电性连接第一接垫121，第二电极132电性连接第二接垫122。
在本发明的一实施例的显示装置10中，通过使第二接垫122围绕第一接垫121，使得第二电极132与第二接垫122的电连接不需使用蚀刻工艺来形成，因此能够避免第一电极131与第一接垫121的电连接受到蚀刻工艺破坏，借此改善显示装置10的可靠度。以下，配合图1A至图1C，继续说明显示装置10的各个元件的实施方式，但本发明不以此为限。
具体而言，显示装置10可以包括多个子像素PXs，且多个子像素PXs可呈阵列排列，但本发明不以此为限。在一些实施例中，显示装置10还可以包括驱动元件DC，且驱动元件DC可以电性连接子像素PXs，以个别控制子像素PXs的操作。
举例而言，显示装置10的每个子像素PXs包括电路基板110、接垫组120以及发光元件130。接垫组120配置于电路基板110的表面上，且发光元件130的第一电极131电性连接至接垫组120的第一接垫121，发光元件130的第二电极132电性连接至接垫组120的第二接垫122，且驱动元件DC可以分别电性连接第一接垫121及第二接垫122。在一些实施例中，多个子像素PXs中的第一接垫121彼此分离，而独立地接收由驱动元件DC提供的信号。在一些实施例中，多个子像素PXs中的第二接垫122可彼此电性相连或是在操作时被施加相同的共用电压。在一些实施例中，驱动元件DC可为接合至电路基板110的芯片或直接形成于电路基板110中的电路元件(包含主动元件、被动元件或其组合)。
在一些实施例中，电路基板110可以包括设置于底板上的驱动电路结构，其中底板可以是透明基板或非透明基板，其材质可以是石英基板、玻璃基板、高分子基板或其他适当材质。驱动电路结构可包括显示装置10需要的元件或线路，例如驱动元件、开关元件、存储电容、电源线、驱动信号线、时序信号线、电流补偿线、检测信号线等等。
在一些实施例中，各个子像素PXs可以包括一组接垫组120，但本发明不限于此。在某些实施例中，各个子像素PXs可以包括两组或更多组接垫组120。如图1C所示，在一些实施例中，第一接垫121及第二接垫122可以属于不同膜层或位于不同平面上。举例而言，绝缘层I1局部覆盖第一接垫121，而第二接垫122设置于绝缘层I1上，以避免第一接垫121与第二接垫122之间产生电性连接。在某些实施例中，第一接垫121及第二接垫122可以属于相同膜层或位于相同平面上，且第一接垫121及第二接垫122的图案彼此分离。在一些实施例中，第一接垫121与第二接垫122可以具有不同电位。
请参照图1B，在一些实施例中，第一接垫121具有块状导电图案，例如矩形块状导电图案。在某些实施例中，第一接垫121具有圆形块状导电图案。在一些实施例中，第二接垫122具有环绕第一接垫121的矩形环状轮廓。在某些实施例中，第一接垫121可以重叠第二接垫122的矩形环状轮廓的中心。在一些实施例中，第二接垫122的环宽度RW介于1μm至3μm。在一些实施例中，第一接垫121与第二接垫122之间的间距PS小于发光元件130的尺寸DW的一半，即PS<1/2DW。
第一接垫121及第二接垫122可以具有单层结构或多层以上的导电层层叠的结构。举例而言，第一接垫121或第二接垫122为铝、钼、钛、铜等金属的单层金属层，但本发明不以此为限。在一些实施例中，第一接垫121或第二接垫122可以具有铝、钼、钛、铜等金属与铟锡氧化物(ITO)、铟锌氧化物(IZO)、铟镓锌氧化物(IGZO)或其他适合的导电氧化物层叠的结构。
请参照图1C，在一些实施例中，显示装置10的多个发光元件130包括发光元件130A、发光元件130B以及发光元件130C，且发光元件130A、发光元件130B以及发光元件130C于电路基板110上的最大高度Ha、最大高度Hb以及最大高度Hc彼此相近似。在一些实施例中，最大高度Ha、最大高度Hb以及最大高度Hc实质上彼此相等。在一些实施例中，发光元件130A、发光元件130B以及发光元件130C皆为蓝色发光二极管，且显示装置10另包括分别设置于发光元件130B及发光元件130C上的色转换层(图未示)，色转换层可以包括荧光粉或类似性质的波长转换材料，以让蓝色发光二极管所发出的蓝色光线转换成不同色彩的光线而实现全彩化的显示效果。在其他的实施例中，发光元件130A可以是蓝色发光二极管，发光元件130B可以是红色发光二极管，且发光元件130C可以是绿色发光二极管，借此实现全彩化的显示效果。当发光元件130A、发光元件130B以及发光元件130C的发光色彩彼此不同时，前述的色转换层可选择性地被省略或是保留于显示装置10中。在另外一些实施例中，发光元件130A、发光元件130B以及发光元件130C可以皆为白色发光二极管，而色转换层可以是彩色滤光层以实现全彩化的显示效果。
发光元件130的第一电极131及第二电极132可以分别电性连接发光叠层133中的不同层。举例而言，发光叠层133可以包括半导体层SL1、半导体层SL2以及夹于半导体层SL1与半导体层SL2之间的发光层EL，且第一电极131可电性连接半导体层SL1，而第二电极132可电性连接半导体层SL2。在一些实施例中，发光元件130为垂直式(Vertical)微型发光二极管。
在一些实施例中，发光元件130的第一电极131及发光叠层133在垂直方向上排列叠构，且发光元件130的第二电极132围绕发光叠层133的侧壁133S。在一些实施例中，第二电极132从发光叠层133的远离第一电极131的顶面133T延伸至发光叠层133的侧壁133S。在一些实施例中，第二电极132包覆发光叠层133的除底面133B以外的所有表面。在一些实施例中，第二电极132于电路基板110的正投影重叠第一电极131于电路基板110的正投影。在一些实施例中，第一电极131、第二电极132及发光叠层133于电路基板110的正投影相互重叠。
在一些实施例中，发光元件130还包括绝缘层134，且绝缘层134位于发光叠层133的侧壁133S与第二电极132之间，以避免第二电极132电性连接半导体层SL1。在一些实施例中，绝缘层134设置于发光叠层133的侧壁133S、顶面133T以及底面133B。在某些实施例中，绝缘层134包覆发光叠层133的所有表面且具有开口O1、O2，其中开口O1露出半导体层SL1，且第一电极131通过开口O1电性连接半导体层SL1；开口O2露出半导体层SL2，且第二电极132通过开口O2电性连接半导体层SL2。在一些实施例中，开口O1邻接发光叠层133的底面133B，且开口O2邻接发光叠层133的顶面133T。
在一些实施例中，第一电极131的材质包括金属、合金、金属材料的氮化物、金属材料的氧化物、金属材料的氮氧化物或其他合适的材料或是金属材料与其他导电材料的堆叠层或其他低阻值的材料。在某些实施例中，第一电极131的材质包括锡(Sn)、锡铅(SnPb)合金、铋锡(BiSn)合金及/或银锡(AgSn)合金。在一些实施例中，第二电极132为透明导电层。在某些实施例中，第二电极132的材质包括铟锡氧化物(InSnO)、铟锌氧化物(InZnO)、铝锡氧化物(AlSnO)、铝锌氧化物(AlZnO)、铟镓锌氧化物(InGaZnO)、纳米银或其他适合的导电氧化物。
在一些实施例中，半导体层SL1是N型掺杂半导体层，N型掺杂半导体层的材料例如是N型氮化镓(n-GaN)。在其他实施例中，半导体层SL1可以包括Ⅱ-Ⅵ族材料(例如：锌化硒(ZnSe))或Ⅲ-Ⅴ氮族化物材料(例如：氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铝铟镓(AlInGaN))。在一些实施例中，半导体层SL2是P型掺杂半导体层，P型掺杂半导体层的材料例如是P型氮化镓(p-GaN)。在其他实施例中，半导体层SL2可以包括Ⅱ-Ⅵ族材料(例如：锌化硒(ZnSe))或Ⅲ-Ⅴ氮族化物材料(例如：氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铝铟镓(AlInGaN))。在一些实施例中，发光层EL可以包括Ⅱ-Ⅵ族材料(例如：锌化硒(ZnSe))或Ⅲ-Ⅴ氮族化物材料(例如：氮化镓(GaN)、氮化铝(AlN)、氮化铟(InN)、氮化铟镓(InGaN)、氮化铝镓(AlGaN)或氮化铝铟镓(AlInGaN))。在一些实施例中，发光层EL的结构例如是多层量子井结构(Multiple Quantum Well,MQW)，多重量子井结构可以包括交替堆叠的多层氮化铟镓(InGaN)以及多层氮化镓(GaN)，通过设计发光层EL中铟或镓的比例，可以调整发光层EL的发光波长范围。
举例而言，发光元件130是于生长基板(例如蓝宝石基板)上制造后通过巨量转移工艺转置于电路基板110上，且发光元件130的第一电极131可被转置于第一接垫121上。在一些实施例中，第一电极131位于第一接垫121与发光叠层133之间。在一些实施例中，第一接垫121、第一电极131及发光叠层133于电路基板110的正投影相互重叠。在一些实施例中，第二电极132于电路基板110的正投影重叠第一接垫121于电路基板110的正投影。在某些实施例中，第一接垫121、第一电极131、发光叠层133及第二电极132于电路基板110的正投影相互重叠。在一些实施例中，第一电极131可以通过金属、导电胶或其他导电材料电性连接至第一接垫121。在一些实施例中，发光元件130的尺寸DW大于第二接垫122的内径ID。
在一些实施例中，显示装置10还包括连接件140，连接件140设置于第二接垫122上。在一些实施例中，连接件140包括热熔材料。如此一来，当发光元件130的发光叠层133的侧壁133S上的第二电极132位于第二接垫122上，第二接垫122上的连接件140经过热处理之后便能够将第二接垫122电连接至第二电极132。在某些实施例中，连接件140围绕发光元件130。在一些实施例中，连接件140于电路基板110的正投影在第二电极132于电路基板110的正投影之外。在一些实施例中，连接件140的材质包括锡(Sn)、锡铅(SnPb)合金、铋锡(BiSn)合金、银锡(AgSn)合金或其他焊料。
以下，使用图1D至图7继续说明本发明的其他实施例，并且，沿用图1A至图1C的实施例的元件标号与相关内容，其中，采用相同的标号来表示相同或近似的元件，并且省略了相同技术内容的说明。关于省略部分的说明，可参考图1A至图1C的实施例，在以下的说明中不再重述。
图1D是依照本发明一实施例的显示装置10的制造方法的步骤流程的局部剖面示意图。以下，配合图1C以及图1D说明显示装置10的制造方法。
请参照图1D，在一些实施例中，提供电路基板110，且电路基板110上形成有第一接垫121、局部覆盖第一接垫121的绝缘层I1、位于绝缘层I1上的第二接垫122以及位于第二接垫122的表面上的连接图案140’。
接着，可以将多个发光元件130(包括发光元件130A、发光元件130B以及发光元件130C)通过巨量转移工艺MT转置于电路基板110上，以使发光元件130的第一电极131位于第一接垫121上，且使连接图案140’邻接发光元件130的一侧。在一些实施例中，连接图案140’围绕发光元件130。在某些实施例中，连接图案140’不接触发光元件130。
接着，进行热处理，例如红外线激光处理，以使第一电极131热熔后附着于第一接垫121，且使连接图案140’热熔后延伸至第二电极132且附着于第二电极132而形成连接件140，如图1C所示。如此一来，第一电极131即可电连接第一接垫121，且第二电极132可通过连接件140电连接至第二接垫122。在一些实施例中，绝缘层134贴合第二接垫122，以避免连接件140与第一电极131电性连接。在一些实施例中，第一电极131实体连接第一接垫121。在一些实施例中，第一电极131热熔后还延伸至第一接垫121外侧。在一些实施例中，第一电极131热熔后可包覆第一接垫121。在一些实施例中，连接图案140’热熔后还延伸至第二接垫122外侧。
图2A是依照本发明一实施例的显示装置20的局部俯视图。图2B是沿图2A的剖面线B-B’所作的剖面示意图。显示装置20包括：电路基板110；多个接垫组120，设置于电路基板110上，且各接垫组120包括：第一接垫121；以及第二接垫122，围绕第一接垫121；多个发光元件130，设置于电路基板110上，且各发光元件130包括第一电极131、第二电极132以及位于第一电极131与第二电极132之间的发光叠层133；以及连接件140，其中第一电极131电性连接第一接垫121，且第二电极132通过连接件140电性连接第二接垫122。
与如图1A至图1C所示的显示装置10相比，图2A至图2B所示的显示装置20的不同之处主要在于：显示装置20还包括平坦层150，平坦层150位于第二接垫122与电路基板110之间，且平坦层150具有多个开口O3，其中多个接垫组120的第一接垫121分别设置于多个开口O3中。
在一些实施例中，绝缘层134贴合第二接垫122，以避免连接件140进入开口O3中与第一电极131电连接。在一些实施例中，发光元件130的尺寸DW不小于开口O3的口径D3，换句话说，尺寸DW≥口径D3，以避免第二电极132在热处理之后与第一电极131形成电性连接。在一些实施例中，第一电极131的高度H1大于平坦层150的高度H2。在一些实施例中，第一电极131的高度H1近似于或实质上等于平坦层150的高度H2。在一些实施例中，平坦层150的材质可以包括透明的绝缘材料，例如有机材料、亚克力(acrylic)材料、硅氧烷(siloxane)材料、聚酰亚胺(polyimide)材料、环氧树脂(epoxy)材料等。
在一些实施例中，连接件140包括多个连接段140B，且多个连接段140B彼此分离。在一些实施例中，多个连接段140B分别设置于发光元件130的不同侧边，且多个连接段140B分别电性连接位于发光元件130的不同侧边的第二电极132。
图3是依照本发明一实施例的显示装置30的局部俯视图。显示装置30包括：多个子像素PXs、多个接垫组120、多个发光元件130、多个连接件140以及平坦层150。与如图2A至图2B所示的显示装置20相比，图3所示的显示装置30的不同之处主要在于：连接件140包括多个连接段140C，多个连接段140C彼此分离，且多个连接段140C可以分别电性连接位于发光元件130的不同转角的第二电极132。
图4是依照本发明一实施例的显示装置40的局部剖面示意图。显示装置40包括：电路基板110、多个接垫组120、多个发光元件430、连接件140以及平坦层150。多个接垫组120设置于电路基板110上，且各接垫组120包括第一接垫121以及第二接垫122，其中第二接垫122围绕第一接垫121。多个发光元件430设置于电路基板110上，且各发光元件430包括第一电极431、第二电极132、发光叠层133以及绝缘层134，其中发光叠层133位于第一电极431与第二电极132之间，且绝缘层134位于第二电极132与发光叠层133之间。
与如图2A至图2B所示的显示装置20相比，图4所示的显示装置40的不同之处主要在于：发光元件430的第一电极431包括不受热处理(例如红外线激光处理)熔化的材料。举例而言，第一电极431的材质包括金(Au)或镍金(NiAu)合金。
在本实施例中，显示装置40还包括连接件460，连接件460位于第一电极431与第一接垫121之间，且连接件460将第一电极431电连接至第一接垫121。在一些实施例中，连接件460的材质包括焊料。在某些实施例中，连接件460的材质包括锡。
图5A是依照本发明一实施例的显示装置50的局部俯视图。图5B是沿图5A的剖面线C-C’所作的剖面示意图。显示装置50包括：电路基板110、多个接垫组120、多个发光元件530、以及平坦层150。多个接垫组120设置于电路基板110上，且各接垫组120包括第一接垫121以及第二接垫122，其中第二接垫122围绕第一接垫121。多个发光元件530设置于电路基板110上，且各发光元件530包括第一电极131、第二电极532、发光叠层133以及绝缘层134，其中发光叠层133位于第一电极131与第二电极532之间，绝缘层134包覆发光叠层133且具有开口O1、O2。发光叠层133包括半导体层SL1、半导体层SL2以及发光层EL，且发光层EL位于半导体层SL1与半导体层SL2之间。开口O1露出发光叠层133的半导体层SL1，且第一电极131通过开口O1电性连接半导体层SL1。开口O2露出发光叠层133的半导体层SL2，且第二电极532通过开口O2电性连接半导体层SL2。第一电极131电性连接第一接垫121，且第二电极532电性连接第二接垫122。平坦层150具有多个开口O3，且多个接垫组120的第一接垫121分别设置于多个开口O3中。
与如图2A至图2B所示的显示装置20相比，图5所示的显示装置50的不同之处主要在于：显示装置50并未包括连接件140，且显示装置50的发光元件530的第二电极532仅设置于绝缘层134的开口O2。换句话说，发光元件530的第二电极532仅设置于发光叠层133的顶面133T，且发光元件530的第二电极532未延伸至发光叠层133的侧壁133S。
在本实施例中，显示装置50还包括透明导电层570，透明导电层570覆盖于发光元件530的第二电极532的顶面与发光叠层133的侧壁133S，且透明导电层570电连接第二电极532与接垫组120的第二接垫122。在一些实施例中，第二电极532包含与透明导电层570的接触电阻较小的材料，例如锡、金、银(Ag)或铜(Cu)。在一些实施例中，在各子像素PXs中，透明导电层570完全覆盖接垫组120以及发光元件530。如此一来，即使使用蚀刻工艺来进行透明导电层570的图案化，接垫组120与发光元件530之间的电连接并不会受到蚀刻工艺破坏。
在一些实施例中，各子像素PXs中的透明导电层570彼此分离。在一些实施例中，各子像素PXs中的透明导电层570具有不同电位。在某些实施例中，透明导电层570还延伸至第二接垫122的远离发光元件530的一侧。透明导电层570的材质可以包括铟锡氧化物(InSnO)、铟锌氧化物(InZnO)、铝锡氧化物(AlSnO)、铝锌氧化物(AlZnO)、铟镓锌氧化物(InGaZnO)、纳米银或其他适合的导电氧化物。
在本实施例中，发光元件530的尺寸DW小于第二接垫122的内径ID，但本发明不限于此。在一些实施例中，发光元件530的尺寸DW等于第二接垫122的内径ID。在某些实施例中，发光元件530的尺寸DW大于第二接垫122的内径ID。在一些实施例中，发光元件530的尺寸DW大于或等于开口O3的口径D3，以避免透明导电层570进入开口O3中与发光元件530的第一电极131形成电连接。
图6是依照本发明一实施例的显示装置60的局部俯视图。显示装置60包括：多个接垫组120、多个发光元件530、具有多个开口O3的平坦层150以及透明导电层670。与如图5A至图5B所示的显示装置50相比，图6所示的显示装置60的不同之处主要在于：显示装置60的各子像素PXs中的透明导电层670彼此连接，换句话说，透明导电层670可以作为面电极，且各子像素PXs中的透明导电层670具有相同电位。如此一来，透明导电层670可以不需进行图案化工艺，例如蚀刻工艺。
图7是依照本发明一实施例的显示装置70的局部俯视图。显示装置70包括：多个接垫组720、多个发光元件530、具有多个开口O3的平坦层150以及透明导电层670。与如图6所示的显示装置60相比，图7所示的显示装置70的不同之处主要在于：显示装置70的各子像素PXs中的接垫组720包括第一接垫121以及第二接垫722，且各接垫组720的第二接垫722相互电性连接。在一些实施例中，各接垫组720的第二接垫722相互实体连接。在一些实施例中，第二接垫722可以是具有多个开口O4的面电极，且多个发光元件530分别位于多个开口O4中。
综上所述，本发明的显示装置通过使第二接垫围绕第一接垫，使得第二电极与第二接垫的电连接工艺能够利用热处理来实现，因此能够避免蚀刻工艺破坏第一电极与第一接垫的电连接，借此改善显示装置的可靠度。另外，本发明的显示装置还可在透明导电层完全覆盖接垫组以及发光元件之后再进行图案化，亦可避免蚀刻工艺破坏接垫组与发光元件之间的电连接。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的构思和范围内，当可作些许的变动与润饰，故本发明的保护范围当视权利要求所界定者为准。

Claims (17)

1.一种显示装置，包括：
电路基板；
多个接垫组，设置于所述电路基板上，且各接垫组包括：
第一接垫；以及
第二接垫，围绕所述第一接垫；以及
多个发光元件，设置于所述电路基板上，且各所述发光元件包括第一电极、第二电极以及位于所述第一电极与所述第二电极之间的发光叠层，
其中所述第一电极电性连接所述第一接垫，所述第二电极电性连接所述第二接垫，且所述第二电极于所述电路基板的正投影重叠所述第一接垫于所述电路基板的正投影。
2.如权利要求1所述的显示装置，其中所述第一电极位于所述第一接垫与所述发光叠层之间。
3.如权利要求1所述的显示装置，其中所述第二电极从所述发光叠层的远离所述第一电极的顶面延伸至所述发光叠层的侧壁。
4.如权利要求3所述的显示装置，其中所述第二电极为透明导电层。
5.如权利要求3所述的显示装置，其中所述第二电极围绕所述发光叠层的所述侧壁。
6.如权利要求3所述的显示装置，还包括连接件，设置于所述第二接垫上，且所述连接件电性连接所述第二电极与所述第二接垫。
7.如权利要求3所述的显示装置，还包括第一绝缘层，位于所述第二电极与所述发光叠层的所述侧壁之间。
8.如权利要求3所述的显示装置，其中所述发光元件的尺寸大于所述第二接垫的内径。
9.如权利要求1所述的显示装置，其中所述第二电极仅位于所述发光叠层的远离所述第一电极的顶面。
10.如权利要求9所述的显示装置，还包括透明导电层，电性连接所述第二电极与所述第二接垫。
11.如权利要求10所述的显示装置，其中所述透明导电层覆盖所述第二电极、所述发光叠层的侧壁以及所述第二接垫。
12.如权利要求11所述的显示装置，其中所述透明导电层还延伸至所述第二接垫的远离所述发光元件的一侧。
13.如权利要求9所述的显示装置，其中所述多个接垫组的所述第二接垫相互连接。
14.如权利要求9所述的显示装置，其中所述发光元件的尺寸大于、等于或小于所述第二接垫的内径。
15.如权利要求1所述的显示装置，其中所述多个发光元件于所述电路基板上的最大高度实质上相等。
16.如权利要求1所述的显示装置，还包括第二绝缘层，位于所述第二接垫与所述电路基板之间，且具有多个开口，其中所述多个接垫组的所述第一接垫分别位于所述多个开口中。
17.如权利要求16所述的显示装置，其中所述发光元件的尺寸不小于所述开口的口径。
CN202310358401.3A 2022-11-11 2023-04-06 显示装置 Pending CN116190539A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW111143172A TW202420584A (zh) 2022-11-11 顯示裝置
TW111143172 2022-11-11

Publications (1)

Publication Number Publication Date
CN116190539A true CN116190539A (zh) 2023-05-30

Family

ID=86447505

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310358401.3A Pending CN116190539A (zh) 2022-11-11 2023-04-06 显示装置

Country Status (2)

Country Link
US (1) US20240162402A1 (zh)
CN (1) CN116190539A (zh)

Also Published As

Publication number Publication date
US20240162402A1 (en) 2024-05-16

Similar Documents

Publication Publication Date Title
CN105679751B (zh) 晶片级发光二极管封装件及其制造方法
JP5847421B2 (ja) 発光素子、発光素子パッケージ
US11817435B2 (en) Light emitting device for display and LED display apparatus having the same
CN213845301U (zh) 显示用发光元件以及具有该显示用发光元件的单元像素
CN213845268U (zh) 显示器用发光元件
CN211605176U (zh) 发光芯片
KR20190007226A (ko) 발광소자 패키지 및 이를 이용한 디스플레이 장치
US11398462B2 (en) Light emitting device for display and light emitting package having the same
US11810944B2 (en) LED display apparatus
CN109273572B (zh) 半导体发光装置
EP4024452A1 (en) Led display device
KR102309092B1 (ko) 발광 소자 및 이를 포함하는 발광 소자 어레이
US11658275B2 (en) Light emitting device for display and LED display apparatus having the same
KR20170133758A (ko) 발광 소자
CN212934617U (zh) 发光元件及显示装置
KR102472353B1 (ko) 발광소자, 어레이 기판, 패널, 및 이를 포함하는 표시장치
CN116190539A (zh) 显示装置
US20240204037A1 (en) Projection device
TW202420584A (zh) 顯示裝置
KR102474301B1 (ko) 발광 소자
TWI836732B (zh) 光電半導體元件
KR20240092565A (ko) 투사 디바이스
CN114122236B (zh) 显示装置及其制造方法
CN113097360B (zh) 显示面板及其制造方法
US20230402437A1 (en) Light emitting device for display and led display apparatus having the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination