WO2024040448A1 - 线路板及制备方法、功能背板、背光模组、显示面板 - Google Patents

线路板及制备方法、功能背板、背光模组、显示面板 Download PDF

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Publication number
WO2024040448A1
WO2024040448A1 PCT/CN2022/114350 CN2022114350W WO2024040448A1 WO 2024040448 A1 WO2024040448 A1 WO 2024040448A1 CN 2022114350 W CN2022114350 W CN 2022114350W WO 2024040448 A1 WO2024040448 A1 WO 2024040448A1
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WIPO (PCT)
Prior art keywords
layer
sub
base substrate
circuit board
protection
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PCT/CN2022/114350
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English (en)
French (fr)
Inventor
姚念琦
刘英伟
袁广才
宁策
李正亮
曹占锋
王珂
赵坤
齐琪
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280002770.2A priority Critical patent/CN117941072A/zh
Priority to PCT/CN2022/114350 priority patent/WO2024040448A1/zh
Publication of WO2024040448A1 publication Critical patent/WO2024040448A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a circuit board and a preparation method, a functional backplane, a backlight module, a display panel, and a display device.
  • Sub-millimeter light-emitting diode refers to a light-emitting diode with a size between 80 ⁇ m and 200 ⁇ m.
  • Mini-LED When Mini-LED is used as the pixel point of the display panel to form a self-luminous display, a higher pixel density can be achieved compared to a small-pitch LED display.
  • Mini-LED When Mini-LED is used as a light source in a backlight module, an ultra-thin light source module can be produced through a denser light source arrangement; coupled with local dimming technology, display devices including Mini-LED backlight modules ( For example, mobile phones, etc.) will have better contrast and high dynamic lighting rendering display effects.
  • Micro-Light Emitting Diode Micro-Light Emitting Diode (Micro-LED) is a light-emitting diode with a size less than 80 ⁇ m, which can be directly used as a pixel point of a display panel in a display device.
  • a circuit board including: a base substrate, an active pattern layer and an electrical pattern layer.
  • the active pattern layer is disposed on one side of the base substrate and includes a plurality of active patterns.
  • the electrical pattern layer is disposed on a side of the active pattern layer away from the base substrate, and includes a plurality of connection parts, at least one connection part being coupled to the active pattern.
  • connection part includes a plurality of first sub-layers stacked along the thickness direction of the base substrate, and the two first sub-layers furthest away from the base substrate among the plurality of first sub-layers are respectively the first conductive sub-layer and the third A protection sub-layer, the first protection sub-layer is disposed on a side of the first conductive sub-layer away from the base substrate, and the material of the first protection sub-layer includes nickel.
  • the first welding material and at least a part (eg part, or all) of the first protection sub-layer form the first intermetallic compound
  • the first intermetallic compound and the portion of the first protection sub-layer where the first intermetallic compound is not formed The first welding material is partially blocked to a certain extent, so that the diffusion speed of the first welding material is slowed down, thereby effectively preventing the first welding material from diffusing into the first conductive sublayer.
  • the welding is defective (such as a weak solder or the position of the electronic component is shifted) and maintenance is required, the first conductive sublayer will not be easily removed during the removal of the electronic component, and the first conductive sublayer will not be caused.
  • the lack of electronic layers improves repairability.
  • the material of the first protection sub-layer is pure nickel, or the material of the first protection sub-layer is a nickel alloy with an atomic percentage of nickel greater than or equal to 40%.
  • the material of the first protective sub-layer further includes at least one of tungsten, vanadium, palladium, aluminum, titanium, zirconium, molybdenum, copper, yttrium, niobium, platinum, tin, tantalum, gold and silver.
  • the thickness of the first protective sub-layer is
  • the plurality of first sub-layers further include: at least one second protection sub-layer provided on a side of the first conductive sub-layer close to the base substrate.
  • the material of the second protective sub-layer includes nickel.
  • the plurality of first sub-layers further include: at least one second conductive sub-layer disposed on a side of the first conductive sub-layer close to the base substrate.
  • the second conductive sub-layer and the second protective sub-layer are alternately arranged, and a second protective sub-layer is in contact with the first conductive sub-layer.
  • the material of the second protective sub-layer contains the same composition as the material of the first protective sub-layer.
  • the atomic percentage of nickel in the material of the second protection sub-layer is less than or equal to the atomic percentage of nickel in the material of the first protection sub-layer.
  • the plurality of first sub-layers further include a first buffer sub-layer, which is the one closest to the substrate among the plurality of first sub-layers; the material of the first buffer sub-layer is different from the first protective layer.
  • the material of the sub-layer and the material of the first conductive sub-layer each contain different compositions.
  • the material of the first buffer sub-layer includes at least one of molybdenum-niobium alloy, molybdenum-nickel-titanium alloy, molybdenum, molybdenum alloy, titanium and titanium-copper alloy.
  • the ratio of the areas of orthographic projections of any two first sub-layers among the plurality of first sub-layers on the base substrate is 0.9 to 1.1.
  • connection part includes a bottom surface and a side surface.
  • the bottom surface is the surface of the connection part that is closest to and parallel to the base substrate; the side surface is adjacent to the bottom surface; wherein the angle between the side surface and the bottom surface is 40° to 90°.
  • the circuit board further includes: a transfer part disposed between the electrical pattern layer and the active pattern layer, and the transfer part is coupled to the active pattern and the connection part.
  • the transfer part includes at least one of a first protection sub-layer and a second protection sub-layer, and a transfer sub-layer; wherein the first protection sub-layer is stacked on a side of the transfer sub-layer close to the base substrate. side, and the material of the first protection sub-layer includes nickel; the second protection sub-layer is stacked on the side of the transfer sub-layer away from the base substrate, and the material of the second protection sub-layer includes nickel.
  • the circuit board further includes: a gate pattern layer.
  • the gate pattern layer is disposed on the base substrate and includes a plurality of gate electrodes; the gate electrode includes at least one of a third protection sub-layer and a fourth protection sub-layer, and a gate conductive sub-layer; wherein the third protection sub-layer is stacked On the side of the gate conductive sublayer close to the base substrate, the material of the third protection sublayer includes nickel; the fourth protection sublayer is stacked on the side of the gate conductive sublayer away from the base substrate, and the fourth protection sublayer Materials include nickel.
  • the gate pattern layer is disposed between the active pattern layer and the base substrate, and includes a plurality of gate electrodes, and the orthographic projection of the gate electrodes on the base substrate covers the channel area of the active pattern on the base substrate.
  • the electrical pattern layer further includes: a light-shielding portion, the orthographic projection of the light-shielding portion on the base substrate covers the orthographic projection of the channel region of the active pattern on the base substrate; the light-shielding portion includes a plurality of second sub-layers arranged in a stack; along the Perpendicular to the direction of the base substrate, the second sub-layer and the first sub-layer in the same stacking sequence are made of the same material.
  • a functional backplane including: the above-mentioned circuit board and electronic components.
  • the circuit board has a device area and a bonding area.
  • the electronic components are arranged on a side of the electrical pattern layer away from the base substrate.
  • the connection portion of the electrical pattern layer located in the device area is coupled to the electronic component through a first soldering material, wherein a portion of the first protection sub-layer located at the connection portion of the device area close to the first soldering material is formed with the first soldering material The first intermetallic compound.
  • the electronic component includes a light emitting device, a driving component or a sensing device.
  • the functional backplane also includes: a circuit board.
  • the circuit board and the connecting portion located in the binding area are coupled through the second soldering material; wherein, the portion of the first protective sub-layer of the connecting portion located in the binding area close to the second soldering material forms a second metal gap with the second soldering material. compound.
  • a backlight module including: the above-mentioned functional backplane, and the electronic components are light-emitting devices.
  • Another aspect provides a display module, including: the above-mentioned functional backplane, and the electronic components are light-emitting devices.
  • Another aspect provides a display device, including: the above-mentioned backlight module or display module.
  • Another aspect provides a circuit board preparation method, including:
  • An active pattern layer is formed on the base substrate, and the active pattern layer includes a plurality of active patterns.
  • An electrical pattern layer is formed on the base substrate on which the active pattern layer is formed.
  • the electrical pattern layer includes a plurality of connection parts, and the connection parts are coupled to the active pattern; wherein the connection parts include a plurality of first sub-layers arranged in a stack, Among the plurality of first sub-layers, the two first sub-layers furthest away from the base substrate are respectively the first conductive sub-layer and the first protective sub-layer.
  • the first protective sub-layer is disposed on the first conductive sub-layer far away from the base substrate. On one side, the material of the first protective sub-layer includes nickel.
  • Figure 1 is a structural diagram of a display device according to some embodiments.
  • Figure 2 is a structural diagram of another display device according to some embodiments.
  • Figure 3 is a structural diagram of a functional backplane according to some embodiments.
  • Figure 4 is a circuit diagram of a pixel circuit according to some embodiments.
  • Figure 5 is the corresponding timing control diagram of the pixel circuit.
  • Figure 6 is a structural diagram of a laminate structure of a circuit board and the relative positions of electronic components on the circuit board according to some embodiments.
  • Figure 7a is a bonding diagram of tin, pad and nickel according to some embodiments.
  • Figure 7b is a bonding diagram of tin, pad and tungsten according to some embodiments.
  • Figure 8a is a tabular plot of reflectance versus wavelength for nickel according to some embodiments.
  • Figure 8b is a tabular plot of reflectivity versus wavelength for copper in accordance with some embodiments.
  • Figure 9a is a histogram of resistivity versus temperature for nickel according to some embodiments.
  • Figure 9b is a histogram of copper resistivity versus temperature, according to some embodiments.
  • Figure 10 is an enlarged view of Figure 6 at the second connection portion.
  • Figure 11 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 12 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 13 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 14 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 15 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 16 is an enlarged view of Figure 15 at the second connection portion.
  • Figure 17 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 18 is an enlarged view of Figure 17 at the second connection portion.
  • Figure 19 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 20 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 21 is an enlarged view of Figure 20 at the second connection portion.
  • Figure 22 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 23 is an enlarged view of Figure 22 at the second connection portion.
  • Figure 24 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 25 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 26 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 27 is a structural diagram of another laminate structure of a circuit board according to some embodiments.
  • Figure 28a is a structural diagram of a laminate structure of a functional backplane according to some embodiments.
  • Figure 28b is an enlarged view of Figure 28a at J.
  • Figure 29 is a structural diagram of another laminate structure of a functional backplane according to some embodiments.
  • Figure 30 is a structural diagram of another laminate structure of a functional backplane according to some embodiments.
  • Figure 31 is a flow chart of a method for manufacturing a circuit board according to some embodiments.
  • Figures 32 to 37 are process step diagrams of the circuit board preparation method.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • a display device which may be any device that displays text or images, whether moving (eg, video) or stationary (eg, still images).
  • the display device may include, for example, a mobile phone (Mobile Phone), a tablet computer (Pad), a notebook computer, a television, a personal digital assistant (Personal Digital Assistant, PDA), an ultra-mobile personal computer (Ultra-Mobile Personal Computer, UMPC). ), netbooks, wearable devices (such as smart watches), virtual reality (VR) display devices, augmented reality (AR) display devices or vehicle-mounted display devices, etc.
  • This embodiment does not limit the type of display device .
  • the display device includes a display module 1 and may also include a frame (such as a middle frame, etc.).
  • Display module 1 is a component configured to display a screen.
  • the frame is configured to fix display module 1.
  • the display module 1 includes a functional backplane 10 for displaying images.
  • the functional backplane 10 may be called a display substrate or a display panel.
  • the display panel can be a self-luminous display panel such as Mini-LED or Micro-LED display panel.
  • the functional backplane 10 includes a circuit board D1 and electronic components D2.
  • the electronic component D2 may be a light-emitting device, such as Mini-LED or Micro-LED.
  • the circuit board D1 has a device area SA and a bonding area SS. Among them, the device area SA of the circuit board D1 constitutes a display area (that is, an area used for displaying images), and the light-emitting device can be coupled to the display area of the circuit board D1.
  • the circuit board D1 is configured to receive the data signal and control the brightness of the light-emitting device based on the data signal to achieve a display screen.
  • the functional backplane 10 may also include a circuit board D3, which may be a Flexible Printed Circuit (FPC), for example.
  • the circuit board D3 is coupled to the circuit board D1.
  • the circuit board D3 can be bound to the binding area SS of the circuit board D1.
  • the display module 1 may also include a driver circuit 20, which may be a driver IC, for example, a source driver IC or a display driver circuit (Display Driver Integrated Circuit, DDIC).
  • the driving circuit 20 is coupled to the functional backplane (ie, the display panel) 10 and is configured to provide data signals to the functional backplane 10 .
  • the driving circuit 20 can be disposed on the circuit board D3 and coupled with the circuit board D1 through the circuit board D3 to send data signals to the circuit board D1.
  • the display device includes a display panel 2 and may also include a backlight module 3 .
  • the display panel 2 may be a liquid crystal display panel.
  • the display panel 2 has a display area AA and a binding area (referred to as the first binding area in this embodiment) SS1.
  • the display area AA is an area used for displaying pictures
  • the first binding area SS1 is used for connecting to the circuit board. (eg, flexible circuit board) coupling area, where the first binding area SS1 may be distributed on at least one side (eg, one side, or multiple sides) of the display area AA.
  • the backlight module 3 is configured to provide a light source to the display panel 2 .
  • the backlight module 3 includes a functional backplane 10 for providing a light source.
  • the functional backplane 10 may be called a light-emitting substrate.
  • the functional backplane 10 includes a circuit board D1 and electronic components D2.
  • the electronic component D2 may be a light-emitting device, such as Mini-LED or Micro-LED.
  • the circuit board D1 has a device area SA and a bonding area SS.
  • the device area SA of the circuit board D1 is an area used for emitting light.
  • the area of the device area SA of the circuit board D1 may be larger than or equal to the display area AA of the display panel 2 .
  • the orthographic projection of the display area AA of the display panel 2 on the circuit board D1 falls within the range of the device area SA of the circuit board D1 , so that each pixel in the display area AA of the display panel 2 All can be illuminated by the light emitted by the light-emitting devices in the device area, so that the display panel 2 can display.
  • each light-emitting group may include at least one electronic component D2.
  • each lighting group may include one electronic component D2.
  • each light-emitting group includes at least two electronic components D2 connected in series.
  • the circuit board D1 is configured to receive the dimming signal and control the lighting brightness of each electronic component D2 in each lighting group based on the dimming signal.
  • the functional backplane 10 may also include a circuit board D3, which may be a flexible circuit board, for example.
  • the circuit board D3 is coupled to the circuit board D1.
  • the circuit board D3 can be bound to the binding area (called the second binding area in this embodiment) SS2 of the circuit board D1.
  • the relative position of the second bonding area SS2 and the device area SA on the circuit board D1 is the same as the relative position of the first bonding area SS1 and the display area AA on the display panel 2 .
  • the second binding area SS2 is located on the right side of the device area SA
  • the first binding area SS1 is also located on the right side of the display area AA, which is beneficial to reducing the frame of the display device.
  • the backlight module 3 may also include a dimming circuit 30 coupled to the functional backplane (ie, the light-emitting substrate) 10 and configured to provide a dimming signal to the functional backplane 10 .
  • the dimming circuit 30 can be disposed on the circuit board D3 and coupled with the circuit board D1 through the circuit board D3 to send the dimming signal to the circuit board D1.
  • the type of the electronic component D2 in the functional backplane 10 shown in FIG. 1 or 2 above can be changed to achieve corresponding functions.
  • the electronic component D2 in the functional backplane 10 may also be a driving component (for example, a driver or a driving chip, etc.) or a sensing component.
  • the sensing device may be a photosensitive element (such as a photodiode), a pressure sensitive element or a temperature sensing element.
  • the electronic component D2 may be a photosensitive component, and the functional backplane 10 including such electronic component D2 may be applied to electronic devices such as fingerprint readers.
  • the functional backplane 10 mentioned above is introduced in detail below.
  • the functional backplane 10 includes a circuit board D1 and a plurality of electronic components D2 disposed on the circuit board D1 and electrically connected to the circuit board D1 .
  • the circuit board D1 is configured to provide an electrical signal (such as current or voltage) to each electronic component D2 to drive the electronic component D2 to operate.
  • the circuit board D1 may include multiple pixel circuits Q (which may also be referred to as minimum repetition driving circuits).
  • a pixel circuit Q is electrically connected to an electronic component D2 and is configured to provide an electrical signal to the electronic component D2.
  • the size of the electrical signal provided by the pixel circuit Q can be adjusted, so that the working state of the electronic component D2 is adjustable.
  • the electronic component D2 is a light-emitting device
  • a pixel circuit Q is electrically connected to a light-emitting device and is configured to provide an electrical signal with adjustable size to the light-emitting device, so that the brightness of the light-emitting device is adjustable.
  • the pixel circuit Q may include a plurality of transistors and at least one (such as one, or a plurality of) capacitors, and the like.
  • each pixel circuit Q may include three transistors and a capacitor, forming a 3T1C structure. It can also include more than three transistors and at least one capacitor, such as a 4T1C structure (i.e., four transistors and a capacitor), a 5T1C structure (i.e., five transistors and a capacitor), or a 7T1C structure (i.e., seven transistors and a capacitor). wait.
  • the transistors in the embodiments of the present disclosure are exemplified by thin film transistors, but are not limited to thin film transistors and may also be field effect transistors.
  • the transistor includes: a gate, a source, a drain, and an active pattern connected between the source and the drain.
  • the material of the active pattern may include an oxide semiconductor.
  • the oxide semiconductor may include indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium zinc tin oxide (Indium Gallium Tinc Oxide, IGTO), indium zinc oxide (Indium Zinc Oxide, IZO) and C-Axis Aligned Crystalline (CAAC) structure, etc.; correspondingly, the transistor can be an oxide transistor (also called an oxide thin film transistor) .
  • the material of the active pattern may also include polysilicon (P-Si); accordingly, the transistor may be a polysilicon transistor.
  • the active pattern can exhibit conductive properties driven by voltages at the gate and source, causing the source and drain to be turned on; or, exhibit insulating properties, causing the source and drain to be disconnected.
  • a layer including a plurality of active patterns will be referred to as an active pattern layer below.
  • all transistors in the pixel circuit Q are of the same type, for example, all are oxide transistors or all are polysilicon transistors. In other embodiments, there are at least two types of transistors in the pixel circuit Q.
  • the pixel circuit Q may include some oxide transistors and some polysilicon transistors.
  • each transistor in the pixel circuit Q may be a P-type transistor. It should be noted that embodiments of the present disclosure include but are not limited to this.
  • one or more transistors in the pixel circuit Q provided by the embodiments of the present disclosure can also be N-type transistors. It is only necessary to refer to each pole of the N-type transistor with reference to each pole of the corresponding P-type transistor in the embodiments of the present disclosure. The poles are connected accordingly, and the corresponding high level is applied to the corresponding gate.
  • the pixel circuit Q includes: a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 and a capacitor C.
  • the third transistor T3 may be a driving transistor.
  • the gate of the third transistor T3 is coupled to the N node.
  • Each transistor includes a gate electrode, a first electrode, and a second electrode.
  • one of the first electrode and the second electrode is the source electrode, and the other is the drain electrode.
  • the first pole is the drain and the second pole is the source.
  • the gate of the third transistor T3 is coupled to the N node.
  • the gate electrode of the first transistor T1 is coupled to the first reset signal terminal G3, the first electrode is coupled to the initialization signal terminal Vinit, and the second electrode is coupled to the N node.
  • the gate electrode of the second transistor T2 is coupled to the gate line G1, the first electrode is coupled to the second electrode of the third transistor T3, and the second electrode is coupled to the N node.
  • the gate electrode of the fourth transistor T4 is coupled to the gate line G1, the first electrode is coupled to the data line DL, and the second electrode is coupled to the first electrode of the third transistor T3.
  • the gate electrode of the fifth transistor T5 is coupled to the light-emitting control signal terminal EM, the first electrode is coupled to the first power supply voltage terminal VDD, and the second electrode is coupled to the first electrode of the third transistor T3.
  • the gate electrode of the sixth transistor T6 is coupled to the light emission control signal terminal EM, the first electrode is coupled to the second electrode of the third transistor T3, and the second electrode is coupled to the first electrode (eg anode) of the electronic component D2.
  • the second electrode (eg cathode) in the electronic component D2 is coupled to the second power supply voltage terminal VSS.
  • the gate electrode of the seventh transistor T7 is coupled to the second reset signal terminal G2, the first electrode is coupled to the initialization signal terminal Vinit, and the second electrode is coupled to the first electrode of the electronic component D2.
  • One end of the capacitor C is coupled to the N node, and the other end is coupled to the first power supply voltage terminal VDD.
  • the voltage provided by the first power supply voltage terminal VDD may be greater than the voltage provided by the second power supply voltage terminal VSS, and may also be greater than the voltage provided by the initialization signal terminal Vinit.
  • the gate line G1, the first reset signal terminal G3, and the second reset signal terminal G2 may each provide their own signals, that is, the signals provided by the three may be different.
  • the first reset signal terminal G3 and the second reset signal terminal G2 can provide the same signal. At this time, they can be coupled; the signals provided by the two are different from the signals provided by the gate line G1.
  • the second reset signal terminal G2 and the gate line G1 may provide the same signal, and at this time, they may be coupled; the signals provided by the two are different from the signal provided by the first reset signal terminal G3.
  • the working process of the above-mentioned pixel circuit Q includes, for example, the following stages:
  • Reset phase (S1 phase): The first transistor T1 is turned on in response to the signal provided by the first reset signal terminal G3, thereby transmitting the signal provided by the initialization signal terminal Vinit (for example, it can be called an initialization signal) to the N node to The node is reset.
  • Vinit for example, it can be called an initialization signal
  • Both the second transistor T2 and the fourth transistor T4 can be turned on in response to the scan signal provided by the gate line G1, thereby writing the data signal (for example, marked Vdate) provided by the data line DL to N node starts charging the capacitor C at the same time.
  • the voltage of the N node may be the compensated data signal, for example, Vdate+Vth, where Vth is the threshold voltage of the third transistor.
  • the seventh transistor T7 is turned on in response to the signal provided by the second reset signal terminal G2, thereby transmitting the initialization signal provided by the initialization signal terminal Vinit to the first electrode of the electronic component D2 to reset the first electrode of the electronic component D2.
  • Both the fifth transistor T5 and the sixth transistor T6 can be turned on in response to the signal provided by the light-emitting control signal terminal EM, so that from the first power supply voltage terminal VDD, through the fifth transistor T5, the third The path from the transistor T3, the sixth transistor T6, and the electronic component D2 to the second power supply voltage terminal VSS is turned on, so that the electronic component D2 can work (for example, emit light).
  • the transistors in the above-mentioned pixel circuit Q may all be polysilicon transistors.
  • the first transistor T1 and the second transistor T2 in the above-mentioned pixel circuit Q can be oxide thin film transistors to reduce the leakage current at the first transistor T1 and the second transistor T2, thereby making the N node Voltage is maintained better; other transistors can be polysilicon transistors.
  • the pins of the electronic component D2 and the connection portion (also called the pad P) of at least part of the exposed surface of the circuit board D1 are fixedly connected through a soldering material through a process such as reflow soldering or dip soldering.
  • a soldering material needs to be provided on the surface of the connection part (called the first soldering material T, such as a material containing metal tin), or a soldering material needs to be provided on the pin of the electronic component D2 material, and then align and contact the pins of the electronic component D2 with the connection part.
  • the soldering material is melted and well moistened with the connection part, and then quickly cooled down, so as to The electronic component D2 is fixedly connected to the circuit board D1.
  • connection part on the circuit board D1 prevents the connection part from being soldered to the electronic component D2 again.
  • Figure 6 shows a laminate structure of a circuit board and the relative positions of electronic components on the circuit board.
  • the circuit board D1 includes: a base substrate 100 , an active pattern layer 400 and an electrical pattern layer 300 .
  • the base substrate 100 may be a rigid substrate.
  • the rigid substrate may include, for example, a glass substrate, a quartz substrate, or a plastic substrate.
  • the circuit board D1 is rigid.
  • the base substrate 100 may also be a flexible substrate.
  • the flexible substrate may include, for example, a polyimide substrate, a polymethyl methacrylate substrate, a polyethylene naphthalate substrate, or the like. In this case, the circuit board D1 is flexible.
  • the base substrate 100 may have a one-layer structure or a multi-layer structure.
  • the base substrate 100 may include at least one flexible substrate and at least one buffer layer, and the flexible substrate and the buffer layer are alternately stacked.
  • the active pattern layer 400 is disposed on one side of the base substrate 100 .
  • the active pattern layer 400 includes a plurality of active patterns 410, and one active pattern 410 is, for example, the active pattern 410 of the transistor in the above-mentioned pixel circuit Q.
  • the transistor may be a polysilicon transistor, and the transistor (or the active pattern layer 400) has an active region, a first electrode region 420 and a second electrode region 430 located on opposite sides of the active region.
  • the portion of the active pattern layer 400 located in the active area may be referred to as the active pattern 410 .
  • One of the first electrode region 420 and the second electrode region 430 is a source region (can be used as a source), and the other is a drain region (can be used as a drain); the materials of the two can be Doped polysilicon becomes conductive.
  • the electrical pattern layer 300 is disposed on a side of the active pattern layer 400 away from the base substrate 100 .
  • the electrical pattern layer 300 includes a plurality of connections. At least one (eg, one, or multiple) connection portion is coupled to an active pattern 410 .
  • the connection part coupled with the active pattern 410 may be called the first connection part 300a.
  • first connection part 300a coupled to an active pattern 410.
  • the first connection portion 300a may be coupled to any one of the first pole region 420 and the second pole region 430 located on both sides of the active pattern 410.
  • a first connection portion 300a is coupled to a second electrode region 430; based on this, when the transistor including the active pattern 410 is operating, the first connection portion 300a can have the same potential as the second electrode region 430, Therefore, the equivalent circuit of the pixel circuit Q can be equivalent to the same point.
  • first connection portions 300a coupled to an active pattern 410; one of the first connection portions 300a is coupled to the first pole region 420 located on one side of the active pattern 410, and in addition A first connection portion 300a is coupled to the second pole region 430 located on the other side of the active pattern 410.
  • the electronic component D2 may include a pin coupled to at least one active pattern 410, called a first pin (eg, anode) D21; specifically, the first pin D21 may be coupled to a first connection portion 300a, and The first connection portion 300a is coupled to at least one active pattern 410 .
  • the electronic component D2 may also include other pins, such as a second pin (eg, negative electrode) D22.
  • the plurality of connection portions in the electrical pattern layer 300 may further include a connection portion coupled to the second pin D22 of the electronic component D2, which is referred to as the second connection portion 300b.
  • the second connection part 300b may be coupled to the second power supply voltage terminal VSS in FIG. 4 , so that the second pin D22 of the electronic component D2 is coupled to the second power supply voltage terminal VSS through the second connection part 300b.
  • the plurality of connection parts in the electrical pattern layer 300 may include a third connection part 300c.
  • the third connection portion 300c is coupled to the first power supply voltage terminal VDD in FIG. 4 and is configured to provide a power supply voltage (for example, a power supply voltage supplied to the anode of the electronic component D2) to the above-mentioned pixel circuit Q.
  • the connection part (the first connection part 300a, the second connection part 300b or the third connection part 300c) includes a plurality of first sub-layers stacked along the thickness direction of the base substrate 100 (X direction as shown in FIG. 6) .
  • the two first sub-layers farthest from the base substrate 100 are respectively the first conductive sub-layer 320 and the first protective sub-layer 310.
  • the first The protection sub-layer 310 is disposed on a side of the first conductive sub-layer 320 away from the base substrate 100 .
  • the connection part includes two first sub-layers, namely a first conductive sub-layer 320 and a first protective sub-layer 310.
  • connection part includes more than three (such as three, four, five or more) first sub-layers, for example, from top to bottom, they are the first protective sub-layer 310, the first conductive sub-layer 320 and at least an other sublayer.
  • the first protective sub-layer 310 is disposed on a side of the first conductive sub-layer 320 away from the base substrate 100 .
  • the first soldering material T (mainly composed of tin (Sn)) can be used.
  • the pins of the electronic component D2 (for example, the first pin D21 and the second pin D22) and the first protective sub-layer 310 are welded.
  • the first soldering material T and the first protective sub-layer 310 form a first intermetallic compound.
  • the first soldering material T and the pin of the electronic component D2 form a third intermetallic compound, thereby realizing the electronic component D2 Soldering to circuit board D1.
  • Intermetallic Compound Compounds formed between metals and metals or metals and metalloids (such as H, B, N, S, P, C, Si, etc.) are called intermetallic compounds (Intermetallic Compound, abbreviated as IMC).
  • IMC Intermetallic Compound
  • the elements in intermetallic compounds are bonded by metallic bonds to maintain metallic properties.
  • Intermetallic compounds are products of interfacial reactions.
  • the first soldering material T is first melted under heating; then, the material of the first protection sub-layer 310 is melted.
  • the material of the pin of the electronic component is also melted; subsequently, the metal atoms in the first welding material T react with the metal atoms in the first protective sub-layer 310 and the metal atoms in the pin respectively while diffusing, and The metal atoms in the first protection sub-layer 310 form a first intermetallic compound, and the metal atoms in the lead form a third intermetallic compound.
  • the metal atoms in the first welding material T may also form a fourth intermetallic compound with the metal atoms in the first conductive sublayer 320 .
  • intermetallic compounds are related to the composition, melting point, temperature and reaction time of the material.
  • the original contact interface between the two metal layers will move. Usually the interface will move toward the film layer of the metal with the larger diffusion coefficient.
  • the film layer where metals with large diffusion coefficients are located will also form nano- or micron-sized cavities or gaps.
  • the first intermetallic compound and the first protection sub-layer 310 are not formed with a first intermetallic compound.
  • a part of the intermetallic compound blocks the first soldering material T to a certain extent, so that the diffusion speed of the first soldering material T is slowed down, thereby effectively preventing the first soldering material T from diffusing into the first conductive sublayer 320 .
  • the material of the first conductive sublayer 320 includes copper, for example, pure copper or a copper alloy. However, copper or copper alloys are more susceptible to oxidation.
  • the first protection sub-layer 310 has an anti-oxidation performance higher than that of the first conductive sub-layer 320 .
  • the material of the first protection sub-layer 310 includes nickel.
  • the material of the first protection sub-layer 310 may not include copper.
  • the material of the first protection sub-layer 310 may include copper; and in the first protection sub-layer 310, the atomic percentage of copper is less than the atomic percentage of nickel.
  • the material of the first protective sub-layer 310 is pure nickel (Ni).
  • the material of the first protective sub-layer 310 is nickel alloy.
  • nickel alloys have the highest atomic percentage of nickel compared to the doped metal.
  • the material of the first protective sub-layer 310 is nickel with an atomic percentage (can be recorded as Ni at%) greater than or equal to 40% (such as 40%, 50%, 60%, 70%, 75%, 80%, 90% or 99%) nickel alloy.
  • the nickel alloy may be a Ni binary, ternary, or quaternary alloy with a nickel atomic percentage greater than or equal to 40%.
  • the materials of the first protection sub-layer 310 also include tungsten (Wu), vanadium (V), palladium (Pd), aluminum (Al), titanium (Ti), zirconium (Zr), molybdenum (Mo), copper At least one of (Cu), yttrium (Y), niobium (Nb), platinum (Pt), tin (Sn), tantalum (Ta), gold (Au) and silver (Ag). At least one of these doped metals may form a nickel alloy with nickel.
  • the nickel alloy may be NiAl, NiV, NiTi, NiMo, NiCu or NiAg, etc.
  • the nickel alloy may not react with the first welding material T (for example, tin), that is, they cannot form an IMC with the first welding material T.
  • the nickel alloy may be doped with one or more metals that can react with the first welding material T. The following is a detailed analysis of the benefits of the material of the first protection sub-layer 310 including nickel (Ni):
  • Metals that react well with soldering materials include: gold (Au), silver (Ag), copper (Cu), nickel ( Ni), iron (Fe), etc.
  • Au gold
  • silver Ag
  • Cu copper
  • Ni nickel
  • Fe iron
  • Ni and Ni alloy have good bonding effect and good wettability; at the same time, metal doping can improve the oxidation resistance of Ni alloy.
  • Ni reacts with Sn in the soldering material to generate Ni 3 Sn 2 , Ni 3 Sn 4 , Ni 3 Sn 7 and other IMCs.
  • IMC plays the role of soldering the connection between the electronic component D2 and the circuit board D1 .
  • Ni or Ni alloy eg, NiW alloy, NIV alloy, etc.
  • NiW alloy e.g.
  • NIV alloy e.g.
  • Au and Ag are precious metals with high cost, and Ag is easily oxidized.
  • Cu is easily oxidized, and is still easily oxidized after Cu and Cu alloys are doped with metal. Fe is prone to oxidation and corrosion. Therefore, the material of the first protection sub-layer 310 is Ni or Ni alloy.
  • metals such as molybdenum (Mo), tungsten (W), titanium (Ti) and their alloys do not react with Sn, that is, they cannot react with Sn and generate IMC.
  • Mo molybdenum
  • W tungsten
  • Ti titanium
  • this type of metals or alloys for example, WTi alloy, Mo alloy, Ti, etc.
  • Sn forms Sn balls and shrinks in (that is, indicating poor wettability), and Sn does not interact with such metals or alloys. alloy reaction.
  • the oxidation resistance of Ni and Ni alloy is better than that of Cu alloy.
  • Ni alloy is annealed at 250°C or 300°C, the reflectivity does not decrease significantly (as shown in Figure 8a), and the resistance decreases (as shown in Figure 9a).
  • Cu alloy oxidizes when the annealing temperature is higher than 150°C, resulting in a significant decrease in reflectivity (as shown in Figure 8b) and an increase in resistance (as shown in Figure 9b).
  • Ni and Ni alloys have strong corrosion resistance.
  • the corrosion resistance of Ni alloy is greater than that of Au, and the corrosion resistance of Au is greater than that of Cu alloy.
  • Ni alloy has good adhesion.
  • the thickness made of Ni alloy is The single-layer film (recorded as film 1) can achieve 5B adhesion performance.
  • the thickness of Cu or its alloy is The single-layer film (recorded as film 2) will undergo severe peeling. If film 2 is stacked on film 1 to form a laminated structure, and film 1 is used as a buffer layer for film 2, the adhesion of film 2 is enhanced, and the laminated structure can achieve 5B performance.
  • the connection portion may further include other first sub-layers, and the other first sub-layers are stacked on a side of the first conductive sub-layer 320 away from the first protection sub-layer 310 and are in contact with the first conductive sub-layer 320 .
  • the material of other first sub-layers is Ni or Ni alloy, thereby enhancing the adhesion of the first conductive sub-layer 320 .
  • a layer of Ni or Ni alloy can be deposited first to obtain a thin film, and the thin film can be patterned to form the first protective sub-layer 310 .
  • This step can use a conventional photolithography process, which is low-cost, contains no cyanide and does not pollute the environment; and because it is compatible with the processes used in existing products, it can be adapted to current production lines and is easier to achieve mass production.
  • a plurality of thin films may be deposited in sequence, and then the plurality of thin films may be patterned together to form a connection portion including a plurality of first sub-layers. Likewise, it has the above effects and further simplifies the preparation process.
  • the thickness of the first protective sub-layer 310 is wait. Among them, as the thickness of the first protection sub-layer 310 increases, the first protection sub-layer 310 has a better blocking effect on the first welding material T, thereby preventing the first welding material T and the first conductive sublayer 320 from forming an intermetallic compound. .
  • the thickness of the first protective sub-layer 310 is In the case of , the first solder material T (for example, just enough) may diffuse into the first conductive sublayer 320 and form an intermetallic compound with the first conductive sublayer 320 .
  • the thickness of the first protective sub-layer 310 is In this case, the first soldering material T cannot penetrate the first protective sub-layer 310 , that is, the first soldering material T will not diffuse into the first conductive sub-layer 320 . Therefore, the thick bottom of the first protective sub-layer is and are the two limit values of the first protection sub-layer 310, namely is the minimum limit value, is the maximum limit value.
  • the circuit board D1 further includes a gate pattern layer 200 .
  • the gate pattern layer 200 is provided on the base substrate 100 .
  • the gate pattern layer 200 includes a plurality of gate electrodes 210; for example, the gate electrodes 210 of the transistors in the above-mentioned pixel circuit.
  • the "pattern layer” may be a layer structure containing a specific pattern formed by using the same film formation process to form at least one film layer, and then performing a patterning process on the at least one film layer.
  • the patterning process may include multiple glue coating, exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be in Different heights (or thicknesses).
  • the gate pattern layer 200 can be made of metal material, for example, it can be at least one of aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), titanium (Ti), molybdenum (Mo), etc. .
  • the gate pattern layer 200 is disposed on a side of the active pattern layer 400 away from the base substrate 100; based on this, in the pixel circuit, the gate electrode 210 in the gate pattern layer 200 is located above the active pattern 410, At this time, the transistor corresponding to the gate 210 and the active pattern 410 is a top-gate transistor.
  • the transistors in the pixel circuit may all be top-gate transistors. In still other examples, in the pixel circuit, some transistors are top-gate transistors and some transistors are bottom-gate transistors.
  • the circuit board D1 further includes: a first insulation layer M1 and a second insulation layer M2.
  • the first insulation layer M1 separates the active pattern layer 400 and the gate pattern layer 200.
  • the second insulation layer M1 separates the active pattern layer 400 and the gate pattern layer 200.
  • the insulating layer M2 is located on the side of the active pattern layer 400 , the gate pattern layer 200 and the first insulating layer M1 away from the immersed substrate 100 .
  • the first insulation layer M1 is disposed on the base substrate 100 and covers the active pattern layer 400 .
  • the gate pattern layer 200 is disposed on the first insulation layer M1.
  • the second insulating layer M2 is disposed on the first insulating layer M1 and covers the gate pattern layer 200 .
  • the circuit board D1 further includes a plurality of first via holes penetrating the second insulation layer M2 and the first insulation layer M1.
  • a first via hole exposes the first electrode region 420 or the second electrode region 430 of a transistor.
  • the circuit board D1 further includes: a transfer pattern layer 700 disposed between the electrical pattern layer 300 and the active pattern layer 400 .
  • the transfer pattern layer 700 includes a plurality of transfer portions 710, and the transfer portions 710 are coupled to the active patterns 410 and the connection portions.
  • the connection part coupled with the active pattern 410 is called the first connection part 300a.
  • the first connection part 300a can be coupled with the active pattern 410 of a transistor through the adapter part 710.
  • the two adapter portions 710 may be respectively coupled to the first electrode region 420 and the second electrode region 430 of a transistor. Specifically, a part of the adapter portion 710 can penetrate the first via hole and contact the first electrode region 420 or the second electrode region 430 of a transistor. In addition, for example, one of the two adapter parts 710 may be coupled (eg, in contact) with the first connection part 300a, and the other may not be coupled with the connection part. As another example, the two transfer portions 710 may be coupled (eg, in contact) with two connection portions (eg, the two first connection portions 300a) in the electrical pattern layer 300 respectively.
  • the first and second poles of some transistors in the pixel circuit are only directly connected to other transistors in the pixel circuit, without being connected to the electronic component D2, or
  • the signal input terminals for example, the first power supply voltage terminal VDD, the data line DL, the initialization signal terminal Vinit, etc.
  • the two transition portions 710 of a transistor coupling are not coupled to the electrical pattern layer 300 .
  • the transfer pattern layer 700 can be made of metal materials, for example, it can be aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), nickel (Ni) and other metal elements, or it can also contain the above metals. A metal alloy of at least one of the elements.
  • the transfer pattern layer 700 may also be a stacked structure, for example, three conductive layers are stacked.
  • the circuit board D1 further includes a light-shielding pattern layer 500 .
  • the light-shielding pattern layer 500 is provided between the active pattern layer 400 and the base substrate 100 .
  • the material of the light-shielding pattern layer 500 may be a metal material.
  • the light-shielding pattern layer 500 and the gate pattern layer 200 may be made of the same material.
  • the circuit board D1 further includes a third insulation layer M3 disposed between the light-shielding pattern layer 500 and the active pattern layer 400 .
  • the third insulating layer M3 is disposed on the base substrate 100 and covers the light-shielding pattern layer 500 .
  • the first insulation layer M1 and the active pattern layer 400 are provided on the third insulation layer M3.
  • the light-shielding pattern layer 500 may include a plurality of light-shielding blocks 510 .
  • the orthographic projection of the light shielding block 510 on the base substrate 100 covers the orthographic projection of the active pattern 410 on the base substrate 100 . In this way, the light irradiating the active pattern 410 from the base substrate 100 side can be blocked by the light-shielding pattern layer 500, thereby preventing the characteristics of the transistor from changing due to illumination.
  • the orthographic projection of the entire light-shielding pattern layer 500 on the base substrate 100 covers the orthographic projection of the entire active pattern layer 400 on the base substrate 100; this can better protect the transistors.
  • the circuit board D1 may also include: a fourth insulating layer M4 , the fourth insulating layer M4 is disposed on the second insulating layer M2 superior.
  • the fourth insulation layer M4 also covers the transfer pattern layer 700 .
  • the fourth insulation layer M4 includes a first planarization layer PLN1 and a first passivation layer PVX1.
  • the material of the first flat layer PLN1 is an organic insulating material, so it can also be called an organic insulating layer, which can provide a relatively flat upper surface;
  • the material of the first passivation layer PVX1 is an inorganic insulating material, so it can also be called an inorganic layer. Insulation layer can achieve better insulation effect.
  • the first passivation layer PVX1 is disposed on a side of the first flat layer PLN1 away from the base substrate 100 .
  • the electrical pattern layer 300 may be disposed on a side of the first passivation layer PVX1 away from the base substrate 100 . That is, in the X direction, the first planarization layer PLN1, the first passivation layer PVX1 and the electrical pattern layer 300 are stacked in sequence. For another example, the positions of the first planarization layer PLN1 and the first passivation layer PVX1 can be interchanged.
  • the circuit board D1 further includes a plurality of second via holes penetrating the fourth insulation layer M4. At least one second via hole exposes the adapter portion 710 .
  • a part of the connecting portion passes through the second via hole and contacts the adapter portion 710 .
  • a part of the first connecting part 300a passes through the second via hole and contacts an adapter part 710.
  • a part of the first connecting part 300a passes through the second via hole and contacts an adapter part 710, and a part of the third connecting part 300c passes through the second through hole and contacts another adapter part 710.
  • part of the connection part may be the conductive sub-layer closest to the base substrate 100 (for example, the first conductive sub-layer 320, or the second conductive sub-layer 340) and other first sub-layers close to the side of the base substrate 100. layer.
  • a part of the connection part may be the first conductive sub-layer 320 (ie, the above-mentioned conductive sub-layer).
  • connection part A part may be the second conductive sub-layer 340 (ie, the above-mentioned conductive sub-layer) and the first buffer layer (ie, the above-mentioned other first sub-layer).
  • FIG. 10 is an enlarged view of the electrical pattern layer 300 (eg, the second connection portion 300b) in FIG. 6 .
  • the ratio of the areas of the orthographic projections of any two adjacent first sub-layers on the base substrate 100 among the plurality of first sub-layers is 0.9 ⁇ 1.1.
  • multiple connections can be formed from the electrical pattern layer through one etching process, thereby reducing process steps.
  • the area of the orthogonal projection of the lower surface of the upper first sub-layer on the base substrate 100 is smaller than the area of the lower surface of the lower first sub-layer. The area of the orthographic projection on the base substrate 100 .
  • the ratio of the area of the orthographic projection of the lower surface of the first protective sub-layer 310 and the lower surface of the first conductive sub-layer 320 on the base substrate 100 is, for example, 0.9, 0.91, 0.92, 0.93, 0.95, 0.97 ,0.99,1.
  • the ratio of the orthogonal projection areas of the lower surface of the first conductive sub-layer 320 and the lower surface of the first protective sub-layer 310 on the base substrate 100 is, for example, 1.01, 1.03, 1.05, 1.07, 1.09, 1.1 wait.
  • the connection part includes a bottom surface 300-1 and a side surface 300-2.
  • the bottom surface 300-1 is the surface of the connection portion that is closest to and parallel to the base substrate 100; the side surface 300-2 is adjacent to the bottom surface 300-1.
  • the angle ⁇ between the side surface 300-2 and the bottom surface 300-1 is 40° to 90°.
  • the bottom surface 300-1 of the connecting part is the lower surface shown in FIG. 10; the side surface 300-2 of the connecting part may be the left side or the right side shown in FIG. 10).
  • the angle ⁇ between the bottom surface 300-1 and the side surface 300-2 is, for example, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, 90°, etc. .
  • the selection of materials for different sub-layers will affect this angle.
  • the first conductive sub-layer 320 is made of copper or copper alloy
  • the first protective sub-layer 310 is made of nickel or nickel alloy. Based on this, the two can be formed through one patterning process (such as etching together), and can A good etching angle is produced, thereby forming a connection portion with the above-mentioned included angle ⁇ .
  • FIG. 11 shows a laminated structure of another circuit board D1 provided by an embodiment of the present disclosure. What is different from the circuit board D1 shown in FIG. 6 is that the electrical pattern layer 300 is formed on the circuit board D1 through multiple patterning processes as shown in FIG. 11 .
  • the electrical pattern layer 300 is formed on the circuit board D1 through multiple patterning processes as shown in FIG. 11 .
  • FIG. 11 please refer to the description of the relevant embodiment in Figure 6 and will not be described again here.
  • an electrical pattern layer 300 is provided on the fourth insulating layer M4 .
  • the plurality of connection portions further include a fourth connection portion 800 .
  • the fourth connection portion 800 is coupled to the first power supply voltage terminal VDD.
  • the first conductive sub-layer 320 and the first protection sub-layer 310 are stacked on the fourth insulating layer M4; the fourth connection portion 800 in the first protection sub-layer 310 is etched on the first protection sub-layer 310 For the orthographic projection part, etching is continued to form the first connection part 300a, the second connection part 300b and the fourth connection part 800. Therefore, the first connection part 300a, the second connection part 300b and the fourth connection part 800 of this example can be formed through multiple processes.
  • connection part 800 shown in FIG. 11 has a different structure from the third connection part 300c in FIG. 6 , but has the same function (that is, both are coupled to the first power supply voltage terminal VDD).
  • FIG. 12 shows another laminated structure of a circuit board D1 provided by an embodiment of the present disclosure. What is different from the circuit board D1 shown in Figure 6 is that the circuit board D1 in Figure 12 has improved the first protection sub-layer 310 of the electrical pattern layer 300; for other structures, please refer to the description of the embodiment related to Figure 6, in This will not be described again.
  • the first protection sub-layer 310 shown in FIG. 12 covers the outer surface of the first conductive sub-layer 320 (ie, the first conductive sub-layer in FIG. 12 the top, left side, and right side of layer 320).
  • the first protective sub-layer 310 shown in FIG. 12 can be formed through multiple patterning processes, which can wrap the exposed first conductive sub-layer 320 and thereby prevent the first conductive sub-layer 320 from being oxidized.
  • connection parts since the connection parts are all exposed, the entire first connection part or the second connection part can be used as the pad p.
  • FIG. 13 shows another laminated structure of a circuit board D1 provided by an embodiment of the present disclosure.
  • the circuit board D1 shown in FIG. 13 has a fifth insulating layer M5 added on the side of the fourth insulating layer M4 away from the base substrate 100 .
  • a fifth insulating layer M5 added on the side of the fourth insulating layer M4 away from the base substrate 100 .
  • the circuit board D1 further includes a fifth insulating layer M5 , which is disposed on a side of the fourth insulating layer M4 away from the base substrate 100 .
  • the fifth insulating layer M5 includes a stacked second flat layer PLN2 and a second passivation layer PVX2.
  • the second planarization layer PLN2 is in contact with the first passivation layer PVX1.
  • the material of the second flat layer PLN2 may be an organic insulating material, so the second flat layer PLN2 may also be called an organic insulating layer.
  • the material of the second passivation layer PVX2 may be an inorganic insulating material, so the second passivation layer PVX2 may also be called an inorganic insulating layer.
  • the second flat layer PLN2 covers the electrical pattern layer 300 .
  • a third via hole is opened on the second planarization layer PLN2 and the second passivation layer PVX2 to expose the electrical pattern layer 300 .
  • the first connection part 300a and the second connection part 300b are exposed. This allows the pin of the electronic component D2 to be soldered to the first connection part 300a and the second connection part 300b at the third via hole.
  • the first protection sub-layer 310 exposed by the third via hole is parallel to the upper surface of the base substrate 100 . That is, the first protective sub-layer 310 shown in FIG. 13 may be a horizontal plane.
  • the exposed portion of the connection part (such as the first connection part 300 a and the second connection part 300 b ) at the third through hole may be the pad P, and the pin of the electronic component D2 may pass through the first
  • the solder T is soldered to the pad P to realize the coupling between the electronic component D2 and the circuit board D1.
  • there is a circuit board D1 with a third through hole then the pad P of the circuit board D1 is the exposed part of the connection part at the third through hole (please refer to the related description of the pad P shown in Figure 13) ,No longer.
  • FIG. 14 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure. Compared with the circuit board D1 shown in FIG. 13 , the circuit board D1 shown in FIG. 14 improves the electrical pattern layer 300 .
  • the circuit board D1 shown in FIG. 14 improves the electrical pattern layer 300 .
  • a first conductive sub-layer 320 is formed on the third insulating layer M4, a fifth insulating layer M5 is formed on the first conductive sub-layer 320, and a third via hole is opened on the fifth insulating layer M5 to expose The first conductive sub-layer 320; the first protection sub-layer 310 is provided in the third via hole.
  • the shape of the first protection sub-layer 310 may be similar or identical to the shape of the third via; for example, both may be tapered. Therefore, the process of the electrical pattern layer 300 and the fifth insulating layer M5 in the circuit board D1 shown in FIG. 14 is different from that of the electrical pattern layer 300 and the fifth insulating layer M5 in the circuit board D1 shown in FIG. 13 .
  • the plurality of connection parts in the circuit board D1 shown in FIG. 14 include a first connection part 300a, a second connection part 300b and a fourth connection part 800.
  • the fourth connection portion 800 is formed of the first conductive sublayer 320 and coupled to the first power supply voltage terminal VDD.
  • FIG. 15 shows another laminated structure of a circuit board D1 provided by an embodiment of the present disclosure.
  • the electrical pattern layer 300 in the circuit board D1 shown in FIG. 15 adds a second protective sub-layer 330 and a second conductive sub-layer 340 .
  • FIG. 16 is an enlarged view of the connecting portion (eg, the second connecting portion 300b) in FIG. 15 .
  • Figure 17 is an alternative structural diagram of Figure 15.
  • FIG. 18 is an enlarged view of the connecting portion (eg, the second connecting portion 300b) in FIG. 17 .
  • the plurality of first sub-layers further include: at least one (for example, one, or for example multiple) second conductive sub-layers 340 disposed on the side of the first conductive sub-layer 320 close to the base substrate 100 .
  • the connection part may include three first sub-layers, that is, the number of the first sub-layers is three.
  • the connection part may be in a direction from close to the base substrate 100 to away from the base substrate 100 (for example, from top to bottom).
  • the first protection sub-layer 310, the first conductive sub-layer 320 and the second protection sub-layer 330 are stacked in sequence.
  • the first protection sub-layer 310 has a smaller nickel atomic percentage and/or a thinner thickness
  • the connection portion composed of the first protective sub-layer 310 and the first conductive sub-layer 320 will still be damaged. After the electronic component D2 is removed, the electronic component D2 cannot achieve a stable and good connection with the connection portion again.
  • the pins can also form a stable and good connection with the second protection sub-layer 330 again, thereby realizing the coupling between the electronic component D2 and the connection part, thereby improving the maintenance rate of the circuit board D1.
  • the second protective sub-layer 330 is configured to hinder the diffusion of the first solder material T.
  • the plurality of first sub-layers also include: at least one (for example, one, and for example multiple) second protection sub-layers 330 disposed on the side of the first conductive sub-layer 320 close to the base substrate 100.
  • the second conductive sub-layer 340 and second protection sub-layers 330 are arranged alternately, and a second protection sub-layer 330 is in contact with the first conductive sub-layer 320 .
  • FIGS. 1 for example, one, and for example multiple
  • connection part includes four first sub-layers, that is, the number of the first sub-layers is four; for example, it can be in a direction from close to the base substrate 100 to away from the base substrate 100 (for example, From top to bottom), the first protection sub-layer 310, the first conductive sub-layer 320, the second protection sub-layer 330 and the second conductive sub-layer 340 are stacked in sequence.
  • the connection part includes five first sub-layers, that is, the number of the first sub-layers is five; for example, it can be from a direction close to the base substrate 100 to a direction away from the base substrate 100
  • the first protection sub-layer 310, the first conductive sub-layer 320, the second protection sub-layer 330, the second conductive sub-layer 340 and the second protection sub-layer 330 are stacked in sequence (for example from top to bottom).
  • the connection part also includes multiple (such as six, seven, eight, etc.) first sub-layers, so the number of first sub-layers is not limited here.
  • first soldering material T may pass through the first protective sub-layer 310, the first conductive sub-layer 320 and the second protective sub-layer 330, when the electronic component D2 is soldered or removed, the first protective sub-layer will still be damaged. layer 310, the first conductive sub-layer 320 and the second protective sub-layer 330.
  • the electronic component D2 After removing the electronic component D2, the electronic component D2 cannot achieve a stable and good connection with the connection portion again; however, by providing at least one second conductive Electronic layer 340, in this way, even if the first protective sub-layer 310, the first conductive sub-layer 320 and the second protective sub-layer 330 are destroyed, but there is still the second conductive sub-layer 340, then the pins of the electronic component D2 It can also form a stable and good connection with the second conductive sublayer 340 again, thereby realizing the coupling between the electronic component D2 and the connecting part, thereby improving the maintenance rate of the circuit board D1.
  • the material of the second protection sub-layer 330 and the material of the first protection sub-layer 310 include the same composition.
  • the material of the second protection sub-layer 330 and the material of the first protection sub-layer 310 are both pure nickel or nickel alloy; therefore, the material composition of the second protection sub-layer 330 can refer to the correlation of the material composition of the first protection sub-layer 310 The description will not be repeated; this can achieve the same effect as the first protective sub-layer 310, that is, hindering the diffusion of the first welding material T.
  • the material of the second protection sub-layer 330 includes nickel, wherein the atomic percentage of nickel in the material of the second protection sub-layer 330 is less than or equal to the atomic percentage of nickel in the material of the first protection sub-layer 310 . In some examples, where the material of the second protection sub-layer 330 includes nickel, the atomic percentage of nickel in the material of the second protection sub-layer 330 may be exactly the same as the atomic percentage of nickel in the material of the first protection sub-layer 310 same.
  • FIG. 19 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure. Compared with the circuit board D1 shown in FIG. 17 , the circuit board D1 shown in FIG. 19 includes two first connection parts 300a. For other structures, please refer to the description of the embodiment related to Figure 17 and will not be described again here.
  • the circuit board D1 shown in FIG. 19 includes a second connection part 300b and two first connection parts 300a, where the two first connection parts 300a are respectively coupled to the two adapter parts 710. Two pins of the electronic component are respectively coupled to a first connection part 300a and a second connection part 300b.
  • the other first connection part 300a may also be coupled to the first power supply voltage terminal VDD.
  • the number and structure of the first sub-layer shown in FIG. 19 can be referred to the related description of the number and structure of the first sub-layer shown in FIG. 18 , which will not be described again.
  • FIG. 20 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure. Compared with the circuit board D1 shown in FIG. 13 , a first buffer sub-layer 350 is added to the electrical pattern layer 300 in the circuit board D1 shown in FIG. 19 .
  • FIG. 21 is an enlarged view of the electrical pattern layer 300 (eg, the second connection portion 300b) of FIG. 20 .
  • the plurality of first sub-layers also include a first buffer sub-layer 350.
  • the first buffer sub-layer 350 is the one closest to the base substrate 100 among the plurality of first sub-layers; the first buffer sub-layer
  • the material of 350 contains different components from the material of the first protective sub-layer 310 and the material of the first conductive sub-layer 320 .
  • the material of the first buffer sub-layer 350 and the material of the first protection sub-layer 310 both include pure nickel or nickel alloy; the material of the first buffer sub-layer 350 includes molybdenum-niobium alloy, molybdenum-nickel-titanium alloy, molybdenum, At least one of molybdenum alloy, titanium and titanium-copper alloy.
  • the first buffer sub-layer 350 also blocks the diffusion of the first solder material T.
  • FIG. 23 is an enlarged view of the electrical pattern layer 300 (eg, the second connection portion 300b) of FIG. 22 .
  • the plurality of first sub-layers include a first protective sub-layer 310 , a first conductive sub-layer 320 , a second protective sub-layer 330 , which are sequentially stacked (eg, from top to bottom).
  • the second conductive sub-layer 340 and the first buffer sub-layer 350 are sequentially stacked (eg, from top to bottom).
  • the plurality of first sub-layers include a first protective sub-layer 310, a first conductive sub-layer 320, a second protective sub-layer 330 and a first buffer sub-layer 350 stacked in sequence (eg from top to bottom). .
  • Figure 24 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure.
  • the circuit board D1 shown in FIG. 24 includes a second connection part 300b and two first connection parts 300a, where the two first connection parts 300a are respectively coupled to the two adapter parts 710. Two pins of the electronic component are respectively coupled to a first connection part 300a and a second connection part 300b.
  • the other first connection part 300a may also be coupled to the first power supply voltage terminal VDD.
  • the number and structure of the first sub-layer shown in Figure 24 can be referred to the related description of the number and structure of the first sub-layer shown in Figure 22. For other structures, please refer to the description of the relevant embodiment in Figure 22, which will not be discussed here. Repeat.
  • FIG. 25 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure.
  • the transfer portion 710 includes at least one of a first protection sub-layer 711 and a second protection sub-layer 713, and a transfer sub-layer 712; wherein the first protection sub-layer 711 is stacked on the transfer sub-layer 712 is close to the side of the base substrate 100, and the material of the first protection sub-layer 711 includes nickel; the second protection sub-layer 713 is stacked on the side of the adapter sub-layer 712 away from the base substrate 100, and the second protection sub-layer 713 is stacked on the side of the adapter sub-layer 712 away from the base substrate 100.
  • the material of layer 713 includes nickel.
  • the material of the first protection sub-layer 711 and the material of the second protection sub-layer 713 may be the same as the material of the first protection sub-layer 310 , that is, the material of the first protection sub-layer 711 includes nickel and the material of the second protection sub-layer 713 Including nickel, please refer to the related description that the material of the first protection sub-layer 310 includes nickel.
  • the material of the transfer sub-layer 712 is the same as the material of the transfer portion 710 disclosed in the above embodiment.
  • the transfer part 710 includes a first protection sub-layer 711 and a transfer sub-layer 712.
  • the first protection sub-layer 711 is stacked on a side of the transfer sub-layer 712 close to the base substrate 100, and the material of the first protection sub-layer 711 includes nickel.
  • the first protection sub-layer 711 can prevent the transfer sub-layer 712 from being oxidized; when the transfer part 710 and the connection part are welded, the first protection sub-layer 711 and the welding material form an intermetallic compound, and the first protection sub-layer 711 It can also hinder the diffusion of the solder material; if the connection portion on the side of the adapter portion 710 away from the base substrate 100 is removed, the first protection sub-layer 711 may be damaged, but since the adapter portion 710 also includes an adapter The layer 712, and thus the electronic component, can also be fixedly connected to the adapter sub-layer 712 of the adapter portion 710 again.
  • the transfer part 710 includes a second protection sub-layer 713 and a transfer sub-layer 712 .
  • the second protection sub-layer 713 is stacked on a side of the transfer sub-layer away from the base substrate 100, and the material of the second protection sub-layer 713 includes nickel.
  • connection portion on the side of the adapter portion 710 away from the base substrate 100 is removed, the adapter sub-layer 712 will be damaged.
  • second protection sub-layer 713 on the adapter portion 710 there is still a second protection sub-layer 713 on the adapter portion 710, and the electronic components can still be connected to the adapter portion.
  • the second protection sub-layer 713 of 710 realizes the fixed connection again; wherein, the second protection sub-layer 713 can hinder the diffusion of the soldering material.
  • the transfer part 710 includes a first protection sub-layer 711, a second protection sub-layer 713 and a transfer sub-layer 712.
  • the first protection sub-layer 711 is stacked on a side of the transfer sub-layer 712 close to the base substrate 100, and the material of the first protection sub-layer 711 includes nickel.
  • the second protection sub-layer 713 is stacked on the side of the transfer sub-layer 712 away from the base substrate 100, and the material of the second protection sub-layer 713 includes nickel.
  • the first protection sub-layer 711 can prevent the transfer sub-layer 712 from being oxidized; when the transfer part 710 and the connection part are welded, the first protection sub-layer 711 and the welding material form an intermetallic compound, and the first protection sub-layer 711 It can also hinder the diffusion of solder material; in some examples, after the connection part is removed from the adapter part 710, the first protection sub-layer 711 may be damaged, but the adapter part 710 still has the adapter sub-layer 712 and the second protection sub-layer 711.
  • the protection sub-layer 713, and thus the electronic component, can also be fixedly connected to the transfer sub-layer 712 of the transfer portion 710 again.
  • the first protection sub-layer 711 and the adapter sub-layer 712 may be damaged, but the adapter portion 710 still exists.
  • the second protection sub-layer 713, and thus the electronic component can be fixedly connected to the second protection sub-layer 713 of the adapter portion 710 again; wherein, the second protection sub-layer 713 can hinder the diffusion of the soldering material.
  • the gate 210 in the circuit board D1 includes at least one of the third protection sub-layer 211 and the fourth protection sub-layer 213 , and the gate conductive sub-layer 212 .
  • the third protection sub-layer 211 is stacked on the side of the gate conductive sub-layer 212 close to the base substrate 100, and the material of the third protection sub-layer 211 includes nickel.
  • the fourth protection sub-layer 213 is stacked on a side of the gate conductive sub-layer 212 away from the base substrate 100, and the material of the fourth protection sub-layer 213 includes nickel.
  • the material of the third protection sub-layer 211 and the material of the fourth protection sub-layer 213 are both the same as the material of the first protection sub-layer 310 , that is, the material of the third protection sub-layer 211 includes nickel and the material of the fourth protection sub-layer 213 includes For nickel, please refer to the relevant description of the material of the first protection sub-layer 310 including nickel, which will not be described again.
  • the material of the gate conductive sublayer 212 may refer to the relevant description of the material of the gate electrode 210 in the above disclosed embodiments.
  • the gate 210 includes a third protection sub-layer 211 and a gate conductive sub-layer 212.
  • the third protection sub-layer 211 is stacked on the side of the gate conductive sub-layer 212 close to the base substrate 100, and the material of the third protection sub-layer 211 includes nickel.
  • the gate 210 includes a fourth protection sub-layer 213 and a gate conductive sub-layer 212.
  • the fourth protection sub-layer 213 is stacked on a side of the gate conductive sub-layer 212 away from the base substrate 100, and the material of the fourth protection sub-layer 213 includes nickel.
  • the gate 210 includes a third protection sub-layer 211 , a fourth protection sub-layer 213 and a gate conductive sub-layer 212 .
  • the third protection sub-layer 211 is stacked on the side of the gate conductive sub-layer 212 close to the base substrate 100, and the material of the third protection sub-layer 211 includes nickel.
  • the fourth protection sub-layer 213 is stacked on a side of the gate conductive sub-layer 212 away from the base substrate 100, and the material of the fourth protection sub-layer 213 includes nickel.
  • FIG. 26 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure.
  • the material of the active pattern layer 400 may be an oxide semiconductor.
  • the oxide semiconductor may be IGZO, IGTO, IZO, CAAC, etc.
  • the transistor is an oxide transistor.
  • two adapter portions 710 are respectively coupled to the first pole region 420 and the second pole region 430 , and the adapter portion 710 directly contacts or directly overlaps the first pole region 420 and the second pole region 430 . In this way, the thickness of the circuit board in the X direction can be reduced.
  • the gate pattern layer 200 may be disposed on the base substrate 100 .
  • the first insulating layer M1 is disposed on the base substrate 100 and covers the gate pattern layer 200; the active pattern layer 400 is disposed on a side of the first insulating layer M1 away from the base substrate 100.
  • the fourth insulating layer M4 is provided on the first insulating layer M1.
  • the first passivation layer PVX1 is provided on the first insulation layer M1.
  • the first planar layer PLN1 covers the active pattern layer 400 and the transfer pattern layer 700, that is, the active pattern layer 400 and the transfer pattern layer 700 are arranged in the same layer.
  • the electrical pattern layer 300 is disposed on the first passivation layer PVX1; the second passivation layer PVX2 is disposed on the first passivation layer PVX1 and covers the electrical pattern layer 300.
  • a second via hole is opened on the first passivation layer PVX1 to expose the adapter portion 710.
  • the oxide transistor thus has a bottom gate structure.
  • the orthographic projection of the gate electrode 210 on the base substrate 100 covers the orthographic projection of the channel region of the active pattern 410 on the base substrate 100 .
  • the electrical pattern layer 300 also includes a light shielding portion.
  • the orthographic projection of the light shielding portion on the base substrate 100 covers the orthographic projection of the channel region of the active pattern 410 on the base substrate 100 .
  • the light shielding portion can cover the side of the active pattern 410 away from the base substrate 100, thereby preventing light from irradiating the side of the active pattern 410 away from the base substrate (i.e. Prevent light from shining on the top surface of the active pattern 410).
  • a gate 210 (i.e., a bottom gate structure) is provided on the side of the active pattern 410 close to the base substrate 100.
  • the gate 210 can prevent light from irradiating on the side of the active pattern 410 close to the base substrate (i.e., prevent light from irradiating the side). irradiated on the bottom surface of the active pattern 410).
  • the light-shielding part includes a plurality of second sub-layers arranged in a stack; along the direction perpendicular to the base substrate 100 , the second sub-layers with the same stacking sequence are made of the same material as the first sub-layer.
  • connection portions include a first connection portion 300a, a second connection portion b, and a third connection portion 300c.
  • the third connection part 300c may be the above-mentioned light-shielding part, that is, the plurality of first sub-layers included in the third connection part 300c and the plurality of second sub-layers included in the light-shielding part are arranged in the same stacking order, and are arranged along a direction perpendicular to the substrate. In the direction of the substrate 100, the materials of the second sub-layer and the first sub-layer with the same stacking order are also the same.
  • FIG. 27 shows another laminated structure of circuit board D1 provided by an embodiment of the present disclosure. Through multiple processes, a circuit board D1 of oxide transistors and polysilicon transistors can be formed.
  • the circuit board D1 shown in Figure 27 includes polysilicon transistors and oxide transistors.
  • the oxide transistor includes a gate electrode, an active pattern, a first electrode region and a second electrode region, a transfer portion, an insulating layer (for example, a ninth insulating layer and a tenth insulating layer), and the like.
  • the ninth insulating layer M9 and the tenth insulating layer M10 are disposed between the fourth insulating layer M4 and the second insulating layer M2, and the active pattern 410a of the oxide transistor is disposed on the second insulating layer M2.
  • the nine insulating layer M9 covers the second insulating layer M2, the gate 210a is disposed on the ninth insulating layer M9, the tenth insulating layer M10 covers the ninth insulating layer M9, and the transfer portion 710a penetrates the ninth insulating layer M9 and
  • the tenth insulating layer M10 is coupled to the first electrode region and the second electrode region of the oxide transistor.
  • the fourth insulating layer M4 covers the tenth insulating layer M10.
  • circuit board D1 shown in FIG. 27 can form both polysilicon transistors and oxide transistors, thereby reducing process steps.
  • Figure 28a shows a functional backplane provided by an embodiment of the present disclosure.
  • Figure 28b is an enlarged view of Figure 28a at J.
  • the functional backplane 10 may include the above-mentioned circuit board D1 and electronic components D2.
  • the connection portion of the electrical pattern layer 300 located in the device area SA is coupled to the electronic component D2 through the first soldering material T.
  • the first connection portion 300a and the second connection portion 300b located in the device area SA in the electrical pattern layer 300 are respectively soldered to the first pin D21 and the second pin D22 of the electronic component D2.
  • the pins of the electronic component D2 may be coupled to the connection part through die-bonding.
  • the portion of the first protection sub-layer 310 located at the connection portion of the device area SA and close to the first soldering material T forms a first intermetallic compound K1 with the first soldering material T.
  • the portion of the first protection sub-layer 310 of the first connection portion 300a close to the first soldering material T and the first soldering material T form a first intermetallic compound K1.
  • the circuit board D3 and the connection portion located in the binding area SS are coupled through the second soldering material.
  • the portion of the first protection sub-layer 310 located at the connection portion of the bonding area SS and close to the second soldering material forms a second intermetallic compound with the second soldering material.
  • the electrical pattern layer 300 also includes: a connection portion (denoted as a fifth connection portion) located in the binding area SS.
  • the fifth connection part is coupled to the circuit board D3 through the second soldering material.
  • the part of the first protection sub-layer 310 of the fifth connection part close to the second welding material and the second welding material form a second intermetallic compound.
  • Figures 28a and 28b show functional backplanes.
  • Figure 29 shows a functional backplane provided by an embodiment of the present disclosure.
  • the electronic component D2 can be welded on the connection part through the second planar layer PLN2 and the second passivation layer PVX2.
  • the electronic component D2 can be soldered on the connection part through the third via hole.
  • Figure 30 shows a functional backplane provided by an embodiment of the present disclosure. Refer to the circuit board shown in Figure 14 and the functional backplane shown in Figures 28a and 28b, which will not be described again.
  • circuit board preparation method S1000 includes steps S100 to S600, as detailed below.
  • Step S100 Referring to FIG. 32, a light-shielding pattern layer LS is formed on the base substrate 100, and a third insulating layer M3 is formed on the base substrate 100; the light-shielding pattern layer LS includes a plurality of light-shielding blocks. Wherein, the third insulating layer M3 covers the base substrate 100 and the light-shielding pattern layer LS.
  • a sputtering process is used to deposit the light-shielding pattern layer LS.
  • the material of the light-shielding pattern layer LS is metal.
  • the metal can be metal elements such as Mo, Ti, Cu, etc., or can also be metal alloys such as MTD, MoNb, etc. Thickness of light-shielding pattern layer LS
  • Step S200 Referring to FIG. 33, a semiconductor pattern layer 600 (for example, polysilicon) is formed on the third insulating layer M3, and then the first insulating layer M1 is formed. Wherein, the first insulation layer M1 covers the active pattern layer 400 and the first insulation layer M1.
  • a semiconductor pattern layer 600 for example, polysilicon
  • a semiconductor pattern layer (eg, a-Si) is vapor deposited, which (For example, using ELA technology) a-Si is modified into p-Si, and the semiconductor pattern layer 600 is formed.
  • Step S300 Referring to FIG. 34, a gate pattern layer 200 is formed on the first insulating layer M1, and then a second insulating layer M2 is formed; the gate pattern layer 200 includes a plurality of gate electrodes 210.
  • the semiconductor pattern layer 600 is doped to form an active pattern layer 400.
  • the active pattern layer 400 includes an active pattern 410, a first electrode region 420 and a second electrode region 430.
  • the second insulating layer M2 covers the gate pattern layer 200 and the first insulating layer M1.
  • the gate pattern layer 200 is deposited by vapor deposition, and the material of the gate pattern layer 200 may be at least one of SiN and SiO. Gate pattern layer 200 thickness
  • Step S400 Referring to FIG. 35, a transfer pattern layer 700 is formed on the second insulation layer M2.
  • the transfer pattern layer 700 includes a plurality of transfer parts 710, and the two transfer parts 710 are respectively coupled to the first pole region 420 and the second pole region 430.
  • a plurality of first via holes are opened in the first insulating layer and the second insulating layer.
  • a conductive part is also deposited in the first via hole, that is, the transfer part 710 is connected to the first via hole through the conductive part.
  • the first pole region 420 or the second pole region 430 is coupled.
  • Step S500 Referring to FIG. 36, an electrical pattern layer 300 is formed on the side of the active pattern layer 400 away from the base substrate 100.
  • the electrical pattern layer 300 includes a plurality of connection portions, and the connection portions are coupled to the active patterns 410 .
  • a fourth insulation layer M4 is formed on the second insulation layer M2, and the fourth insulation layer M4 includes a first planarization layer PLN1 and a first passivation layer PVX1; the first planarization layer PLN1 covers the transfer pattern layer 700, A first passivation layer PVX1 is formed on the first planarization layer PLN1. A plurality of second via holes are opened on the first passivation layer PVX1 and the first planar layer PLN1 to expose the first pole region 420 and the second pole region 430 of the active pattern 410 .
  • electrical pattern layer 300 is formed on first passivation layer PVX1.
  • the connection part is coupled to the active pattern 410 through the second via hole.
  • the connection part includes a plurality of first sub-layers arranged in a stack.
  • the two first sub-layers farthest from the base substrate 100 among the plurality of first sub-layers are respectively the first conductive sub-layer 320 and the first protection sub-layer 310.
  • the first protection sub-layer 310 is provided on the first conductive sub-layer 320.
  • the material of the first protection sub-layer 310 includes nickel.
  • connection portion in step S500 reference can be made to the related description of the number of layers of the connection portion and the material of each layer in the disclosed example of the circuit board D1, which will not be described again.
  • the preparation method of the first sub-layer is: forming the first conductive sub-layer 320.
  • a first protective sub-layer 310 is formed on the first conductive sub-layer 320 .
  • At least one second protective sub-layer 330 is provided.
  • a first conductive sublayer 320 is formed on the second protective sublayer 330 .
  • a first protective sub-layer 310 is formed on the first conductive sub-layer 320 .
  • the material of the second protection sub-layer 330 may be MoNb, MTD, Mo, Mo alloy, Ti, TiCu, etc.
  • the thickness of the second protective sub-layer 330 is The material of the first conductive sub-layer 320 is metal with good conductive properties such as Cu.
  • the thickness of the first conductive sublayer 320 can be selected from 0.3 ⁇ m to 2 ⁇ m.
  • At least one second conductive sub-layer 340 and at least one second protective sub-layer 330 are formed alternately.
  • a first conductive sublayer 320 is formed on the second protective sublayer 330 .
  • a first protective sub-layer 310 is formed on the first conductive sub-layer 320 .
  • first buffer sub-layer 350 is formed.
  • a first conductive sublayer 320 is formed on the first buffer sublayer 350 .
  • a first protective sub-layer 310 is formed on the first conductive sub-layer 320 .
  • a first buffer sub-layer 350 is formed. At least one second conductive sub-layer 340 and at least one second protective sub-layer 330 are formed alternately on the first buffer sub-layer 350 .
  • a first conductive sublayer 320 is formed on the second protective sublayer 330 .
  • a first protective sub-layer 310 is formed on the first conductive sub-layer 320 .
  • the materials of the first protection sub-layer 310, the first conductive sub-layer 320, the second protection sub-layer 330, the second conductive sub-layer 340 and the first buffer sub-layer 350 may refer to the relevant descriptions above.
  • Step S600 Referring to Figure 36, exemplarily, a second flat layer PLN2 is deposited on the first passivation layer PVX1. A second passivation layer PVX2 is formed on the second flat layer PLN2. Wherein, a plurality of third via holes are opened on the second passivation layer PVX2 and the second planarization layer PLN2.
  • the second passivation layer PVX2 is deposited on the first passivation layer PVX1.
  • a second flat layer PLN2 is formed on the second passivation layer PVX2.
  • the second passivation layer PVX2 is deposited by vapor deposition, and the material of the second passivation layer PVX2 may be at least one of SiN and SiO; the thickness of the second passivation layer PVX2
  • the second flat layer PLN2 is then formed through a photolithography process, and the thickness of the second flat layer PLN2 is 2 ⁇ m to 5 ⁇ m.

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Abstract

一种线路板，包括：衬底基板、有源图案层和电学图案层。有源图案层设置在衬底基板的一侧，包括多个有源图案。电学图案层，设置在有源图案层远离衬底基板的一侧，包括多个连接部，至少一个连接部与有源图案耦接。其中，连接部包括沿衬底基板的厚度方向层叠设置的多个第一子层，多个第一子层中最远离衬底基板的两个第一子层分别为第一导电子层和第一防护子层，第一防护子层设置在第一导电子层远离衬底基板的一侧，第一防护子层的材料包括镍。

Description

线路板及制备方法、功能背板、背光模组、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种线路板及制备方法、功能背板、背光模组、显示面板、显示装置。
背景技术
次毫米发光二极管(Mini-Light Emitting Diode，Mini-LED)是指尺寸在80μm～200μm之间的发光二极管。在Mini-LED作为显示面板的像素点构成自发光显示器时，相比于小间距LED显示器，可以实现更高的像素密度。在Mini-LED作为光源应用在背光模组中时，可以通过更加密集的光源排布来制作超薄的光源模组；再配合区域调光技术，使得包括Mini-LED背光模组的显示装置(例如手机等)将有更好的对比度和高动态光照渲染显示效果。微型发光二极管(Micro-Light Emitting Diode，Micro-LED)是尺寸小于80μm的发光二极管，可以直接作为显示装置中显示面板的像素点。
发明内容
一方面提供了一种线路板，包括：衬底基板、有源图案层和电学图案层。有源图案层设置在衬底基板的一侧，包括多个有源图案。电学图案层，设置在有源图案层远离衬底基板的一侧，包括多个连接部，至少一个连接部与有源图案耦接。其中，连接部包括沿衬底基板的厚度方向层叠设置的多个第一子层，多个第一子层中最远离衬底基板的两个第一子层分别为第一导电子层和第一防护子层，第一防护子层设置在第一导电子层远离衬底基板的一侧，第一防护子层的材料包括镍。
在第一焊接材料与第一防护子层的至少一部分(例如部分，又如全部)形成第一金属间化合物之后，第一金属间化合物以及第一防护子层中未形成第一金属间化合物的部分对第一焊接材料进行一定的阻挡，使得第一焊接材料扩散的速度变慢，从而有效阻止第一焊接材料扩散到第一导电子层中。这样一来，即便焊接出现不良(如出现虚焊或者电子元件位置偏移)，需要进行维修，将电子元件去除的过程中，不容易将第一导电子层也去除掉，不造成第一导电子层的缺失，从而可以提高可维修率。
可选地，第一防护子层的材料为纯镍，或者，第一防护子层的材料为镍的原子百分比大于或等于40％的镍合金。
可选地，第一防护子层的材料还包括钨、钒、钯、铝、钛、锆、钼、铜、钇、铌、铂、锡、钽、金和银中的至少一者。
可选地，第一防护子层的厚度为
Figure PCTCN2022114350-appb-000001
可选地，多个第一子层还包括：设置在第一导电子层靠近衬底基板的一侧的至少一个第二防护子层。第二防护子层的材料包括镍。
可选地，多个第一子层还包括：设置在第一导电子层靠近衬底基板的一侧的至少一个第二导电子层。第二导电子层和第二防护子层交替设置，且一第二防护子层与第一导电子层接触。
可选地，第二防护子层的材料与第一防护子层的材料包含的成分相同。
可选地，第二防护子层的材料中镍的原子百分比小于或等于第一防护子层的材料中镍的原子百分比。
可选地，多个第一子层还包括第一缓冲子层，第一缓冲子层为多个第一子层中最靠近衬底基板的一个；第一缓冲子层的材料与第一防护子层的材料和第一导电子层的材料包含的成分均不同。
可选地，第一缓冲子层的材料包括钼铌合金、钼镍钛合金、钼、钼合金、钛和钛铜合金中的至少一种。
可选地，多个第一子层中的任意两个第一子层，在衬底基板上的正投影的面积之比为0.9～1.1。
可选地，连接部包括底面和侧面，底面为连接部中最靠近且平行于衬底基板的面；侧面与底面相邻接；其中，侧面与底面的夹角为40°～90°。
可选地，线路板还包括：设置在电学图案层和有源图案层之间的转接部，转接部与有源图案和连接部耦接。
可选地，转接部包括第一保护子层和第二保护子层中的至少一者，以及转接子层；其中，第一保护子层叠置在转接子层靠近衬底基板的一侧，且第一保护子层的材料包括镍；第二保护子层叠置在转接子层远离衬底基板的一侧，且第二保护子层的材料包括镍。
可选地，线路板还包括：栅图案层。栅图案层设置在衬底基板上，包括多个栅极；栅极包括第三保护子层和第四保护子层中的至少一者，以及栅导电子层；其中，第三保护子层叠置在栅导电子层靠近衬底基板的一侧，且第三保护子层的材料包括镍；第四保护子层叠置在栅导电子层远离衬底基板的一侧，且第四保护子层的材料包括镍。
可选地，栅图案层设置在有源图案层与衬底基板之间，包括多个栅极，栅极在衬底基板上的正投影覆盖有源图案的沟道区在衬底基板上的正投影。电学图案层还包括：遮光部，遮光部在衬底基板上的正投影覆盖有源图案的沟道区在衬底基板上的正投影；遮光部包括层叠设置的多个第二子层；沿垂 直于衬底基板的方向，设置堆叠顺序相同的第二子层和第一子层的材料相同。
另一方面提供了一种功能背板，包括：上述的线路板和电子元件。线路板具有器件区和绑定区。电子元件设置在电学图案层远离衬底基板的一侧。其中，电学图案层中位于器件区的连接部通过第一焊接材料与电子元件耦接，其中，位于器件区的连接部的第一防护子层靠近第一焊接材料的部分与第一焊接材料形成第一金属间化合物。
可选地，电子元件包括发光器件、驱动元件或传感器件。
可选地，功能背板还包括：电路板。电路板与位于绑定区的连接部通过第二焊接材料耦接；其中，位于绑定区的连接部的第一防护子层靠近第二焊接材料的部分与第二焊接材料形成第二金属间化合物。
又一方面提供了一种背光模组，包括：上述的功能背板，电子元件为发光器件。
又一方面提供了一种显示模组，包括：上述的功能背板，电子元件为发光器件。
又一方面提供了一种显示装置，包括：上述的背光模组或显示模组。
又一方面提供了一种线路板的制备方法，包括：
在衬底基板上形成有源图案层，有源图案层包括多个有源图案。
在形成有有源图案层的衬底基板上形成电学图案层，电学图案层包括多个连接部，连接部与有源图案耦接；其中，连接部包括层叠设置的多个第一子层，多个第一子层中最远离衬底基板的两个第一子层分别为第一导电子层和第一防护子层，第一防护子层设置在第一导电子层远离衬底基板的一侧，第一防护子层的材料包括镍。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示装置的结构图。
图2为根据一些实施例的另一种显示装置的结构图。
图3为根据一些实施例的功能背板的结构图。
图4为根据一些实施例的像素电路的电路图。
图5为像素电路对应的时序控制图。
图6为根据一些实施例的一种线路板的叠层结构以及电子元件在线路板上的相对位置的结构图。
图7a为根据一些实施例的锡、焊盘和镍的键合图。
图7b为根据一些实施例的锡、焊盘和钨的键合图。
图8a为根据一些实施例的镍的反射率与波长的表格图。
图8b为根据一些实施例的铜的反射率与波长的表格图。
图9a为根据一些实施例的镍的电阻率与温度的柱状图。
图9b为根据一些实施例的铜的电阻率与温度的柱状图。
图10为图6在第二连接部处的放大图。
图11为根据一些实施例的另一种线路板的叠层结构的结构图。
图12为根据一些实施例的另一种线路板的叠层结构的结构图。
图13为根据一些实施例的另一种线路板的叠层结构的结构图。
图14为根据一些实施例的另一种线路板的叠层结构的结构图。
图15为根据一些实施例的另一种线路板的叠层结构的结构图。
图16为图15在第二连接部处的放大图。
图17为根据一些实施例的另一种线路板的叠层结构的结构图。
图18为图17在第二连接部处的放大图。
图19为根据一些实施例的另一种线路板的叠层结构的结构图。
图20为根据一些实施例的另一种线路板的叠层结构的结构图。
图21为图20在第二连接部处的放大图。
图22为根据一些实施例的另一种线路板的叠层结构的结构图。
图23为图22在第二连接部处的放大图。
图24为根据一些实施例的另一种线路板的叠层结构的结构图。
图25为根据一些实施例的另一种线路板的叠层结构的结构图。
图26为根据一些实施例的另一种线路板的叠层结构的结构图。
图27为根据一些实施例的另一种线路板的叠层结构的结构图。
图28a为根据一些实施例的一种功能背板的叠层结构的结构图。
图28b为图28a在J处的放大图。
图29为根据一些实施例的另一种功能背板的叠层结构的结构图。
图30为根据一些实施例的另一种功能背板的叠层结构的结构图。
图31为根据一些实施例的一种线路板的制备方法流程图。
图32～图37为线路板制备方法的工艺步骤图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条 件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种显示装置，该显示装置可以是显示不论运动(例如，视频)，还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，显示装置例如可以包括手机(Mobile Phone)、平板电脑(Pad)、笔记本电脑、电视、个人数字助理(Personal Digital Assistant，PDA)、超级移动个人计算机(Ultra-Mobile Personal Computer，UMPC)、上网本、可穿戴设备(例如智能手表)、虚拟现实(Virtual Reality，VR)显示设备、增强现实(Augmented Reality，AR)显示设备或车载显示装置等，本实施例对显示装置的类型不作限制。
在一些实施例中，参见图1，显示装置包括显示模组1，还可以包括框体(例如中框等)。显示模组1为被配置为显示画面的组件。框体被配置为固定显示模组1。
显示模组1包括用于显示画面的功能背板10，此时功能背板10可以称为显示基板或显示面板。其中，根据显示原理的不同，显示面板可以是Mini-LED或Micro-LED显示面板等自发光显示面板。
功能背板10包括线路板D1和电子元件D2。电子元件D2可以为发光器件，例如Mini-LED或Micro-LED等。线路板D1具有器件区SA和绑定区SS。其中，线路板D1的器件区SA构成显示区(即用于显示画面的区域)，发光器件可以耦接在线路板D1的显示区。线路板D1被配置为接收数据信号，并基于数据信号控制发光器件的发光亮度，从而实现显示画面。
功能背板10还可以包括电路板D3，例如可以是柔性电路板(Flexible Printed Circuit，FPC)等。电路板D3与线路板D1耦接，例如该电路板D3可以绑定到线路板D1的绑定区SS上。
此外，显示模组1还可以包括驱动电路20，具体可以是驱动IC，例如，源极驱动IC或显示驱动电路(Display Driver Integrated Circuit，DDIC)等。驱动电路20与功能背板(即显示面板)10耦接，被配置为向功能背板10提供数据信号。例如，驱动电路20可以设置在电路板D3上，并通过电路板D3与线路板D1耦接，以向线路板D1发送数据信号。
在另一些实施例中，参见图2，显示装置包括显示面板2，还可以包括背光模组3。其中，显示面板2可以是液晶显示面板。显示面板2具有显示区AA和绑定区(在本实施例中称为第一绑定区)SS1，显示区AA为用于显示画面的区域，第一绑定区SS1为用于与电路板(例如柔性电路板)耦接的区域，其中，第一绑定区SS1可以分布在显示区AA的至少一侧(例如一侧，又如多侧)。
背光模组3被配置为给显示面板2提供光源。背光模组3包括用于提供光源的功能背板10，此时功能背板10可以称为发光基板。
功能背板10包括线路板D1和电子元件D2。其中，电子元件D2可以为发光器件，例如Mini-LED或Micro-LED等。线路板D1具有器件区SA和绑定区SS。线路板D1的器件区SA为用于发光的区域。示例性地，线路板D1的器件区SA的面积可以大于或等于显示面板2的显示区AA。例如，沿显示面板2的厚度方向，显示面板2的显示区AA在线路板D1上的正投影落入线路板D1的器件区SA的范围内，使得显示面板2的显示区AA内的各个像素 均能被器件区中发光器件发出的光线照射到，而使得显示面板2实现显示。
示例性地，安装在线路板D1的多个电子元件(例如发光器件)D2可以分成多个发光组，每个发光组可以包括至少一个电子元件D2。例如，每个发光组可以包括一个电子元件D2。又如，每个发光组包括至少两个相互串联的电子元件D2。线路板D1被配置为接收调光信号，并基于调光信号控制每个发光组中各个电子元件D2的发光亮度。
功能背板10还可以包括电路板D3，例如可以是柔性电路板等。电路板D3与线路板D1耦接，例如该电路板D3可以绑定到线路板D1的绑定区(在本实施例中称为第二绑定区)SS2上。其中，线路板D1上第二绑定区SS2与器件区SA的相对位置，与显示面板2上第一绑定区SS1与显示区AA的相对位置相同。例如，第二绑定区SS2位于器件区SA的右侧，第一绑定区SS1也位于显示区AA的右侧，这样有利于减小显示装置的边框。
此外，背光模组3还可以包括调光电路30，调光电路30与功能背板(即发光基板)10耦接，被配置为向功能背板10提供调光信号。例如，调光电路30可以设置在电路板D3上，并通过电路板D3与线路板D1耦接，以向线路板D1发送调光信号。
在又一些实施例中，上文图1或图2示出的功能背板10中电子元件D2的类型可以改变，从而实现相应的功能。例如，功能背板10中的电子元件D2还可以是驱动元件(例如，驱动器或驱动芯片等)或传感器件。其中，传感器件可以是感光元件(例如光电二极管)、压敏元件或温度感应元件等。例如，电子元件D2可以是感光元件，包含这种电子元件D2的功能背板10可以应用于指纹识别器等电子设备中。下面对上文中的功能背板10进行详细介绍。
参见图3，功能背板10包括线路板D1和设置在线路板D1上且与线路板D1电连接的多个电子元件D2。线路板D1被配置为向每个电子元件D2提供电信号(例如电流，又如电压)，以驱动电子元件D2工作。
在一些实施例中，线路板D1可以包括多个像素电路Q(还可以称为最小重复驱动电路)。一像素电路Q与一电子元件D2电连接，被配置为向该电子元件D2提供电信号。此外，像素电路Q提供的电信号的大小可以调整，以使得电子元件D2的工作状态可调。例如，电子元件D2为发光器件，一像素电路Q与一发光器件电连接，被配置为向该发光器件提供大小可以调整的电信号，使得发光器件的亮度可调。
在一些实施例中，像素电路Q可以包括多个晶体管和至少一个(例如一 个，又如多个)电容器等。例如，像素电路Q均可以包括三个晶体管和一个电容器，构成3T1C结构。还可以包括三个以上的晶体管和至少一个电容器，构成如4T1C结构(即四个晶体管和一个电容器)、5T1C结构(即五个晶体管和一个电容器)或7T1C结构(即七个晶体管和一个电容器)等。
在本公开的实施例中的晶体管均以薄膜晶体管进行举例说明，但又不限于薄膜晶体管，还可以是场效应晶体管等。
其中，晶体管包括：栅极、源极、漏极以及连接在源极和漏极之间的有源图案。有源图案的材料可以包括氧化物半导体，例如该氧化物半导体可以包括氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)，氧化铟锌锡(Indium Gallium Tinc Oxide，IGTO)、氧化铟锌(Indium Zinc Oxide，IZO)和C轴取向结晶(C-Axis Aligned Crystalline，CAAC)结构等中的一种或多种的组合；相应地，该晶体管可以为氧化物晶体管(也可以称为氧化物薄膜晶体管)。有源图案的材料还可以包括多晶硅(P-Si)；相应地，该晶体管可以为多晶硅晶体管。晶体管中，有源图案可以在栅极和源极的电压的驱动下表现为导电特性，使得源极和漏极导通；或者，表现为绝缘特性，使得源极和漏极断开。下文中将包含多个有源图案的层称为有源图案层。
在一些实施例中，像素电路Q中所有晶体管的类型相同，例如均为氧化物晶体管或均为多晶硅晶体管。在另一些实施例中，像素电路Q中晶体管的类型至少有两种，例如像素电路Q可以包括一些氧化物晶体管和一些多晶硅晶体管等。
在一些实施例中，像素电路Q中各晶体管可以均为P型晶体管。需要说明的是，本公开的实施例包括但不限于此。例如，本公开的实施例提供的像素电路Q中的一个或多个晶体管也可以采用N型晶体管，只需将N型晶体管的各极参照本公开的实施例中的相应的P型晶体管的各极相应连接，并且向相应的栅极施加对应的高电平即可。
参见图4，像素电路Q包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和电容器C。本公开的实施例中仅以第一晶体管T1至第七晶体管T7均为P型晶体管为例进行示意。其中，第三晶体管T3可以为驱动晶体管。第三晶体管T3的栅极与N节点耦接。每个晶体管包括栅极、第一极和第二极。其中，对于一晶体管而言，第一极和第二极中的一者为源极，另一者为漏极。例如，第一极为漏极，第二极为源极。
第三晶体管T3的栅极与N节点耦接。
第一晶体管T1的栅极与第一复位信号端G3耦接，第一极与初始化信号端Vinit耦接，第二极与N节点耦接。
第二晶体管T2的栅极与栅线G1耦接，第一极与第三晶体管T3的第二极耦接，第二极与N节点耦接。第四晶体管T4的栅极与栅线G1耦接，第一极与数据线DL耦接，第二极与第三晶体管T3的第一极耦接。
第五晶体管T5的栅极与发光控制信号端EM耦接，第一极与第一电源电压端VDD耦接，第二极与第三晶体管T3的第一极耦接。
第六晶体管T6的栅极与发光控制信号端EM耦接，第一极与第三晶体管T3的第二极耦接，第二极与电子元件D2中的第一电极(例如阳极)耦接。电子元件D2中的第二电极(例如阴极)与第二电源电压端VSS耦接。
第七晶体管T7的栅极与第二复位信号端G2耦接，第一极与初始化信号端Vinit耦接，第二极与电子元件D2中的第一电极耦接。
电容器C的一端与N节点耦接，另一端与第一电源电压端VDD耦接。
其中，第一电源电压端VDD提供的电压可以大于第二电源电压端VSS提供的电压，也可以大于初始化信号端Vinit提供的电压。此外，示例性地，栅线G1、第一复位信号端G3和第二复位信号端G2可以各自提供各自的信号，即三者提供的信号可以不相同。又示例性地，第一复位信号端G3和第二复位信号端G2可以提供相同的信号，此时，二者可以耦接；二者提供的信号与栅线G1提供的信号不同。又示例性地，第二复位信号端G2和栅线G1可以提供相同的信号，此时，二者可以耦接；二者提供的信号与第一复位信号端G3提供的信号不同。
参见图5，上述像素电路Q的工作过程例如包括以下阶段：
复位阶段(S1阶段)：第一晶体管T1响应于第一复位信号端G3提供的信号而开启，从而将初始化信号端Vinit提供的信号(例如可以称为初始化信号)传输至N节点，以对N节点进行复位。
数据写入阶段(S2阶段)：第二晶体管T2和第四晶体管T4均可以响应于栅线G1提供的扫描信号而开启，从而将数据线DL提供的数据信号(例如标记为Vdate)写入到N节点，同时对电容器C开始充电。N结点的电压可以是补偿后的数据信号，例如为Vdate+Vth，其中Vth为第三晶体管的阈值电压。第七晶体管T7响应于第二复位信号端G2提供的信号而开启，从而将初始化信号端Vinit提供的初始化信号传输至电子元件D2的第一电极，以对电子元件D2的第一电极进行复位。
发光阶段(S3阶段)：第五晶体管T5和第六晶体管T6均可以响应于发 光控制信号端EM提供的信号而开启，从而使得从第一电源电压端VDD，依次经第五晶体管T5、第三晶体管T3、第六晶体管T6、电子元件D2，到第二电源电压端VSS的这条通路导通，从而电子元件D2得以工作(例如发光)。
示例性地，上述的像素电路Q中的晶体管可以全部为多晶硅晶体管。又示例性地，上述的像素电路Q中的第一晶体管T1和第二晶体管T2可以为氧化物薄膜晶体管，以减小第一晶体管T1和第二晶体管T2处的漏电流，从而使得N节点的电压得以更好地保持；其他晶体管可以是多晶硅晶体管。
在相关技术中，电子元件D2的引脚与线路板D1的至少部分表面裸露的连接部(也称作焊盘P)在回流焊或浸焊等工艺通过焊接材料实现固定连接。为了完成电子元件D2与线路板D1的固定连接，需要在连接部表面设置焊接材料，(称为第一焊接材料T，例如包含金属锡的材料)，或者将电子元件D2的引脚上设置焊接材料，接着将电子元件D2的引脚与连接部对位并接触设置，例如在230℃～260℃的高温下，使焊接材料熔融并与连接部获得良好的湿润，再迅速冷却降温，从而将电子元件D2与线路板D1固定连接。
在电子元件D2出现虚焊或焊接位置偏移的情况下，需要施加侧向的剪切力以将电子元件D2去除并重新牢固焊接在正确的位置，在去除电子元件D2的过程中可能会损坏线路板D1上的连接部，导致该连接部无法再次与电子元件D2焊接。
为了解决这一问题，图6示出了一种线路板的叠层结构以及电子元件在线路板上的相对位置。参见图6，该线路板D1包括：衬底基板100、有源图案层400和电学图案层300。
衬底基板100的结构可以根据实际需要选择设置。例如，衬底基板100可以是刚性衬底。该刚性衬底例如可以包括玻璃衬底、石英衬底或塑料衬底。在此情况下，上述该线路板D1是刚性的。又如，衬底基板100还可以是柔性衬底。该柔性衬底例如可以包括聚酰亚胺衬底、聚甲基丙烯酸甲酯衬底、聚萘二甲酸乙二醇酯衬底等。在此情况下，该线路板D1是柔性的。
其中，衬底基板100可以为一层结构，还可以为多层结构。例如，衬底基板100可以包括至少一个柔性衬底和至少一个缓冲层，柔性衬底和缓冲层交替层叠设置。
继续参见图6，有源图案层400设置在衬底基板100的一侧。有源图案层400包括多个有源图案410，一有源图案410例如为上述像素电路Q中晶体管的有源图案410。示例性地，该晶体管可以是多晶硅晶体管，该晶体管(或者有源图案层400)具有有源区、位于有源区相对两侧的第一极区420和第二极 区430。其中，有源图案层400中位于有源区的部分可以称为有源图案410。第一极区420和第二极区430中的其中一者为源极区(可用作源极)，另一者为漏极区(可用作漏极)；二者的材料可以是经掺杂后的多晶硅，而呈现能够导电的性能。
继续参见图6，电学图案层300设置在有源图案层400远离衬底基板100的一侧。电学图案层300包括多个连接部。至少一个(例如一个，又例如多个)连接部与一有源图案410耦接。为了清楚描述方案，与有源图案410耦接的连接部可以称为第一连接部300a。
示例性地，与一有源图案410耦接的第一连接部300a可以有一个。该第一连接部300a可以与位于有源图案410两侧的第一极区420和第二极区430中的任一者耦接。例如，一第一连接部300a与一第二极区430耦接；基于此，在包含有源图案410的晶体管工作时，该第一连接部300a可以与该第二极区430具有相同电位，从而可以在像素电路Q的等效电路中等效为同一点。
又示例性地，与一有源图案410耦接的第一连接部300a可以有两个；其中一个第一连接部300a与位于该有源图案410一侧的第一极区420耦接，另外一个第一连接部300a与位于该有源图案410另一侧的第二极区430耦接。
通过上文对图3和图4的介绍可知，像素电路Q和电子元件D2存在耦接关系。具体地，像素电路Q中的至少一个有源图案410与电子元件D2耦接；例如图4中，第六晶体管T6的有源图案410和第七晶体管T7的有源图案410均与电子元件D2耦接。
电子元件D2可以包括与至少一个有源图案410耦接的引脚，称为第一引脚(例如正极)D21；具体地，第一引脚D21可以与一第一连接部300a耦接，并通过该第一连接部300a与至少一个有源图案410耦接。此外，电子元件D2还可以包括其他引脚，例如第二引脚(例如负极)D22。电学图案层300中的多个连接部还可以包括与电子元件D2的第二引脚D22耦接的连接部，称为第二连接部300b。例如，第二连接部300b可以与图4中的第二电源电压端VSS耦接，使得电子元件D2的第二引脚D22通过第二连接部300b与第二电源电压端VSS耦接。
此外，电学图案层300中的多个连接部可以包括第三连接部300c。在一种示例中，第三连接部300c与图4中的第一电源电压端VDD耦接，被配置为给上述的像素电路Q提供电源电压(例如供给电子元件D2的阳极的电源电压)。
连接部(第一连接部300a、第二连接部300b或第三连接部300c)包括沿 衬底基板100的厚度方向(如图6中示出的X方向)层叠设置的多个第一子层。多个第一子层中最远离衬底基板100的两个第一子层(位于最上方的两个第一子层)分别为第一导电子层320和第一防护子层310，第一防护子层310设置在第一导电子层320远离衬底基板100的一侧。例如，连接部包括两个第一子层，分别为第一导电子层320和第一防护子层310。又如，连接部包括三个以上(例如三个、四个、五个或者更多)第一子层，例如从上而下分别为第一防护子层310、第一导电子层320和至少一个其他子层。
由于在多个第一子层中，第一防护子层310设置在第一导电子层320远离衬底基板100的一侧，因此可以采用第一焊接材料T(主要成分为锡(Sn))对电子元件D2的引脚(例如第一引脚D21，又如第二引脚D22)和第一防护子层310进行焊接。在此过程中，第一焊接材料T与第一防护子层310形成第一金属间化合物，此外，第一焊接材料T与电子元件D2的引脚形成第三金属间化合物，从而实现电子元件D2与线路板D1的焊接。
金属与金属或金属与类金属(如H、B、N、S、P、C、Si等)形成的化合物，称为金属间化合物(Intermetallic Compound，缩写为IMC)。金属间化合物中元素之间以金属键结合，保持金属特性。金属间化合物是界面反应的产物。在采用第一焊接材料T对电子元件D2的引脚和第一防护子层310进行焊接的过程中，第一焊接材料T先在加热下被熔化；接着，第一防护子层310的材料被熔化，同时，电子元件引脚的材料也被熔化；随后，第一焊接材料T中的金属原子边扩散边分别与第一防护子层310中的金属原子和引脚中的金属原子反应，与第一防护子层310中的金属原子形成第一金属间化合物，与引脚中的金属原子形成第三金属间化合物。此外，随着第一焊接材料T继续扩散，第一焊接材料T中的金属原子还可以与第一导电子层320中的金属原子也形成第四金属间化合物。
可以理解的是，金属间化合物的形成速度与材料的组成、熔点，温度以及反应时间等有关。此外，两种扩散系数不同的金属，随着扩散进行，其二者所在膜层原有相接触的界面会发生移动，通常界面会向扩散系数大的金属所在膜层移动，在一些情况下，扩散系数大的金属所在膜层还会形成纳米或微米尺寸的空洞或者空隙等。
其中，在第一焊接材料T与第一防护子层310的至少一部分(例如部分，又如全部)形成第一金属间化合物之后，第一金属间化合物以及第一防护子层310中未形成第一金属间化合物的部分对第一焊接材料T进行一定的阻挡，使得第一焊接材料T扩散的速度变慢，从而有效阻止第一焊接材料T扩散到 第一导电子层320中。这样一来，即便焊接出现不良(如出现虚焊或者电子元件D2位置偏移)，需要进行维修，将电子元件D2去除的过程中，不容易将第一导电子层320也去除掉，不造成第一导电子层320的缺失，从而可以提高可维修率。
在一些示例中，第一导电子层320的材料包括铜，例如，为纯铜或者铜合金。但是铜或铜合金较易氧化。第一防护子层310为了防止第一导电子层320被氧化，第一防护子层310的抗氧化性能高于第一导电子层320的抗氧化性能。为了保障第一防护子层310具有较高的抗氧化性能，第一防护子层310的材料包括镍。此外，示例性地，第一防护子层310的材料可以不包含铜。又示例性地，第一防护子层310的材料可以包含铜；且第一防护子层310中，铜的原子百分比小于镍的原子百分比。
在一些示例中，第一防护子层310的材料为纯镍(Ni)。
在另一些示例中，第一防护子层310的材料为镍合金。示例性地，镍合金中，相较于掺杂的金属，镍的原子百分比最高。例如，第一防护子层310的材料为镍的原子百分比(可记为Ni at％)大于或等于40％(例如40％、50％、60％、70％、75％、80％、90％或99％)的镍合金。示例性地，镍合金可以是镍原子百分比大于或等于40％的Ni二元、三元、四元合金。
示例性地，第一防护子层310的材料还包括钨(Wu)、钒(V)、钯(Pd)、铝(Al)、钛(Ti)、锆(Zr)、钼(Mo)、铜(Cu)、钇(Y)、铌(Nb)、铂(Pt)、锡(Sn)、钽(Ta)、金(Au)和银(Ag)中的至少一者。这些掺杂的金属中的至少一者可以与镍形成镍合金。例如，镍合金可以为NiAl、NiV、NiTi、NiMo、NiCu或NiAg等。又示例性地，镍合金中，掺杂的金属可以全部不与第一焊接材料T(例如锡)反应，即无法与第一焊接材料T形成IMC。又示例性地，镍合金中可以掺杂有一种或多种可以与第一焊接材料T反应的金属。以下具体分析第一防护子层310的材料包括镍(Ni)的好处：
第一、Ni及Ni合金的键合效果好。
与焊接材料(例如第一焊接材料T)有良好反应的金属(例如，与锡(Sn)能够反应生成IMC的金属)有：金(Au)、银(Ag)、铜(Cu)、镍(Ni)、铁(Fe)等。其中，Ni及Ni合金键合效果好，浸润性好；同时进行金属掺杂后，可以提高Ni合金的抗氧化性。在高温回流焊接时，Ni与焊接材料中的Sn反应生成Ni 3Sn 2、Ni 3Sn 4、Ni 3Sn 7等IMC，IMC起到将电子元件D2与线路板D1上的连接部焊接的作用。参见图7a，Ni或Ni合金(例如，NiW合金、NIV合金等)能够与Sn反应生成IMC，且具有较好的浸润性，使得Sn能够 在Ni或Ni合金制成的层上铺展。此外，Au和Ag属于贵重金属成本较高，且Ag易氧化。Cu易氧化，且在Cu和Cu合金进行金属掺杂后也还是容易氧化。Fe易氧化腐蚀。因而，第一防护子层310的材料选用Ni或Ni合金。
此外，钼(Mo)、钨(W)、钛(Ti)等金属及其合金不与Sn反应，即无法与Sn反应并生成IMC。我们对这类金属或合金(例如，WTi合金、Mo合金、Ti等)也做了验证。参见图7b，在这类金属或合金(以W或W合金举例说明)制成的层上，Sn形成Sn球并发生内缩(即表明浸润性较差)，且Sn不与这类金属或合金反应。
第二、Ni及Ni合金的抗氧化性能优于Cu合金。
Ni合金在250℃或300℃退火处理后，反射率未明显降低(如图8a所示)，且电阻降低(如图9a所示)。Cu合金在退火温度高于150℃时发生氧化，导致反射率明显降低(如图8b所示)，且电阻上升(如图9b所示)。
第三、Ni及Ni合金的抗腐蚀性能强。
在高温高湿下，Ni合金的抗腐蚀性能大于Au的抗腐蚀性能，Au的抗腐蚀性能大于Cu合金的抗腐蚀性能。
第四、Ni合金的粘附性好。
由Ni合金制成的厚度为
Figure PCTCN2022114350-appb-000002
的单层薄膜(记为薄膜1)可以达到5B粘附性能。而Cu或其合金制成的厚度为
Figure PCTCN2022114350-appb-000003
的单层薄膜(记为薄膜2)会发生严重的脱落(peeling)。而若将薄膜2叠置在薄膜1上形成叠层结构，此时薄膜1用作薄膜2的缓冲层(buffer)，则增强了薄膜2的粘附力，叠层结构可达到5B性能。例如，连接部还可以包括其他第一子层，其他第一子层叠置在第一导电子层320远离第一防护子层310的一侧，且与第一导电子层320接触。其他第一子层的材料为Ni或Ni合金，从而增强第一导电子层320的粘附力。
第四、兼容常规的制备工艺，成本较低，更为环保，且量产可行性高。
例如，可以先沉积一层Ni或Ni合金，得到一薄膜，将该薄膜图案化形成第一防护子层310。这一步骤可以采用常规光刻工艺，成本低，无氰化物不污染环境；并且，由于兼容了现有产品所采用的工艺，能够适配当前产线，更容易实现量产。
又如，也可以依次沉积多个薄膜，再将多个薄膜一并图案化形成包含多个第一子层的连接部。同样地，具有上述效果，且进一步简化了制备工艺。
在一些实施例中，第一防护子层310的厚度为
Figure PCTCN2022114350-appb-000004
Figure PCTCN2022114350-appb-000005
Figure PCTCN2022114350-appb-000006
等。其中，随着第一防护子层310的厚度增加，第一防护子层310对第一焊接材料T的阻挡效果越好，从而避免第一焊接材料T与第一导电子层320形成金属间化合物。在第一防护子层310的厚度为
Figure PCTCN2022114350-appb-000007
的情况下，第一焊接材料T(例如刚好)可以扩散到第一导电子层320中，并与第一导电子层320形成金属间化合物。在第一防护子层310的厚度为
Figure PCTCN2022114350-appb-000008
的情况下，第一焊接材料T穿不过第一防护子层310，也就是说，第一焊接材料T不会扩散到第一导电子层320中。故第一防护子层的厚底为
Figure PCTCN2022114350-appb-000009
和
Figure PCTCN2022114350-appb-000010
是第一防护子层310的两个极限值，即
Figure PCTCN2022114350-appb-000011
为最小极限值，
Figure PCTCN2022114350-appb-000012
为最大极限值。
在一些实施例中，继续参见图6，线路板D1还包括栅图案层200。栅图案层200设置在衬底基板100上。栅图案层200包括多个栅极210；例如上述像素电路中晶体管的栅极210。
在本公开的实施例中，“图案层”可以是采用同一成膜工艺形成至少一个膜层，然后对这至少一个膜层执行构图工艺形成的包含特定图案的层结构。根据特定图案的不同，该构图工艺可能包括多次涂胶、曝光、显影或刻蚀工艺，而形成的层结构中的特定图案可以是连续的也可以是不连续的，这些特定图案还可能处于不同的高度(或者厚度)。栅图案层200可以采用金属材料制成，例如，可以是铝(Al)、银(Ag)、铜(Cu)、铬(Cr)、钛(Ti)、钼(Mo)等中的至少一者。
在一些示例中，栅图案层200设置在有源图案层400远离衬底基板100的一侧；基于此，像素电路中，该栅图案层200中的栅极210位于有源图案410的上方，此时该栅极210和该有源图案410对应的晶体管为顶栅型晶体管。在另一些示例中，像素电路中的晶体管可以全部为顶栅型晶体管。在又一些示例中，像素电路中，一些晶体管为顶栅型晶体管，一些晶体管为底栅型晶体管。
在一些实施例中，继续参见图6，线路板D1还包括：第一绝缘层M1和第二绝缘层M2，第一绝缘层M1将有源图案层400和栅图案层200间隔开，第二绝缘层M2位于有源图案层400、栅图案层200和第一绝缘层M1远离沉衬底基板100的一侧。
在一种可能的实现方式中，第一绝缘层M1设置在衬底基板100上，并覆盖有源图案层400。栅图案层200设置第一绝缘层M1上。第二绝缘层M2设置在第一绝缘层M1上，并覆盖栅图案层200。
基于此，线路板D1还包括贯穿第二绝缘层M2和第一绝缘层M1的多个 第一过孔。一第一过孔暴露出一晶体管的第一极区420或第二极区430。
继续参见图6，本公开的一些实施例中，线路板D1还包括：设置在电学图案层300和有源图案层400之间的转接图案层700。转接图案层700包括多个转接部710，转接部710与有源图案410和连接部均耦接。如上文所述，与有源图案410耦接的连接部称为第一连接部300a。那么，第一连接部300a可以通过转接部710与一晶体管的有源图案410耦接。
在一些示例中，两个转接部710可以分别与一晶体管的第一极区420和第二极区430耦接。具体地，转接部710的一部分可以贯穿第一过孔，而与一晶体管的第一极区420或第二极区430接触。此外，例如两个转接部710中的一个还可以与第一连接部300a耦接(例如接触)，另一个不与连接部耦接。又如，两个转接部710可以分别与电学图案层300中的两个连接部(例如两个第一连接部300a)耦接(例如接触)。
在另一些示例中，像素电路中的一些晶体管(例如图4中的第二晶体管T2)第一极和第二极仅仅和像素电路中的其他晶体管直接连接，而不需要与电子元件D2、或者信号输入端(例如，第一电源电压端VDD、数据线DL、初始化信号端Vinit等)直接相连。对于这些晶体管而言，一晶体管耦接的两个转接部710与电学图案层300均不耦接。
转接图案层700可以采用金属材料制成，例如，可以是铝(Al)、银(Ag)、铜(Cu)、铬(Cr)、镍(Ni)等金属单质，也可以是包含以上金属单质中至少一者的金属合金。转接图案层700还可以是叠层结构，例如由三个导电层堆叠而成。
为了减少有源图案层400受到光照，继续参见图6，线路板D1还包括遮光图案层500。遮光图案层500设置在有源图案层400与衬底基板100之间。在一些示例中，遮光图案层500的材料可以为金属材料，具体可以参考栅图案层200的材料的相关介绍。例如，遮光图案层500和栅图案层200的材料可以相同。为了避免有源图案层400与遮光图案层500直接接触，线路板D1还包括设置在遮光图案层500与有源图案层400之间的第三绝缘层M3。例如，第三绝缘层M3设置在衬底基板100上，并覆盖遮光图案层500。第一绝缘层M1和有源图案层400设置在第三绝缘层M3上。
在一些示例中，遮光图案层500可以包括多个遮光块510。遮光块510在衬底基板100上的正投影覆盖有源图案410在衬底基板100上的正投影。这样一来，由衬底基板100一侧照射到有源图案410的光能够被遮光图案层500遮挡，从而避免晶体管的特性因光照而发生变化。在另一些示例中，遮光图 案层500整体在衬底基板100上的正投影覆盖有源图案层400整体在衬底基板100上的正投影；这样能够更好地保护晶体管。
继续参见图6，为了在线路板中形成较为平坦的表面，以承载电学图案层300，线路板D1还可以包括：第四绝缘层M4，所述第四绝缘层M4设置在第二绝缘层M2上。第四绝缘层M4还覆盖转接图案层700。
在一些示例中，第四绝缘层M4包括第一平坦层PLN1和第一钝化层PVX1。其中，第一平坦层PLN1的材料为有机绝缘材料，因此也可以称为有机绝缘层，能够提供较为平坦的上表面；第一钝化层PVX1的材料为无机绝缘材料，因此也可以称为无机绝缘层，能够起到更好的绝缘效果。
例如，第一钝化层PVX1设置在第一平坦层PLN1远离衬底基板100的一侧。电学图案层300可以设置在第一钝化层PVX1远离衬底基板100的一侧。即，在X方向，第一平坦层PLN1、第一钝化层PVX1和电学图案层300依次堆叠。又如，第一平坦层PLN1和第一钝化层PVX1的位置可以互换。
基于此，线路板D1还包括贯穿第四绝缘层M4的多个第二过孔。至少一个第二过孔暴露出转接部710。
在一种可能的实现方式中，连接部的一部分穿过第二过孔与转接部710接触。例如第一连接部300a的一部分穿过第二过孔与一转接部710接触。又例如第一连接部300a的一部分穿过第二过孔与一转接部710接触，第三连接部300c的一部分穿过第二过孔与另一转接部710接触。
其中，该连接部的一部分可以是最靠近衬底基板100的导电子层(例如第一导电子层320，又例如第二导电子层340)和靠近衬底基板100一侧的其他第一子层。例如第一连接部300a包括第一防护子层310和第一导电子层320的情况下，该连接部的一部分可以是第一导电子层320(即为上述导电子层)。又例如第一连接部300a包括第一防护子层310、第一导电子层320、第二防护子层330、第二导电子层340和第一缓冲子层350的情况下，该连接部的一部分可以是第二导电子层340(即为上述的导电子层)和第一缓冲层(即为上述的其他第一子层)。
图10为图6中电学图案层300(例如第二连接部300b)的放大图。
参见图10，多个第一子层中的任意相邻两个第一子层，在衬底基板100上的正投影的面积之比为0.9～1.1。这样一来，由电学图案层通过一次刻蚀工艺可以形成多个连接部，从而减少工艺步骤。示例性地，相邻两个第一子层中，位置靠上的第一子层的下表面在衬底基板100上的正投影的面积，小于位置靠下的第一子层的下表面在衬底基板100上的正投影的面积。在一些示 例中，第一防护子层310的下表面和第一导电子层320的下表面在衬底基板100上的正投影的面积之比例如为0.9、0.91、0.92、0.93、0.95、0.97、0.99、1。与之类似地，第一导电子层320的下表面和第一防护子层310的下表面在衬底基板100上的正投影的面积之比例如为1.01、1.03、1.05、1.07、1.09、1.1等。
参见图10，连接部包括底面300-1和侧面300-2。底面300-1为连接部中最靠近且平行于衬底基板100的面；侧面300-2与底面300-1相邻接。其中，侧面300-2与底面300-1的夹角α为40°～90°。例如，连接部的底面300-1为图10中示出的下表面；连接部的侧面300-2可以是图10中示出的例如左侧面或右侧)。底面300-1与侧面300-2之间的夹角α例如为40°、45°、50°、55°、60°、65°、70°、75°、80°、85°、90°等。对于多个子层形成的连接部而言，不同子层的选材会影响这一角度。本实施例中，第一导电子层320选用铜或铜合金，第一防护子层310选用镍或镍合金；基于此，二者可以通过一次构图工艺(例如一起刻蚀)而形成，且能够产生良好的刻蚀角度，从而形成具有上述夹角α的连接部。
图11示出了本公开实施例提供的另一种线路板D1的叠层结构。与图6示出的线路板D1不同的是，图11示出线路板D1是通过多次构图工艺形成电学图案层300。其他结构可以参见图6相关的实施例的描述，在此不再赘述。
参考图11，在第四绝缘层M4上设置有电学图案层300，多个连接部还包括第四连接部800，第四连接部800与第一电源电压端VDD耦接。
在一些示例中，在第四绝缘层M4上堆叠形成第一导电子层320和第一防护子层310；刻蚀第一防护子层310中第四连接部800在第一防护子层310上正投影的部分，之后继续刻蚀形成第一连接部300a、第二连接部300b和第四连接部800。故本实例的第一连接部300a、第二连接部300b和第四连接部800可以通过多次工艺形成。
需要说明的是，图11中示出的第四连接部800与图6中的第三连接部300c结构不同，但作用相同(即均与第一电源电压端VDD耦接)。
图12示出了本公开实施例提供的又一种线路板D1的叠层结构。与图6示出的线路板D1不同的是，图12中的线路板D1对电学图案层300的第一防护子层310做了改进；其他结构可以参见图6相关的实施例的描述，在此不再赘述。
在一些示例中，与图6中第一防护子层310不同的是，图12示出的第一防护子层310覆盖第一导电子层320的外表面(即图12中的第一导电子层320 的上面、左侧面、和右侧面)。其中，形成图12示出的第一防护子层310可以通过多次构图工艺形成，这样可以将暴露的第一导电子层320包裹起来，进而防止第一导电子层320被氧化。
需要说明的是，图6、图11和图12示出的线路板中，由于连接部全部裸露，因此整个第一连接部或第二连接部可以作为焊盘p。
图13示出了本公开实施例提供的又一种线路板D1的叠层结构。相比于图6示出的线路板D1，图13示出的线路板D1中在第四绝缘层M4远离衬底基板100的一侧增设了第五绝缘层M5。其他结构可以参见图6相关的实施例的描述，在此不再赘述。
参见图13，线路板D1还包括第五绝缘层M5，第五绝缘层M5设置在第四绝缘层M4远离衬底基板100的一侧。其中，第五绝缘层M5包括堆叠设置的第二平坦层PLN2和第二钝化层PVX2。例如第二平坦层PLN2与第一钝化层PVX1接触。第二平坦层PLN2的材料可以是有机绝缘材料，因此第二平坦层PLN2还可以称为有机绝缘层。第二钝化层PVX2的材料可以是无机绝缘材料，因此第二钝化层PVX2还可以称为无机绝缘层。其中，第二平坦层PLN2覆盖电学图案层300。
在一些示例中，第二平坦层PLN2和第二钝化层PVX2上开设第三过孔，以暴露电学图案层300。例如暴露出第一连接部300a和第二连接部300b。使得电子元件D2的引脚在第三过孔处，可以与第一连接部300a和第二连接部300b焊接。
在一种可能的实现方式中，第三过孔暴露出的第一防护子层310与衬底基板100的上表面平行。也就是图13示出的第一防护子层310可以是水平面。
在一些示例中，参见图13，连接部(例如第一连接部300a和第二连接部300b)在第三通孔处裸露的部分可以是焊盘P，电子元件D2的引脚可以通过第一焊料焊T焊接在该焊盘P处，从而实现电子元件D2与线路板D1的耦接。其中，在下文中存在第三通孔的线路板D1，那么该线路板D1的焊盘P为连接部在第三通孔处裸露的部分(可参见图13示出的焊盘P的相关描述)，不再赘述。
图14示出了本公开实施例提供的又一种线路板D1的叠层结构。相比于图13示出的线路板D1，图14示出的线路板D1对电学图案层300作出改进。其他结构可以参见图13相关的实施例的描述，在此不再赘述。
参见图14，在第三绝缘层M4上形成第一导电子层320，在第一导电子层320上形成第五绝缘层M5，在第五绝缘层M5上开设第三过孔，以暴露出第 一导电子层320；在第三过孔内设置第一防护子层310。其中该第一防护子层310的形状可以与第三过孔形状相似或相同；例如均可以为锥形。从而图14示出的线路板D1中的电学图案层300和第五绝缘层M5与图13示出的线路板D1中的电学图案层300和第五绝缘层M5的工艺不相同。
在图14示出的线路板D1中的多个连接部包括第一连接部300a、第二连接部300b和第四连接部800。第四连接部800由第一导电子层320形成，并与第一电源电压端VDD耦接。
图15示出了本公开实施例提供的又一种线路板D1的叠层结构。相比于图13示出的线路板D1，图15示出的线路板D1中的电学图案层300增加了第二防护子层330和第二导电子层340。其他结构可以参见图13相关的实施例的描述，在此不再赘述。图16为图15中连接部(例如第二连接部300b)的放大图。图17为图15的一种替换结构图。图18为图17中连接部(例如第二连接部300b)的放大图。
参见图15～图18，多个第一子层还包括：设置在第一导电子层320靠近衬底基板100的一侧的至少一个(例如一个，又例如多个)第二导电子层340。示例性地，连接部可以包括三个第一子层，即第一子层的数量为三个，例如可以从靠近衬底基板100到远离衬底基板100的方向(例如从上到下)按照第一防护子层310、第一导电子层320和第二防护子层330的顺序依次堆叠。
在第一焊接材料T可能穿过第一防护子层310和第一导电子层320的情况下，例如，第一防护子层310的镍原子百分比较少和/或厚度较薄的情况下，虚焊或拆除电子元件D2时，仍然会破坏由第一防护子层310和第一导电子层320组成的连接部，在拆除电子元件D2后，电子元件D2无法再次与连接部实现稳固良好的连接；但是通过设置至少一个第二防护子层330，这样一来，即便第一防护子层310和第一导电子层320被破坏了，但是还存在第二防护子层330，那么电子元件D2的引脚还可以再次与第二防护子层330形成稳固良好的连接，从而实现了电子元件D2与连接部的耦接，进而提高了线路板D1的维修率。第二防护子层330被配置为阻碍第一焊接材料T的扩散。
多个第一子层还包括：设置在第一导电子层320靠近衬底基板100的一侧的至少一个(例如一个，又例如多个)第二防护子层330，第二导电子层340和第二防护子层330交替设置，且一第二防护子层330与第一导电子层320接触。示例性地，参见图15和图16示出连接部包括四个第一子层，即第一子层的数量为四个；例如可以靠近衬底基板100到远离衬底基板100的方向(例如从上到下)按照第一防护子层310、第一导电子层320、第二防护子 层330和第二导电子层340的顺序依次堆叠。
又示例性地，参见图17和图18示出连接部包括五个第一子层，即第一子层的数量为五个；例如可以从靠近衬底基板100到远离衬底基板100的方向(例如从上到下)按照第一防护子层310、第一导电子层320、第二防护子层330、第二导电子层340和第二防护子层330的顺序依次堆叠。此外，连接部还包括多个(例如六个、七个、八个等)第一子层，故第一子层的数量在此不做限定。
在第一焊接材料T可能穿过第一防护子层310、第一导电子层320和第二防护子层330的情况下，虚焊或拆除电子元件D2时，仍然会破坏由第一防护子层310、第一导电子层320和第二防护子层330组成的连接部，在拆除电子元件D2后，电子元件D2无法再次与连接部实现稳固良好的连接；但是通过设置至少一个第二导电子层340，这样一来，即便第一防护子层310、第一导电子层320和第二防护子层330被破坏了，但是还存在第二导电子层340，那么电子元件D2的引脚还可以再次与第二导电子层340形成稳固良好的连接，从而实现了电子元件D2与连接部的耦接，进而提高了线路板D1的维修率。
第二防护子层330的材料与第一防护子层310的材料包含的成分相同。例如，第二防护子层330的材料与第一防护子层310的材料均为纯镍或者镍合金；故第二防护子层330的材料成分可参考第一防护子层310的材料成分的相关描述，不再赘述；这样可以起到与第一防护子层310相同的效果，即阻碍第一焊接材料T的扩散。在一些示例中，第二防护子层330的材料包括镍的情况下，其中，第二防护子层330的材料中镍的原子百分比小于或等于第一防护子层310的材料中镍的原子百分比。在一些示例中，第二防护子层330的材料包括镍的情况下，其中，第二防护子层330的材料中镍的原子百分比可以与第一防护子层310的材料中镍的原子百分比完全相同。
图19示出了本公开实施例提供的又一种线路板D1的叠层结构。相比于图17示出的线路板D1，图19示出的线路板D1中包括两个第一连接部300a。其他结构可以参见图17相关的实施例的描述，在此不再赘述。
在一些示例中，参见图19示出的线路板D1包括第二连接部300b和两个第一连接部300a，其中两个第一连接部300a分别与两个转接部710耦接。电子元件的两个引脚分别与一第一连接部300a和第二连接部300b耦接。另一第一连接部300a还可以与第一电源电压端VDD耦接。此外图19示出的第一子层的数量和结构可以参考图18示出的第一子层的数量和结构的相关描述，不再赘述。
图20示出了本公开实施例提供的又一种线路板D1的叠层结构。相比于图13示出的线路板D1，图19示出的线路板D1中的电学图案层300增加了第一缓冲子层350。其他结构可以参见图13相关的实施例的描述，在此不再赘述。图21为图20电学图案层300(例如第二连接部300b)的放大图。
参见图20和图21，多个第一子层还包括第一缓冲子层350，第一缓冲子层350为多个第一子层中最靠近衬底基板100的一个；第一缓冲子层350的材料与第一防护子层310的材料和第一导电子层320的材料包含的成分均不同。在一些示例中，第一缓冲子层350的材料与第一防护子层310的材料均包括纯镍或镍合金；第一缓冲子层350的材料包括钼铌合金、钼镍钛合金、钼、钼合金、钛和钛铜合金中的至少一种。第一缓冲子层350也阻碍了第一焊接材料T的扩散。
相比于图17示出的线路板D1，图22示出的线路板D1中的电学图案层300增加了第一缓冲子层350。其他结构可以参见图17相关的实施例的描述，在此不再赘述。图23为图22电学图案层300(例如第二连接部300b)的放大图。
在一些示例中，参见图22和图23，多个第一子层包括依次堆叠(例如从上到下)的第一防护子层310、第一导电子层320、第二防护子层330、第二导电子层340和第一缓冲子层350。
在另一些示例中，多个第一子层包括依次堆叠(例如从上到下)的第一防护子层310、第一导电子层320、第二防护子层330和第一缓冲子层350。
图24为本公开实施例提供的又一种线路板D1的叠层结构。
在一些示例中，图24示出的线路板D1包括第二连接部300b和两个第一连接部300a，其中两个第一连接部300a分别与两个转接部710耦接。电子元件的两个引脚分别与一第一连接部300a和第二连接部300b耦接。另一第一连接部300a还可以与第一电源电压端VDD耦接。此外图24示出的第一子层的数量和结构可以参考图22示出的第一子层的数量和结构的相关描述，其他结构可以参见图22相关的实施例的描述，在此不再赘述。
图25示出了本公开实施例提供的又一种线路板D1的叠层结构。
参见图25，转接部710包括第一保护子层711和第二保护子层713中的至少一者，以及转接子层712；其中，第一保护子层711叠置在转接子层712靠近衬底基板100的一侧，且第一保护子层711的材料包括镍；第二保护子层713叠置在转接子层712远离衬底基板100的一侧，且第二保护子层713的材料包括镍。其中，第一保护子层711材料和第二保护子层713材料均可 以与第一防护子层310的材料相同，即第一保护子层711的材料包括镍和第二保护子层713的材料包括镍均可以参考第一防护子层310的材料包括镍的相关描述。转接子层712的材料与上述实施例中的公开的转接部710的材料相同。
示例性地，转接部710包括第一保护子层711和转接子层712。第一保护子层711叠置在转接子层712靠近衬底基板100的一侧，且第一保护子层711的材料包括镍。
第一保护子层711可以防止转接子层712的被氧化；在转接部710与连接部焊接时，第一保护子层711与该焊接材料形成金属间化合物，并且第一保护子层711还可以阻碍焊接材料的扩散；若转接部710远离衬底基板100一侧的连接部被移除后，第一保护子层711可能会被破坏，但是由于转接部710还包括转接子层712，进而电子元件还可以与转接部710的转接子层712实现再次固定连接。
示例性地，转接部710包括第二保护子层713和转接子层712。第二保护子层713叠置在转接子层远离衬底基板100的一侧，且第二保护子层713的材料包括镍。
若转接部710远离衬底基板100一侧的连接部被移除，会破坏转接子层712，但是转接部710还存在第二保护子层713，进而电子元件还可以与转接部710的第二保护子层713实现再次固定连接；其中，第二保护子层713可以阻碍该焊接材料的扩散。
示例性地，转接部710包括第一保护子层711、第二保护子层713和转接子层712。第一保护子层711叠置在转接子层712靠近衬底基板100的一侧，且第一保护子层711的材料包括镍。第二保护子层713叠置在转接子层712远离衬底基板100的一侧，且第二保护子层713的材料包括镍。
第一保护子层711可以防止转接子层712的被氧化；在转接部710与连接部焊接时，第一保护子层711与该焊接材料形成金属间化合物，并且第一保护子层711还可以阻碍焊接材料的扩散；在一些示例中，连接部从转接部710上移除后，可能会破坏第一保护子层711，但是转接部710还存在转接子层712和第二保护子层713，进而电子元件还可以与转接部710的转接子层712实现再次固定连接。
在另一些示例中，若转接部710远离衬底基板100一侧的连接部被移除后，第一保护子层711和转接子层712可能会被破坏，但是转接部710还存在第二保护子层713，进而电子元件还可以与转接部710的第二保护子层713 实现再次固定连接；其中，第二保护子层713可以阻碍该焊接材料的扩散。
继续参见图25，线路板D1中的栅极210包括第三保护子层211和第四保护子层213中的至少一者，以及栅导电子层212。第三保护子层211叠置在栅导电子层212靠近衬底基板100的一侧，且第三保护子层211的材料包括镍。第四保护子层213叠置在栅导电子层212远离衬底基板100的一侧，且第四保护子层213的材料包括镍。第三保护子层211的材料和第四保护子层213的材料均与第一防护子层310的材料相同，即第三保护子层211的材料包括镍和第四保护子层213的材料包括镍均可以参考第一防护子层310的材料包括镍的相关描述，不再赘述。栅导电子层212的材料可以参考上述公开实施例中的栅极210的材料的相关描述。
示例性地，栅极210包括第三保护子层211和栅导电子层212。第三保护子层211叠置在栅导电子层212靠近衬底基板100的一侧，且第三保护子层211的材料包括镍。
又示例性地，栅极210包括第四保护子层213和栅导电子层212。第四保护子层213叠置在栅导电子层212远离衬底基板100的一侧，且第四保护子层213的材料包括镍。
又示例性地，栅极210包括第三保护子层211、第四保护子层213和栅导电子层212。第三保护子层211叠置在栅导电子层212靠近衬底基板100的一侧，且第三保护子层211的材料包括镍。第四保护子层213叠置在栅导电子层212远离衬底基板100的一侧，且第四保护子层213的材料包括镍。
图26示出了本公开实施例提供的又一种线路板D1的叠层结构。其中，该有源图案层400的材质可以是氧化物半导体，例如该氧化物半导体可以是IGZO，IGTO，IZO，CAAC等。那么该晶体管为氧化物晶体管。
参见图26，两个转接部710分别耦接在第一极区420和第二极区430，且转接部710与第一极区420和第二极区430直接接触或直接搭接。这样一来，可以减薄线路板在X方向上的厚度。
在一些示例中，栅图案层200可以设置在衬底基板100上。第一绝缘层M1设置在衬底基板100上，第一绝缘层M1覆盖栅图案层200；有源图案层400设置在第一绝缘层M1远离衬底基板100的一侧。第四绝缘层M4设置在第一绝缘层M1上。例如第一钝化层PVX1设置在第一绝缘层M1上。使得第一平坦层PLN1覆盖有源图案层400和转接图案层700，即有源图案层400和转接图案层700同层设置。电学图案层300设置在第一钝化层PVX1；第二钝化层PVX2设置在第一钝化层PVX1上，并覆盖电学图案层300。在第一钝化 层PVX1上开设有连接第二过孔，以暴露出转接部710。从而该氧化物晶体管为底栅结构。
栅极210在衬底基板100上的正投影覆盖有源图案410的沟道区在衬底基板100上的正投影。电学图案层300还包括遮光部。遮光部在衬底基板100上的正投影覆盖有源图案410的沟道区在衬底基板100上的正投影。这样一来，对于晶体管(例如氧化物晶体管)而言，遮光部可以遮盖有源图案410远离衬底基板100的一侧，从而避免光照射在有源图案410远离衬底基板的一侧(即防止光照射在有源图案410的顶面上)。其中，有源图案410靠近衬底基板100的一侧设置有栅极210(即底栅结构)，利用栅极210可以避免光照射在有源图案410靠近衬底基板的一侧(即防止光照射在有源图案410的底面上)。遮光部包括层叠设置的多个第二子层；沿垂直于衬底基板100的方向，设置堆叠顺序相同的第二子层和第一子层的材料相同。
在一些示例中，连接部包括第一连接部300a、第二连接部b和第三连接部300c。其中第三连接部300c可以为上述的遮光部，即第三连接部300c包括的多个第一子层与遮光部包括的多个第二子层的设置堆叠顺序相同，并且沿垂直于衬底基板100的方向，设置堆叠顺序相同的第二子层和第一子层的材料也相同。
图27示出了本公开实施例提供的又一种线路板D1的叠层结构。通过多次工艺，可以形成氧化物晶体管和多晶硅晶体管的线路板D1。
参见图27，相比于图13，图27示出的线路板D1包括多晶硅晶体管和氧化物晶体管。其中，该氧化物晶体管包括其栅极、有源图案、第一极区和第二极区、转接部和绝缘层(例如第九绝缘层和第十绝缘层)等。
在一些示例中，第九绝缘层M9和第十绝缘层M10设置在第四绝缘层M4和第二绝缘层M2之间，氧化物晶体管的有源图案410a设置在第二绝缘层M2上，第九绝缘层M9覆盖在第二绝缘层M2上，栅极210a设置在第九绝缘层M9上，第十绝缘层M10覆盖在第九绝缘层M9上，转接部710a贯穿第九绝缘层M9和第十绝缘层M10与该氧化物晶体管的第一极区和第二极区耦接。第四绝缘层M4覆盖在第十绝缘层M10上。
这样一来，图27示出的线路板D1即可以形成多晶硅晶体管，同时还可以形成氧化物晶体管，从而减少了工艺步骤。
图28a示出了本公开实施例提供的一种功能背板。图28b为图28a在J处的放大图。
参见图28a和图28b，本申请还提供一种功能背板。功能背板10可以包 括上述的线路板D1和电子元件D2。电学图案层300中位于器件区SA的连接部通过第一焊接材料T与电子元件D2耦接。例如，电学图案层300中位于器件区SA的第一连接部300a和第二连接部300b分别与电子元件D2的第一引脚D21和第二引脚D22焊接。在一些示例中，电子元件D2的引脚可以通过固晶方式与连接部耦接。
位于器件区SA的连接部的第一防护子层310靠近第一焊接材料T的部分与第一焊接材料T形成第一金属间化合物K1。例如，第一连接部300a的第一防护子层310靠近第一焊接材料T的部分与第一焊接材料T形成第一金属间化合物K1。
电路板D3与位于绑定区SS的连接部通过第二焊接材料耦接。位于绑定区SS的连接部的第一防护子层310靠近第二焊接材料的部分与第二焊接材料形成第二金属间化合物。
电学图案层300还包括：位于绑定区SS的连接部(记为第五连接部)。第五连接部通过第二焊接材料与电路板D3耦接。其中，第五连接部的第一防护子层310靠近第二焊接材料的部分与第二焊接材料形成第二金属间化合物。
基于图13示出的线路板，图28a和图28b示出的功能背板。图29示出了本公开实施例又提供的一种功能背板，参见图29，在一些示例中，电子元件D2可以通过第二平坦层PLN2和第二钝化层PVX2焊接在连接部上。电子元件D2可以通过第三过孔焊接在连接部上。
图30示出了本公开实施例又提供的一种功能背板，可参见图14示出的线路板，图28a和图28b示出的功能背板，不再赘述。
本公开的实施例还提供一种线路板的制备方法。参见图31，线路板的制备方法S1000，包括步骤S100～S600，具体如下。
步骤S100：参见图32，在衬底基板100上形成遮光图案层LS，在衬底基板100上再形成第三绝缘层M3；遮光图案层LS包括多个遮光块。其中，第三绝缘层M3覆盖衬底基板100和遮光图案层LS。
在一些示例中，采用溅射工艺沉积遮光图案层LS，遮光图案层LS的材料为金属，该金属可以是金属单质Mo、Ti、Cu等，还可以是金属合金例如MTD、MoNb等。遮光图案层LS的厚度
Figure PCTCN2022114350-appb-000013
步骤S200：参见图33，在第三绝缘层M3上形成半导体图案层600(例如多晶硅)，再形成第一绝缘层M1。其中，第一绝缘层M1覆盖有源图案层400和第一绝缘层M1。
在一些示例中，气象沉积半导体图案层(例如为a-Si)，其
Figure PCTCN2022114350-appb-000014
(例如采用ELA技术)将a-Si改性为p-Si，并形成半导体图案层600。
步骤S300：参见图34，在第一绝缘层M1上形成栅图案层200，再形成第二绝缘层M2；栅图案层200包括多个栅极210。半导体图案层600经掺杂后形成有源图案层400，有源图案层400包括有源图案410、第一极区420和第二极区430。其中，第二绝缘层M2覆盖栅图案层200和第一绝缘层M1。
在一些示例中，通过气象沉积栅图案层200，栅图案层200的材料可以SiN和SiO中的至少一者。栅图案层200厚度
Figure PCTCN2022114350-appb-000015
步骤S400：参见图35，在第二绝缘层M2上形成转接图案层700。转接图案层700包括多个转接部710，两个转接部710分别与第一极区420和第二极区430耦接。其中，第一绝缘层和第二绝缘层开设有多个第一过孔，在形成转接图案层的同时，也沉积在第一过孔中形成导电部，即转接部710通过导电部与第一极区420或第二极区430耦接。
步骤S500：参见图36，有源图案层400的远离衬底基板100的一侧形成电学图案层300。电学图案层300包括多个连接部，连接部与有源图案410耦接。
在一些示例中，在第二绝缘层M2上形成第四绝缘层M4，第四绝缘层M4包括第一平坦层PLN1和第一钝化层PVX1；第一平坦层PLN1覆盖转接图案层700，在第一平坦层PLN1形成第一钝化层PVX1。在第一钝化层PVX1和第一平坦层PLN1上开设多个第二过孔，以暴露出与有源图案410的第一极区420和第二极区430。
在一些示例中，电学图案层300形成在第一钝化层PVX1上。连接部通过第二过孔与有源图案410耦接。
连接部包括层叠设置的多个第一子层。多个第一子层中最远离衬底基板100的两个第一子层分别为第一导电子层320和第一防护子层310，第一防护子层310设置在第一导电子层320远离衬底基板100的一侧，第一防护子层310的材料包括镍。
需要说明的是，步骤S500中的连接部可参考上述线路板D1公开实例中连接部的层数、以及每层的材料的相关描述，不再赘述。
第一子层的制备方法为：形成第一导电子层320。在第一导电子层320上形成第一防护子层310。
在一些示例中，设置的至少一个第二防护子层330。在第二防护子层330上形成第一导电子层320。在第一导电子层320上形成第一防护子层310。第二防护子层330的材料可以为MoNb、MTD、Mo、Mo合金、Ti、TiCu等。 第二防护子层330的厚度为
Figure PCTCN2022114350-appb-000016
第一导电子层320的材质为Cu等具有良好导电性能的金属。第一导电子层320的厚度可选为0.3μm-2μm。
在另一些示例中，形成交替设置的至少一个第二导电子层340和至少一个第二防护子层330。在第二防护子层330上形成第一导电子层320。在第一导电子层320上形成第一防护子层310。
在另一些示例中，形成第一缓冲子层350。在第一缓冲子层350上形成第一导电子层320。在第一导电子层320上形成第一防护子层310。
在一种可能的实现方式中，形成第一缓冲子层350。在第一缓冲子层350上形成交替设置的至少一个第二导电子层340和至少一个第二防护子层330。在第二防护子层330上形成第一导电子层320。在第一导电子层320上形成第一防护子层310。
其中，第一防护子层310、第一导电子层320、第二防护子层330、第二导电子层340和第一缓冲子层350的材料可参考上文中的相关描述。
步骤S600：参见图36，示例性地，在第一钝化层PVX1上沉积第二平坦层PLN2。在第二平坦层PLN2形成第二钝化层PVX2。其中，在第二钝化层PVX2和第二平坦层PLN2上开设多个第三过孔。
又示例性地，在第一钝化层PVX1上沉积第二钝化层PVX2。在第二钝化层PVX2形成第二平坦层PLN2。
在一些示例中，通过气象沉积第二钝化层PVX2，第二钝化层PVX2的材料可以是SiN和SiO其中的至少一者；第二钝化层PVX2的厚度
Figure PCTCN2022114350-appb-000017
Figure PCTCN2022114350-appb-000018
再通过光刻工艺形成第二平坦层PLN2，第二平坦层PLN2的厚度为2μm～5μm。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种线路板，包括：
    衬底基板；
    有源图案层，设置在所述衬底基板的一侧，包括多个有源图案；
    电学图案层，设置在所述有源图案层远离所述衬底基板的一侧，包括多个连接部，至少一个所述连接部与所述有源图案耦接；
    其中，所述连接部包括沿所述衬底基板的厚度方向层叠设置的多个第一子层，所述多个第一子层中最远离所述衬底基板的两个第一子层分别为第一导电子层和第一防护子层，所述第一防护子层设置在所述第一导电子层远离所述衬底基板的一侧，所述第一防护子层的材料包括镍。
  2. 根据权利要求1所述的线路板，其中，
    所述第一防护子层的材料为纯镍，或者，所述第一防护子层的材料为镍的原子百分比大于或等于40％的镍合金。
  3. 根据权利要求1或2所述的线路板，其中，
    所述第一防护子层的材料还包括钨、钒、钯、铝、钛、锆、钼、铜、钇、铌、铂、锡、钽、金和银中的至少一者。
  4. 根据权利要求1～3中任一项所述的线路板，其中，
    所述第一防护子层的厚度为
    Figure PCTCN2022114350-appb-100001
  5. 根据权利要求1～4中任一项所述的线路板，其中，
    所述多个第一子层还包括：设置在所述第一导电子层靠近所述衬底基板的一侧的至少一个第二防护子层，所述第二防护子层的材料包括镍。
  6. 根据权利要求5中任一项所述的线路板，其中，
    所述多个第一子层还包括：设置在所述第一导电子层靠近所述衬底基板的一侧的至少一个第二导电子层；所述第二导电子层和所述第二防护子层交替设置，且一第二防护子层与所述第一导电子层接触。
  7. 根据权利要求6所述的线路板，其中，
    所述第二防护子层的材料与所述第一防护子层的材料包含的成分相同。
  8. 根据权利要求5～7中任一项所述的线路板，其中，
    所述第二防护子层的材料中镍的原子百分比小于或等于所述第一防护子层的材料中镍的原子百分比。
  9. 根据权利要求1～8中任一项所述的线路板，其中，
    所述多个第一子层还包括第一缓冲子层，所述第一缓冲子层为所述多个第一子层中最靠近所述衬底基板的一个；所述第一缓冲子层的材料与所述第一防护子层的材料和所述第一导电子层的材料包含的成分均不同。
  10. 根据权利要求9所述的线路板，其中，
    所述第一缓冲子层的材料包括钼铌合金、钼镍钛合金、钼、钼合金、钛和钛铜合金中的至少一种。
  11. 根据权利要求1～10中任一项所述的线路板，其中，
    所述多个第一子层中的任意两个第一子层，在所述衬底基板上的正投影的面积之比为0.9～1.1。
  12. 根据权利要求1～11中任一项所述的线路板，其中，
    所述连接部包括底面和侧面，所述底面为所述连接部中最靠近且平行于所述衬底基板的面；所述侧面与所述底面相邻接；其中，所述侧面与所述底面的夹角为40°～90°。
  13. 根据权利要求1～12中任一项所述的线路板，还包括：
    设置在所述电学图案层和所述有源图案层之间的转接部，所述转接部与所述有源图案和所述连接部耦接。
  14. 根据权利要求13所述的线路板，其中，
    所述转接部包括第一保护子层和第二保护子层中的至少一者，以及转接子层；其中，所述第一保护子层叠置在所述转接子层靠近所述衬底基板的一侧，且所述第一保护子层的材料包括镍；所述第二保护子层叠置在所述转接子层远离所述衬底基板的一侧，且所述第二保护子层的材料包括镍。
  15. 根据权利要求1～14中任一项所述的线路板，还包括：
    栅图案层，设置在所述衬底基板上，包括多个栅极；所述栅极包括第三保护子层和第四保护子层中的至少一者，以及栅导电子层；其中，所述第三保护子层叠置在所述栅导电子层靠近所述衬底基板的一侧，且所述第三保护子层的材料包括镍；所述第四保护子层叠置在所述栅导电子层远离所述衬底基板的一侧，且所述第四保护子层的材料包括镍。
  16. 根据权利要求1～15中任一项所述的线路板，其中，
    栅图案层，设置在所述有源图案层与所述衬底基板之间，包括多个栅极，所述栅极在所述衬底基板上的正投影覆盖所述有源图案的沟道区在所述衬底基板上的正投影；
    所述电学图案层还包括：遮光部，所述遮光部在所述衬底基板上的正投影覆盖所述有源图案的沟道区在所述衬底基板上的正投影；所述遮光部包括层叠设置的多个第二子层；沿垂直于所述衬底基板的方向，设置堆叠顺序相同的所述第二子层和所述第一子层的材料相同。
  17. 一种功能背板，包括：
    如权利要求1～16中任一项所述的线路板；所述线路板具有器件区和绑定区；
    电子元件，设置在电学图案层远离衬底基板的一侧；
    其中，所述电学图案层中位于所述器件区的连接部通过第一焊接材料与所述电子元件耦接，其中，位于所述器件区的连接部的第一防护子层靠近所述第一焊接材料的部分与所述第一焊接材料形成第一金属间化合物。
  18. 根据权利要求17所述的功能背板，其中，
    所述电子元件包括发光器件、驱动元件或传感器件。
  19. 根据权利要求17～18所述的功能背板，还包括：
    电路板，与位于所述绑定区的连接部通过第二焊接材料耦接；其中，位于所述绑定区的连接部的第一防护子层靠近所述第二焊接材料的部分与所述第二焊接材料形成第二金属间化合物。
  20. 一种背光模组，包括：根据权利要求17～19中任一项所述的功能背板，所述电子元件为发光器件。
  21. 一种显示模组，包括：根据权利要求17～19中任一项所述的功能背板，所述电子元件为发光器件。
  22. 一种显示装置，包括：
    根据权利要求20所述的背光模组或根据权利要求21所述的显示模组。
  23. 一种线路板的制备方法，包括：
    在衬底基板上形成有源图案层，所述有源图案层包括多个有源图案；
    在形成有所述有源图案层的衬底基板上形成电学图案层，所述电学图案层包括多个连接部，所述连接部与所述有源图案耦接；其中，所述连接部包括层叠设置的多个第一子层，所述多个第一子层中最远离所述衬底基板的两个第一子层分别为第一导电子层和第一防护子层，所述第一防护子层设置在所述第一导电子层远离所述衬底基板的一侧，所述第一防护子层的材料包括镍。
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