WO2023230923A1 - 布线基板及制备方法、背板、显示装置 - Google Patents

布线基板及制备方法、背板、显示装置 Download PDF

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Publication number
WO2023230923A1
WO2023230923A1 PCT/CN2022/096478 CN2022096478W WO2023230923A1 WO 2023230923 A1 WO2023230923 A1 WO 2023230923A1 CN 2022096478 W CN2022096478 W CN 2022096478W WO 2023230923 A1 WO2023230923 A1 WO 2023230923A1
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WIPO (PCT)
Prior art keywords
pad
conductive
substrate
layer
conductive layer
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PCT/CN2022/096478
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English (en)
French (fr)
Inventor
王杰
许邹明
吴信涛
金枝
罗涛
罗宁雨
韩停伟
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方瑞晟科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280001585.1A priority Critical patent/CN117751692A/zh
Priority to PCT/CN2022/096478 priority patent/WO2023230923A1/zh
Publication of WO2023230923A1 publication Critical patent/WO2023230923A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate and a preparation method, a backplane, and a display device.
  • Mini LED Mini Organic Light-Emitting Diode, mini light-emitting diode
  • Micro LED Micro Organic Light-Emitting Diode, micro light-emitting diode
  • display device has the advantages of high brightness, clear display screen and low power consumption, and has good application prospects.
  • a wiring substrate in one aspect, includes a substrate, a conductive layer and a protective layer.
  • the conductive layer is located on one side of the substrate, the conductive layer includes a plurality of pad groups, and one pad group includes a plurality of conductive pads.
  • the protective layer is located on a side of the conductive layer away from the substrate, and the protective layer includes a plurality of openings; the portion of the conductive layer exposed to the openings is the conductive pad.
  • the maximum size of the conductive pad in a direction parallel to the substrate is greater than or equal to 1.5 times the minimum distance between the edge of the conductive pad and the edge of the conductive layer, and less than or Equal to 30 times the minimum distance between the edge of the conductive pad and the edge of the conductive layer.
  • the maximum size of the conductive pad in a direction parallel to the substrate is 0.5 to 5 times the distance between the conductive pad and an adjacent conductive pad.
  • the maximum dimension of the conductive pad in a direction parallel to the substrate is greater than or equal to 105 ⁇ m and less than or equal to 350 ⁇ m.
  • the area of the conductive pad is greater than or equal to 5000 ⁇ m 2 and less than or equal to 55000 ⁇ m 2 .
  • the distance between two adjacent conductive pads is greater than or equal to 70 ⁇ m and less than or equal to 214 ⁇ m.
  • the conductive layer includes a plurality of conductive lines, and the portion of the conductive lines exposed to the opening is the conductive pad; the conductive lines include a main surface and a side surface connected to the main surface. , wherein the main surface is a surface of the conductive line facing away from the substrate; the angle between the main surface and the side surface is greater than or equal to 105° and less than or equal to 145°.
  • the conductive layer includes a plurality of conductive lines, and the portion of the conductive lines exposed to the opening is the conductive pad; the conductive lines include a main surface and a plurality of conductive lines connected to the main surface. Side surfaces, wherein the main surface is a surface of the conductive line facing away from the substrate; at least two of the plurality of side surfaces that are shorter than the conductive pads of the conductive line are the first One side surface; the two first side surfaces are connected by a curved surface.
  • the orthographic projection of the curved surface on the substrate is a first rounded corner, and the radius of the first rounded corner is greater than or equal to 20 ⁇ m and less than or equal to 30 ⁇ m.
  • the wiring substrate includes multiple device areas.
  • the plurality of bonding pad groups include a plurality of first bonding pad groups and a second bonding pad group located in any device area; wherein the first bonding pad group includes spaced apart first electrode pads and a second electrode pad group. Diode pads; the second pad group includes at least spaced power pads, ground pads, address pads and output pads; the wiring substrate also includes source voltage lines and drive voltage lines.
  • the power pad is electrically connected to the source voltage line; the address pad is electrically connected to an output pad in another device area; the plurality of first welding pads are electrically connected to the source voltage line.
  • the first electrode pad in the first first pad group is electrically connected to the driving voltage line
  • the second electrode pad in the previous first pad group is electrically connected to the next first pad group.
  • the first pole pad in the first pad group is electrically connected
  • the second pole pad of the last first pad group is electrically connected to the output pad.
  • at least one of the first electrode pad, the power pad and the ground pad in the first first pad group has a maximum size in a direction parallel to the substrate, less than Or equal to 30 times the minimum distance between the edge of the pad and the edge of the conductive layer.
  • the wiring substrate includes a plurality of device areas and a control area.
  • the plurality of bonding pad groups include a plurality of first bonding pad groups located in any device area, and the first bonding pad group includes spaced apart first pole pads and second pole pads.
  • the plurality of pad groups further includes a second pad group located within the control area; the second pad group includes a power pad, a ground pad, an address pad and an output pad.
  • the wiring substrate further includes a source voltage line and a driving voltage line; the power pad is electrically connected to the source voltage line.
  • the first electrode pad in the first first pad group is electrically connected to the driving voltage line, and the previous first pad
  • the second pole pad in the group is electrically connected to the first pole pad in the next first pad group
  • the second pole pad of the last first pad group is electrically connected to the output pad.
  • the number of conductive layers is two.
  • the first conductive layer is located on one side of the substrate, and part of the conductive lines is located in the first conductive layer; the second conductive layer is located away from the first conductive layer.
  • On one side of the substrate another portion of the conductive lines is located in the second conductive layer.
  • one conductive line in the first conductive layer is connected to at least one conductive line located in the second conductive layer through a via hole, and the conductive line located in the second conductive layer is exposed to the The open part is the conductive pad.
  • the wiring substrate further includes: an oxidation protection layer and a conductive functional layer.
  • the oxidation protection layer covers the side of the conductive pad away from the substrate.
  • the conductive functional layer covers the side of the oxidation protection part away from the substrate.
  • a backplane in another aspect, includes: a plurality of functional components, at least one driver chip, and the wiring substrate as described in any of the above embodiments.
  • the plurality of pad groups in the wiring substrate include a first pad group and a second pad group; the first pad group is connected to the functional element, and the second pad group is connected to the driver chip connect.
  • a display device in another aspect, includes: a backlight module and a liquid crystal display panel.
  • the backlight module is the backplane provided in some of the above embodiments, and the functional components include light-emitting diodes.
  • the liquid crystal display panel is located on the light exit side of the backlight module.
  • a display device in another aspect, includes a display panel, and the display panel includes the backplane provided in some of the above embodiments.
  • a method of preparing a wiring substrate includes: forming a conductive layer on the substrate, wherein the conductive layer includes a plurality of pad groups, and one pad group includes a plurality of conductive pads.
  • a protective layer is formed on a side of the conductive layer away from the substrate, and an opening is formed on the protective layer, wherein the portion of the conductive layer exposed to the opening is the conductive pad;
  • the maximum dimension of the electrical pad in a direction parallel to the substrate is less than or equal to 30 times the minimum distance between the edge of the conductive pad and the edge of the conductive layer.
  • the step of forming a conductive layer on the substrate includes depositing a conductive material on the substrate to form an initial conductive layer.
  • a photoresist layer is formed on a side of the initial conductive layer away from the substrate.
  • the photoresist layer is baked at a specified temperature, where the specified temperature is greater than or equal to 125°C and less than or equal to 135°C.
  • the photoresist layer is exposed and developed to pattern the photoresist layer.
  • the initial conductive layer is etched based on the patterned photoresist layer to form the conductive layer.
  • the protective layer in the step of forming a protective layer on a side of the conductive layer away from the substrate, is formed through a chemical vapor deposition process.
  • Figure 1A is a structural diagram of a backplane according to some embodiments.
  • Figure 1B is a structural diagram of a driver chip according to some embodiments.
  • Figure 1C is a structural diagram of a backplane according to some embodiments.
  • Figure 1D is a block diagram of functional elements according to some embodiments.
  • Figure 2A is a cross-sectional view of a wiring substrate according to some embodiments.
  • Figure 2B is a cross-sectional view of a wiring substrate according to some embodiments.
  • Figure 2C is a cross-sectional view of a wiring substrate according to some embodiments.
  • Figure 2D is a structural diagram of a backplane according to some embodiments.
  • Figure 3 is a structural diagram of a wiring substrate according to some embodiments.
  • 4A is a cross-sectional view of a wiring substrate according to some embodiments.
  • Figure 4B is a cross-sectional view of a wiring substrate according to some embodiments.
  • Figure 4C is a schematic diagram of an activation reaction according to some embodiments.
  • Figure 5 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 6 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 7 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 8 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 9A is a partial enlarged view of D in Figure 7;
  • Figure 9B is a partial enlarged view of E in Figure 7;
  • Figure 10 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 11 is a structural diagram of a wiring substrate according to some embodiments.
  • Figure 12 is a partial enlarged view of F in Figure 11;
  • Figure 13 is a partial enlarged view of G in Figure 2A;
  • Figure 14 is a structural diagram of a display device according to some embodiments.
  • Figure 15 is a structural diagram of a display device according to some embodiments.
  • Figure 16 is a flow chart of a method of preparing a wiring substrate according to some embodiments.
  • Figure 17 is a flow chart of a method of preparing a wiring substrate according to some embodiments.
  • Figure 18 is a step diagram of a method of preparing a wiring substrate according to some embodiments.
  • Figure 19 is a step diagram of a method of preparing a wiring substrate according to some embodiments.
  • Figure 20 is a step diagram of a method of preparing a wiring substrate according to some embodiments.
  • Figure 21 is a step diagram of a method of preparing a wiring substrate according to some embodiments.
  • Figure 22 is a step diagram of a method of manufacturing a wiring substrate according to some embodiments.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its derivatives may be used.
  • some embodiments may be described using the term “connected” to indicate that two or more components are in direct physical or electrical contact with each other.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel and “equal” include the stated situation and situations that are similar to the stated situation, and the range of the similar situation is within an acceptable deviation range, where the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • the acceptable deviation Ranges are as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (ie, the limitations of the measurement system).
  • parallel includes absolutely parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°
  • “equal” includes absolute equality and approximately equal, wherein the acceptable deviation range of approximately equal may be, for example, The difference between two equals is less than or equal to 5% of either one.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • Figure 1A is a structural diagram of a backplane 1000 according to some embodiments.
  • some embodiments of the present disclosure provide a backplane 1000 that includes a wiring substrate 100 , a plurality of functional components 200 and at least one driver chip 300 .
  • a plurality of functional components 200 and at least one driver chip 300 are electrically connected to the wiring substrate 100, and a plurality of conductive lines 110 are provided in the wiring substrate 100, between the plurality of functional components 200, and between the functional components 200 and the driver chip 300. All can be electrically connected through conductive wires 110 .
  • the backplane 1000 may also include other electronic components (not shown in the figure), such as sensor chips, capacitors, resistors, inductors, etc.
  • the plurality of conductive lines 110 in the wiring substrate 100 include source address lines 111 , source voltage lines 112 , driving voltage lines 113 and common voltage lines 114 .
  • FIG. 1B is a structural diagram of a driver chip 300 according to some embodiments.
  • the driver chip 300 includes a power pin Pwr, a ground pin Gnd, an address pin Di, and an output pin Ot.
  • the source address line 111 is connected to the address pin Di of the driver chip 300 .
  • the source address line 111 is configured to transmit a first input signal including an address signal to gate the driver chip 300 of a corresponding address.
  • the addresses of different driver chips 300 may be the same or different.
  • the first input signal can be a digital signal with a bit width of 8 bits and includes address information. By analyzing the first input signal, the address to be transmitted can be obtained.
  • the source voltage line 112 is connected to the power pin Pwr of the driver chip 300 .
  • the source voltage line 112 is configured to transmit a second input signal including a power signal and/or a carrier communication signal to provide power to the driver chip 300 and/or transmit communication data.
  • the second input signal is a power signal and a carrier communication signal.
  • the second input signal not only provides power to the driver chip 300, but also transmits communication data to the driver chip 300.
  • the communication data can be used to control the working status of the corresponding functional component 200.
  • the driving voltage line 113 is connected to the output pin Ot of the driving chip 300 .
  • a plurality of functional elements 200 are provided on a circuit in which the driving voltage line 113 is connected to the output pin Ot of the driving chip 300 .
  • the driving voltage line 113 is configured to transmit a driving voltage and provide an operating voltage for the functional element 200 .
  • the output pin Ot of the driving chip 300 may provide a driving signal and/or a relay signal.
  • the driving signal is used to control the working state of the functional element 200
  • the relay signal is used to provide a first input signal to other driving chips 300 .
  • the common voltage line 114 is connected to the ground pin Gnd of the driver chip 300 .
  • Common voltage line 114 is configured to receive and transmit common voltage signals, including ground signals.
  • the backplane 1000 includes a plurality of device areas AA, where the device areas AA include a control area A2 and at least one sub-device area A1 connected to the control area A2.
  • the functional components are arranged in the sub-device area A1, and the driver chip 300 is arranged in the control area A2.
  • a plurality of functional components 200 and a driver chip 300 are provided in a device area AA, where a driver chip 300 is used to control multiple functional components. 200 working status.
  • Figure 1C is a structural diagram of another backplane 1000 according to some embodiments.
  • multiple device areas AA in the backplane 1000 are arranged in multiple rows and multiple columns.
  • the address pin Di of the driver chip 300 in one device area AA is electrically connected to the output pin Ot of the driver chip 300 in the other device area AA.
  • the direction pointed by the arrow X is the column direction X.
  • a device area AA is provided with multiple functional branches, wherein each functional branch includes multiple functional elements 200 connected in series, and the multiple functional branches are arranged in parallel.
  • one functional branch is provided in one device area AA, that is, all the functional elements 200 in one device area AA are arranged in series.
  • the number of functional elements 200 in a functional branch can be 4, 6, 9, etc., or more, and is not specifically limited here.
  • a plurality of functional elements 200 arranged in series in a device area AA, or a plurality of functional elements 200 arranged in series in a functional branch are electrically connected between the driving voltage line 113 and the output pin Ot.
  • a device area AA may be provided with multiple functional branches connected in parallel, and each functional branch includes at least one functional element 200.
  • each functional branch includes multiple functional elements 200, , the functional components 200 belonging to the same functional branch are connected in series, and there is no limit to the number of functional components in each functional branch; both ends of each functional branch are electrically connected to the driving voltage line 113 and the output pin respectively. Ot.
  • Figure ID is a bottom plan view of functional element 200 in accordance with some embodiments.
  • the functional element 200 has two pins, a first pin P and a second pin N respectively.
  • the first pin P of the first functional element 200A is electrically connected to the driving voltage line 113
  • the second pin N of the previous functional element 200 is electrically connected to the next functional element.
  • the first pin P in 200 is electrically connected
  • the second pin N of the last functional element 200 is electrically connected to the output pin Ot.
  • the previous functional element 200 and the next functional element 200 are two adjacent functional elements 200, and the length of the conductive line 110 between the previous functional element 200 and the driving voltage line 113 is longer than that between the next functional element 200 and the driving voltage line 113.
  • the length of conductive wire 110 between voltage wires 113 is the length of conductive wire 110 between voltage wires 113 .
  • the same device area AA includes 9 functional elements 200.
  • the 9 functional elements 200 are the first functional element 200A... the eighth functional element 200H and the ninth functional element in order. 200I.
  • the eighth functional element 200H is the previous functional element 200
  • the ninth functional element 200I is the next functional element 200.
  • the second pin N of the eighth functional element 200H is electrically connected to the first pin P of the ninth functional element 200I
  • the second pin N of the ninth functional element 200I is electrically connected to the output pin of the driver chip 300 Ot electrical connection.
  • Figure 2A is a cross-sectional view of wiring substrate 100 according to some embodiments.
  • some embodiments of the present disclosure provide a wiring substrate 100 , which includes a substrate 120 , a conductive layer 130 and a protective layer 140 .
  • the conductive layer 130 is located on one side of the substrate 120
  • the protective layer 140 is located on the side of the conductive layer 130 away from the substrate 120 .
  • the protective layer 140 includes a plurality of openings 141 , and the portion of the conductive layer 130 exposed to the openings 141 is a conductive pad 131 .
  • the substrate 120 is a flexible substrate, which allows the wiring substrate 100 and the backplane 1000 to bend.
  • the substrate 120 can also be a rigid substrate.
  • the material of the substrate 120 may include any of plastic, FR-4 grade material, resin, glass, quartz, polyimide or polymethyl methacrylate (English full name: Polymethyl Methacrylate, English abbreviation PMMA). one.
  • the protective layer 140 may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the protective layer 140 can protect the conductive layer 130 .
  • a conductive layer 130 may include multiple material layers.
  • the conductive layer 130 includes a copper (Cu) layer and two molybdenum niobium (MoNb) layers, where the two molybdenum niobium layers are respectively disposed on two opposite surfaces of the copper layer. It can be understood that one surface of the copper layer faces the substrate 120 and the other surface faces away from the substrate 120 .
  • the conductive layer 130 may be made of copper only.
  • the conductive layer 130 includes a plurality of conductive lines 110 , and the portion of the conductive lines 110 exposed to the opening 141 is a conductive pad 131 .
  • the opening 141 can be formed by etching the protective layer; in some cases, if the surface layer of the area of the conductive layer 130 exposed by the opening 141 is a molybdenum-niobium layer, it is necessary to further form a molybdenum-niobium layer. Etching is performed to expose the copper layer to ensure the solderability of the subsequent conductive pad 131 .
  • the wiring substrate includes two conductive layers 130 .
  • the first conductive layer 130A is located on one side of the substrate 120, and part of the conductive lines 110 is located in the first conductive layer 130A.
  • the conductive lines 110 located in the first conductive layer 130A may be called signal lines.
  • the signal lines located in the first conductive layer 130A include the above-mentioned source address line 111, source voltage line 112, driving voltage line 113 and common voltage line 114.
  • the second conductive layer 130B is located on a side of the first conductive layer 130A away from the substrate 120, and another portion of the conductive lines 110 is located in the second conductive layer 130B.
  • the other part of the conductive lines 110 located in the second conductive layer 130B is defined as the transfer line 115 .
  • one conductive line 110 in the first conductive layer 130A is connected to at least one conductive line 110 in the second conductive layer 130B through a via hole.
  • each signal line among the source address line 111, the source voltage line 112, the driving voltage line 113 and the common voltage line 114 is connected to at least one transfer line 115 through a via hole.
  • the portion of the conductive line 110 located in the second conductive layer 130B that is exposed to the opening 141 is the conductive pad 131 , that is, the portion of the transfer line 115 that is exposed to the opening 141 is the conductive pad 131 .
  • the wiring substrate 100 also includes other film layers. Based on the embodiment in which the wiring substrate 100 includes two conductive layers 130 , other film layers in the wiring substrate 100 will be introduced below.
  • a buffer layer 150 (English name: Buffer) 150 is provided on one side of the substrate 120 , and the buffer layer 150 is located between the substrate 120 and the first conductive layer 130A.
  • An insulating layer 160 is formed on the side of the first conductive layer 130A away from the substrate 120, and the insulating layer 160 is located between the second conductive layer 130B and the first conductive layer 130A.
  • the insulating layer 160 includes a first passivation layer PVX1, a first resin layer OC1 and a second passivation layer PVX2 sequentially disposed on the first conductive layer 130A.
  • a via hole is formed in the insulating layer 160 , and the second conductive layer 130B can be connected to the first conductive layer 130A through the via hole in the insulating layer 160 .
  • the first passivation layer PVX1 may be formed of an inorganic insulating material, such as SiN.
  • the first passivation layer PVX1, the second passivation layer PVX2 and the protective layer 140 are made of the same material.
  • the first resin layer OC1 may be formed of a resin material.
  • the wiring substrate 100 includes two conductive layers 130. In other embodiments, the wiring substrate 100 may include one conductive layer 130.
  • FIG. 2B is a cross-sectional view of the wiring substrate 100 according to some other embodiments.
  • the wiring substrate 100 includes a buffer layer 150 , a conductive layer 130 and a protective layer 140 which are sequentially stacked on the substrate 120 .
  • the protective layer 140 includes a third passivation layer PVX3 and a second resin layer OC2.
  • the conductive layer 130 may have a double-layer structure.
  • the conductive layer 130 may include two sub-conductive layers 130C.
  • the two sub-conductive layers 130C may be formed in two processes to avoid one process.
  • the conductive layer 130 formed is too thick.
  • FIG. 2C is a cross-sectional view of the wiring substrate 100 according to some other embodiments.
  • the conductive layer 130 may also be a single-layer structure.
  • the conductive layer 130 may also have a single-layer structure.
  • the first conductive layer 130A and/or the second conductive layer 130B includes two sub-conductive layers 130C.
  • the conductive layer 130 includes a plurality of pad groups 1300 , and one pad group 1300 includes a plurality of conductive pads 131 . Among them, a plurality of conductive pads 131 are arranged at intervals.
  • one pad group 1300 can be electrically connected to an electronic component, and the plurality of pad groups 1300 can be divided into multiple types. Each type of pad group 1300 is electrically connected to one type of electronic component, and different types of pad groups 1300 are electrically connected to one type of electronic component. Electrical connection of different electronic components.
  • the number of each pad group 1300 may be one or more.
  • the electronic components may include the above-mentioned functional components 200 and driver chips 300 .
  • the functional element can be an inorganic light-emitting diode, and the light-emitting area of the inorganic light-emitting diode does not exceed 300,000 ⁇ m 2 , specifically, it may not exceed 40,000 ⁇ m 2 ; the orthographic projection area of the driver chip 300 on the substrate 120 does not exceed 300,000 ⁇ m 2 .
  • Figure 2D is a structural diagram of the backplane 1000 according to some embodiments.
  • the backplane 1000 may also include other types of components, such as a circuit board 400 .
  • the circuit board 400 is located on one side of the wiring substrate 100 .
  • the wiring substrate 100 includes the functional area BB and the bonding area CC. It should be noted that in FIG. 2D , the dotted boxes indicated by BB and CC are only for illustrating the positions of the functional area BB and the bonding area CC, and do not necessarily indicate the positions of the functional area BB and the bonding area CC. The functional area BB and the binding area CC are further limited.
  • the plurality of device areas AA (shown in FIG. 1C ) are located in the functional area BB. Therefore, the plurality of pad groups 1300 (shown in FIGS. 2A and 2B ) are located in the functional area BB.
  • the plurality of conductive pads 131 also includes a circuit board pad 1310 .
  • the circuit board pad 1310 is located in the binding area CC.
  • the circuit board pad 1310 can be bound to the pins of the circuit board 400 .
  • electronic components such as the functional component 200, the driver chip 300 and the circuit board 400 can be fixed to the conductive pad 131 through surface assembly technology (or surface mount technology, full English name: Surface Mounted Technology, English abbreviation SMT) connect.
  • surface assembly technology or surface mount technology, full English name: Surface Mounted Technology, English abbreviation SMT
  • the pins of the functional element 200 and the pins of the driver chip 300 are connected to the conductive pad 131 through a welding process.
  • tin-based solder is used to solder the pins of the functional component 200 and the pins of the driver chip 300 .
  • intermetallic compounds IMC layers
  • Cu 6 Sn 5 intermetallic compounds
  • the IMC layer is a sign of a good connection between the pad and the device, but IMC is a brittle substance, and its excessive thickness will seriously reduce the reliability of the welding joint.
  • the nickel-gold process is introduced as a welding joint. A barrier layer in the disk structure to prevent the rapid generation of Cu-Sn compounds.
  • the barrier layer in the wiring substrate 100 also includes an oxidation protection layer 170 and a conductive functional layer 180, wherein the oxidation protection layer 170 covers the side of the conductive pad 131 away from the substrate 120, The conductive functional layer 180 covers the side of the oxidation protection layer 170 away from the substrate 120 .
  • the oxidation protection layer 170 By disposing the oxidation protection layer 170 on the side of the conductive pad 131 away from the substrate 120, the conductive pad 131 can be protected and the degree of oxidation of the conductive pad 131 can be reduced.
  • a conductive functional layer 180 is provided on the side of the oxidation protection layer 170 away from the conductive pad 131, thereby protecting the oxidation protection layer 170, that is, further protecting the conductive pad 131, reducing the risk of
  • the degree of oxidation of the conductive pad 131 and the oxidation protection layer 170 reduces the welding difficulty between the functional component 200, the driver chip 300 and the wiring substrate 100, and further improves the reliability of the connection between the functional component 200, the driver chip 300 and the wiring substrate 100. sex.
  • the material of the oxidation protection layer 170 includes nickel (Ni).
  • nickel is a conductive material.
  • Nickel can chemically react with materials (such as tin) in the solder to improve the wettability of the solder during soldering, thereby improving the soldering firmness between the functional component 200, the driver chip 300 and the conductive pad 131, and further improving the functional component 200 , the connection reliability between the driver chip 300 and the wiring substrate 100.
  • the conductive functional layer 180 includes conductive material, such as gold (Au).
  • the formation process of the oxidation protection layer 170 and the conductive functional layer 180 in some embodiments of the present disclosure is introduced below.
  • an electroless nickel-gold process may be used to form the oxidation protection layer 170 and the conductive functional layer 180 .
  • the wiring substrate 100 is first pickled, and then the wiring substrate 100 is placed in an activation solution containing Pd 2+ .
  • the Cu in the conductive pad 131 and the Pd 2+ in the activation solution A substitution reaction occurs to generate Cu 2+ and Pd (palladium), where Pd is attached to the surface of the Cu layer facing away from the substrate 120 to form a palladium layer.
  • the wiring substrate 100 is then placed in a solution whose main components are nickel sulfate, sodium hypophosphite (a reducing agent that reduces nickel ions to metallic nickel), and a complexing agent.
  • a layer of phosphorus-nickel alloy layer That is, the oxidation protection layer 170).
  • An immersion gold layer (that is, the conductive functional layer 180) is formed on the surface of the nickel alloy layer.
  • the gold particles in the immersion gold layer can fill the gaps in the nickel gold layer to reduce the oxidation probability of the phosphorus-nickel alloy layer, thereby weakening the conductive welding ability.
  • FIG. 3 is a structural diagram of the wiring substrate 100 according to some embodiments.
  • the oxidation protective layer 170 and the conductive functional layer 180 are formed at the conductive pad 131, but also near the conductive pad 131.
  • An oxidation protective layer 170 and a conductive functional layer 180 are also formed on the edge of the conductive line 110.
  • the oxidation protection layer 170 and the conductive functional layer 180 are formed on the edge of the conductive line 110.
  • the phenomenon is called abnormal growth phenomenon.
  • the area where the oxidation protection layer 170 and/or the conductive functional layer 180 is formed at the edge of the conductive line 110 is called an abnormal area. As shown in Figure 3, the area enclosed by the dotted box is the abnormal area.
  • Figure 4A is a cross-sectional view of wiring substrate 100 according to some embodiments.
  • Figure 4B is a cross-sectional view of wiring substrate 100 according to some embodiments.
  • step structure 1101 at the edge of the conductive line 110.
  • the step structure 1101 needs to be covered by the protective layer 140, and the step structure 1101 usually causes the protective layer 140 covered here to have a roof structure (Tip), and thus Fracture occurs, resulting in a loss of protection in the protective layer 140 at the step structure 1101, resulting in partial exposure of the step structure 1101. Therefore, in the electroless nickel gold process, the exposed area of the step structure 1101 is immersed in the activation solution, resulting in abnormal growth of the oxidation protection layer 170 and/or the conductive functional layer 180 at the step structure 1101 .
  • Tip roof structure
  • the oxidation protection layer 170 and the conductive functional layer 180 at the step structure 1101 expand into a spherical shape at the step structure 1101; in some cases, the oxidation protection layer 170 and the step structure 1101 are not completely In contact, that is, there is a gap between the two, and due to the existence of the gap, a path is provided for water and oxygen to corrode the conductive line 110 .
  • Parts of the abnormally grown oxidation protection layer 170 and/or the conductive functional layer 180 are connected in strips along the edges of the conductive lines 110 .
  • the oxidation protection layer 170 and/or the conductive functional layer 180 grows abnormally along the edge of the conductive line 110 and is easy to fall off when connected into strips. When falling off, it will produce pulling force on other positions of the conductive line 110, causing conduction. The portion of the wire 110 located near the abnormal area falls off together under the action of tension, causing the conductive wire 110 to break, thereby causing the functional element 200 connected to the conductive wire 110 to fail. In addition, if the detached abnormal growth overlaps the conductive pad 131, a short circuit will occur in the area where the conductive pad 131 is located, and ultimately the functional element 200 electrically connected to the conductive pad 131 will not work properly.
  • the maximum dimension L1 of the conductive pad 131 in the direction parallel to the substrate 120 is much larger than the minimum dimension L1 between the edge of the conductive pad 131 and the edge of the conductive layer 130 . Distance L2.
  • the orthographic projection of the conductive pad 131 on the substrate 120 can be a rectangle, a square, a pentagon or other polygons. In some examples, the orthographic projection of conductive pad 131 on substrate 120 may also be circular.
  • the maximum dimension of the conductive pad 131 in a direction parallel to the substrate 120 is the diameter of the circle. In the case where the conductive pad 131 is a convex polygon, please refer to FIG. 4B , the maximum dimension of the conductive pad 131 in the direction parallel to the substrate 120 is the length of the diagonal of the conductive pad 131 .
  • the conductive layer 130 includes a conductive line 110 , in which the conductive pad 131 is located at the end area of the conductive line 110 , and the surface of the conductive line 110 is exposed except where the conductive pad 131 is located. Except for this, the surfaces of other areas of the conductive line 110 are covered by other film layers (such as protective layers).
  • the edge of the conductive layer 130 refers to the edge of the conductive line 110 including the conductive pad 131 .
  • the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130 refers to the minimum distance between the edge of the conductive pad 131 and the edge of the conductive line 110 on which it is located.
  • the conductive line 110 has a plurality of edges, one or more of which have the smallest distance from the edge of the conductive pad 131 .
  • Figure 4C is a schematic diagram of an activation reaction according to some embodiments. Among them, it should be noted that the arrows in FIG. 4C indicate the movement direction of ions.
  • Pd 2+ is an important catalyst for precipitating nickel.
  • the Pd 2+ in the reaction area in the activation solution is rapidly consumed and deposited, while the Pd 2+ in the remaining areas diffuses and collects into the reaction area. Pd 2+ in the reaction area is replenished.
  • the reaction region is a region near the conductive pad 131 .
  • L1 is much larger than L2, and the area of the conductive pad 131 is too large.
  • the Pd 2+ in the reaction area in the activation solution is consumed too quickly, and the diffusion rate of Pd 2+ in the solution is too large, and then a palladium layer is rapidly deposited on the exposed step structure 1101, and the subsequent catalytic growth of the oxidation protection layer 170 and the conductive functional layer 180, resulting in abnormal growth.
  • FIG. 5 is a structural diagram of a wiring substrate 100 according to some embodiments.
  • the maximum dimension L1 of the conductive pad 131 in a direction parallel to the substrate 120 is greater than or equal to the distance between the edge of the conductive pad 131 and the edge of the conductive layer 130 1.5 times the minimum distance L2 between them, and less than or equal to 30 times the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5 ⁇ L2 ⁇ L1 ⁇ 30 ⁇ L2.
  • the maximum dimension L1 of the conductive pad 131 in the direction parallel to the substrate 120 is smaller, so that the Pd 2+ consumption rate in the reaction area in the activation solution is smaller, and the Pd 2+ consumption rate in the solution is smaller.
  • the diffusion speed of Pd 2+ is small, which can reduce the speed of depositing the palladium layer on the exposed step structure 1101 and slow down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180 , thereby reducing or even avoiding the occurrence of abnormal growth phenomena.
  • L1 ⁇ 1.5 ⁇ L2 therefore, it can be avoided that the maximum dimension L1 of the conductive pad 131 in the direction parallel to the substrate 120 is too small (for example, less than 1.5 ⁇ L2), thereby ensuring that the conductive pad 131 and Reliability of pin connections of electronic components.
  • FIG. 6 is a structural diagram of the wiring substrate 100 according to some embodiments.
  • the wiring substrate 100 includes a plurality of device areas AA.
  • the plurality of pad groups 1300 includes a plurality of first pad groups 1301 and a second pad group 1302 located in any device area AA.
  • the backplane 1000 includes a wiring substrate 100, and the device area AA in the wiring substrate 100 and the device area AA in the backplane 1000 are the same area.
  • FIG. 7 is a structural diagram of the wiring substrate 100 according to some embodiments.
  • a first pad group 1301 and a second pad group 1302 are shown in FIG. 7 .
  • the first pad group 1301 includes a first pole pad 131P and a second pole pad 131N arranged at intervals.
  • the number of conductive pads 131 in the first pad group 1301 is not limited to two. That is, in some examples, the first pad group 1301 may only include the first electrode pad 131P and the second electrode pad 131N; and in other examples, the first pad group 1301 may also include other electrodes. Conductive pad 131.
  • the orthographic projection of the first electrode pad 131P and the second electrode pad 131N on the substrate 120 may be a circle or a polygon such as a square, a rectangle, or a pentagon.
  • the first electrode pad 131P may be connected to the first pin P of the functional component 200
  • the second electrode pad 131N may be connected to the second pin N of the functional component 200 .
  • the functional component 200 and the first pin P and the second pin N of the functional component 200 are not shown in FIG. 7 . Please refer to FIG. 1D .
  • the area of the first electrode pad 131P is larger than the area of the first pin P
  • the area of the second electrode pad 131N is larger than the area of the second pin N, thereby ensuring the reliability of the connection between the functional component 200 and the wiring substrate 100 .
  • the second pad group 1302 at least includes spaced apart power pads Pwr', ground pads Gnd', address pads Di' and output pads Ot'.
  • the second pad group 1302 is connected to the driver chip 300 .
  • the power pad Pwr' is connected to the power pin Pwr of the driver chip 300
  • the ground pad Gnd' is connected to the ground pin Gnd of the driver chip 300
  • the address pad Di' is connected to the address pin Di of the driver chip 300
  • the disk Ot' is connected to the output pin Ot of the driver chip 300.
  • orthographic projections of the power pad Pwr', the ground pad Gnd', the address pad Di', and the output pad Ot' on the substrate 120 may be a circle or a polygon such as a square, a rectangle, or a pentagon. .
  • the address pad Di' and the output pad Ot' are respectively disposed opposite to two edges adjacent to the power pad Pwr'.
  • the address pad Di' and the output pad Ot' are also respectively welded to the ground. Two adjacent edges of the disk Gnd' are arranged opposite to each other.
  • the wiring substrate 100 also includes a source address line 111, a source voltage line 112, a driving voltage line 113 and a common voltage line 114.
  • the power pad Pwr' is electrically connected to the source voltage line 112; the address pad Di' is electrically connected to the output pad Ot' in another device area AA.
  • the power pad Pwr' is electrically connected to the source voltage line 112
  • the ground pad Gnd' is electrically connected to the common voltage line 114
  • the address pad Di' is electrically connected to the source address line 111
  • the output pad Ot' is electrically connected to the driving voltage line. 113 electrical connection.
  • the conductive pad 131 is located in the second conductive layer 130B.
  • the power pad Pwr' is connected to the source voltage line through the transfer wire 115 (as shown in FIG. 7).
  • 112 is electrically connected
  • the ground pad Gnd' is electrically connected to the common voltage line 114 through the adapter line 115
  • the address pad Di' is electrically connected to the source address line 111 through the adapter line 115
  • the output pad Ot' is connected to the driving voltage through the adapter line 115.
  • Line 113 is electrically connected.
  • the first electrode pad 131P in the first first pad group 1301A is electrically connected to the driving voltage line 113
  • the first electrode pad 131P in the first first pad group 1301A is electrically connected to the driving voltage line 113
  • the The first electrode pad 131P in a first pad group 1301A is connected to the first pin P (as shown in FIG. 1C ) of the first functional component 200A, thereby causing the first pin P of the first functional component 200A to Pin P is electrically connected to the driving voltage line 113 .
  • multiple device areas AA are arranged in multiple rows and multiple columns, wherein the first electrode pads 131P in the multiple first pad groups 1301A in one column of device areas AA are connected to the same driving voltage.
  • the lines 113 are connected, so the first pole pads 131P in the plurality of first pad groups 1301A are arranged in parallel.
  • the second pole pad 131N in the previous first pad group 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301.
  • the second electrode pad 131N of a first pad group 1301 is electrically connected to the output pad Ot'. It should be noted that the previous first pad group 1301 and the next first pad group 1301 refer to two adjacent first pad groups 1301.
  • one or more functional branches can be provided in the same device area AA, and one functional branch has a first functional element 200A (as shown in Figure 1C). It can be understood that, in the same device area AA There may be one or more first first pad groups 1301A in the device area AA.
  • the wiring substrate 100 includes two conductive layers 130, the second electrode pad 131N in the previous first pad group 1301 and the first electrode pad 131P in the next first pad group 1301 are respectively provided on Both ends of a patch cord 115.
  • the same device area AA includes 9 first pad groups 1301, and the 9 first pad groups 1301 are the first first pad group 1301A...the eighth... The first pad group 1301H and the ninth first pad group 1301I. Among them, the ninth first pad group 1301I is the last first pad group 1301.
  • the eighth first pad group 1301H is the previous first pad group 1301
  • the ninth first pad group 1301H is the previous first pad group 1301.
  • the first pad group 1301I is the next first pad group 1301.
  • the second pole pad 131N of the eighth first pad group 1301H is electrically connected to the first pole pad 131P of the ninth first pad group 1301I.
  • the first electrode pad 131P and the second electrode pad 131N in the first pad group 1301 are arranged adjacent to each other, and the first electrode pad 131P and the second electrode pad 131N are insulated from each other, and they need to be passed through functional components. 200 electrical connections.
  • At least one of the first pole pad 131P, the power pad Pwr′ and the ground pad Gnd′ in the first first pad group 1301A is in a direction parallel to the substrate 120
  • the maximum dimension L1 is less than or equal to 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130 .
  • the pad here refers to any of the first electrode pad 131P, the power pad Pwr' and the ground pad Gnd' in at least the first first pad group 1301A. one.
  • the activation solution may be a cathode, and the conductive layer 130 may be an anode. Since Cu in the conductive layer 130 loses electrons to form Cu 2+ , the electrons lost by Cu can flow in the conductive line 110 .
  • the first electrode pads 131P in the plurality of first pad groups 1301A connected to the same driving voltage line 113 undergo an electrochemical parallel reaction, that is, the first electrode pads 131P in the plurality of first pad groups 1301A
  • the first pole pads 131P are arranged in parallel. Therefore, electrons lost from the first electrode pad 131P in the plurality of first pad groups 1301A flow in the driving voltage line 113 . It can be understood that when the wiring substrate 100 includes two conductive layers 130 , the electrons lost by the first electrode pad 131P in the plurality of first pad groups 1301A are still connected to the driving voltage line 113 flows in the adapter line 115.
  • the current of the total circuit of the parallel circuit is equal to the sum of the currents of each branch. Therefore, the greater the number of conductive pads 131 electrically connected to the conductive line 110, the greater the current in the conductive line 110. . Since the number of conductive pads 131 electrically connected to the driving voltage line 113 is larger than the number of conductive pads 131 electrically connected to some other conductive lines 110, therefore, the current in the driving voltage line 113 is larger, thereby driving The current in the first electrode pad 131P in the first first pad group 1301A to which the voltage line 113 is electrically connected is relatively large.
  • the protective layer missing area around the first electrode pad 131P in the first first pad group 1301A is more likely to cause abnormal growth.
  • the power pads Pwr' in the plurality of second pad groups 1302 are all electrically connected to the source voltage line 112. Therefore, the plurality of power pads Pwr' are arranged in parallel, and the current in the source voltage line 112 is larger.
  • the replacement reaction speed of the plurality of power pads Pwr' electrically connected to the source voltage line 112 is faster, that is, the faster the palladium layer is formed, the easier it is to form the oxidation protection layer 170 and the conductive functional layer 180 subsequently. Therefore, the surrounding protective layer missing area in the power pad Pwr' (that is, the area where the step structure 1101 is exposed) is more likely to cause abnormal growth.
  • the ground pads Gnd' in the plurality of second pad groups 1302 are all electrically connected to the common voltage line 114. Therefore, the plurality of ground pads Gnd' are arranged in parallel, and the current in the common voltage line 114 is larger.
  • the replacement reaction speed of the multiple ground pads Gnd' electrically connected to the common voltage line 114 is faster, that is, the palladium layer is formed faster, and it is easier to form the oxidation protection layer 170 and the conductive functional layer 180 subsequently. Therefore, the area where the protective layer is missing around the ground pad Gnd' (that is, the area where the step structure 1101 is exposed) is more likely to cause abnormal growth.
  • At least one of the first electrode pad 131P, the power pad Pwr′ and the ground pad Gnd′ in at least the first first pad group 1301A is parallel to
  • the maximum dimension L1 in the direction of the substrate 120 is less than or equal to 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130 .
  • Abnormal growth in the protective layer missing area near at least one of the first electrode pad 131P, the power pad Pwr' and the ground pad Gnd' in the first first pad group 1301A can be reduced.
  • only the first electrode pad 131P, the power pad Pwr′ and the ground pad Gnd′ in the first first pad group 1301A may have the largest size in a direction parallel to the substrate 120 L1 is less than or equal to 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130 .
  • parts of the first electrode pad 131P, the power pad Pwr′ and the ground pad Gnd′ in the first first pad group 1301A may be aligned in a direction parallel to the substrate 120
  • the maximum dimension L1 on the pad is less than or equal to 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130 .
  • the maximum dimension L1 of all conductive pads 131 in the wiring substrate 100 in the direction parallel to the substrate 120 can be less than or equal to the distance between the edge of the pad and the edge of the conductive layer 130 The minimum distance is 30 times L2.
  • the device area AA in the wiring substrate 100 includes a sub-device area A1 and a control area A2.
  • the device area AA includes at least two sub-device areas A1 and a control area A2.
  • FIG. 8 is a structural diagram of the wiring substrate 100 according to some embodiments.
  • the device area AA includes at least two sub-device areas A1 and a control area A2.
  • the plurality of pad groups 1300 include a plurality of first pad groups 1301 located in any sub-device area A1, and the first pad groups 1301 include spaced apart first pole pads 131P and second pole pads 131N.
  • the first pad group 1301 is used to connect with the functional component 200 .
  • the plurality of pad groups 1300 also includes a second pad group 1302 located in the control area A2; the second pad group 1302 includes a power pad Pwr', a ground pad Gnd', an address input pad Din', an address output pad Pad Dio' and at least two output pads (Ot1' and Ot2', etc.).
  • the power pad Pwr' is electrically connected to the source voltage line 112.
  • the address output pad Dio' in the control area A2 in one of the two different device areas AA is connected to the address input pad Din' in the control area A2 in the other device area AA.
  • the first electrode pad 131P in the first first pad group 1301A is electrically connected to the driving voltage line 113
  • the previous first pad group 1301A is electrically connected to the driving voltage line 113.
  • the second pole pad 131N in 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301, and the second pole pad 131N of the last first pad group 1301I is electrically connected to an output pad Otx 'Electrical connection, where x can be a positive integer greater than or equal to 2.
  • the second electrode pad 131N of the last first pad group 1301I of each sub-device area A1 in the plurality of sub-device areas A1 is respectively connected to an output pad Otx' in the control area A2.
  • the output pad Ot2' is the output pad Otx' at this time
  • the second of the last first pad group 1301I in one sub-device area A1 The pole pad 131N is connected to the output pad Ot1'
  • the second pole pad 131N of the last first pad group 1301I in the other sub-device area A1 is connected to the output pad Ot2'.
  • At least the maximum size of the first electrode pad 131P in the first first pad group 1301A in the direction parallel to the substrate 120 is less than or equal to the edge of the first electrode pad 131P to the conductive layer 130 30 times the minimum distance between edges.
  • the first electrode pads 131P in the first first pad group 1301A of each sub-device area A1 in the multiple sub-device areas A1 belonging to the same device area AA are arranged in parallel. As can be seen from the above, a conductive line 110 is connected in parallel.
  • the greater the number of conductive pads 131 the faster the replacement reaction speed of the conductive pads 131 in the conductive line 110 , that is, the faster the palladium layer is formed, and the easier it is to subsequently form the oxidation protection layer 170 and the conductive functional layer 180 . Therefore, the protective layer missing area near the first electrode pad 131P in the first first pad group 1301A (ie, the area where the step structure 1101 is exposed) is more likely to cause abnormal growth.
  • the maximum dimension L1 of the first electrode pad 131P in the first first pad group 1301A in the direction parallel to the substrate 120 be less than or equal to the edge of the first electrode pad 131P to the conductive layer 130 30 times the minimum distance between edges can reduce abnormal growth in the protective layer missing area near the first electrode pad 131P in the first first pad group 1301A.
  • the wiring substrate 100 may include a device area AA, which includes a plurality of sub-device areas A1 and a control area A2.
  • the plurality of pad groups 1300 includes a plurality of first pad groups 1301 located in any sub-device area A1.
  • a light-emitting branch is provided in a sub-device area A1.
  • the plurality of pad groups 1300 also includes a second pad group 1302 located in the control area A2; the second pad group 1302 includes a power pad Pwr', a ground pad Gnd', an address pad Di' and a plurality of output pads. Disk Ot', where the number of output welds Ot' is the same as the number of light-emitting branches.
  • the first electrode pad 131P in the first first pad group 1301A is electrically connected to the driving voltage line 113, and the previous first pad group 1301A is electrically connected to the driving voltage line 113.
  • the second pole pad 131N in the pad group 1301 is electrically connected to the first pole pad 131P in the next first pad group 1301, and the second pole pad 131N of the last first pad group 1301I is electrically connected to an output pad. DiskOt' electrical connection. It should be noted that the second electrode pads 131N of the last first pad group 1301I in all sub-device areas A1 are respectively connected to different output pads Ot'.
  • control area A2 can also be provided with only one output. Solder Ot'.
  • the second electrode pad 131N of the last first pad group 1301I in each sub-device area A1 is connected to the same output pad Ot'.
  • the second electrode pads 131N of the last first pad group 1301I in the multiple sub-device areas A1 are arranged in parallel. Therefore, the protective layer near the second electrode pads 131N of the last first pad group 1301I is missing. Areas prone to abnormal growth.
  • the maximum dimension L1 of the second electrode pad 131N of the last first pad group 1301 in the direction parallel to the substrate 120 may be less than or equal to the edge of the conductive pad to the conductive layer 130 The minimum distance between edges is 30 times L2.
  • the first pole pad 131P in the first first pad group 1301A and/or the second pole pad 131N in the last first pad group 1301 can be positioned parallel to the substrate 120
  • the maximum dimension L1 in the direction is less than or equal to 30 times the minimum distance L2 between the edge of the pad and the edge of the conductive layer 130 .
  • FIG. 9A is a partial enlarged view of D in FIG. 7 .
  • FIG. 9A shows a first pad group 1301 .
  • the maximum dimension L11 of the conductive pad 131 in the first pad group 1301 in the direction parallel to the substrate 120 is greater than or equal to the distance between the edge of the conductive pad 131 and the edge of the conductive layer 130 1.5 times the minimum distance L21, and less than or equal to 28 times the minimum distance L21 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5 ⁇ L21 ⁇ L11 ⁇ 28 ⁇ L21.
  • the conductive pads 131 in the first pad group 1301 refer to the first pole pad 131P and the second pole pad 131N.
  • the maximum size L11 of the conductive pads 131 in the first pad group 1301 in the direction parallel to the substrate 120 is smaller, so that the corresponding first pad in the activation solution can be
  • the Pd 2+ consumption rate in the reaction area of the conductive pad 131 in the group 1301 is small, and the Pd 2+ diffusion rate is small, thereby reducing the deposition of the exposed step structure 1101 near the conductive pad 131 in the first pad group 1301
  • the speed of the palladium layer slows down the subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thereby reducing the occurrence of abnormal growth phenomena, or even avoiding the occurrence of abnormal growth phenomena.
  • L11 ⁇ 1.5 ⁇ L21 therefore, it can be avoided that the maximum size L11 of the conductive pads 131 in the first pad group 1301 in the direction parallel to the substrate 120 is too small (for example, less than 1.5 ⁇ L21), thereby ensuring Reliability of the pin connection between the conductive pad 131 and the functional component 200 .
  • FIG. 9B is a partial enlarged view of E in FIG. 7 .
  • the maximum dimension L12 of the conductive pad 131 in the second pad group 1302 in the direction parallel to the substrate 120 is greater than or equal to the edge of the conductive pad 131 to the conductive layer. 1.5 times the minimum distance L22 between the edges of the conductive pad 130, and less than or equal to 26 times the minimum distance L22 between the edge of the conductive pad 131 and the edge of the conductive layer 130, that is, 1.5 ⁇ L22 ⁇ L12 ⁇ 26 ⁇ L22 .
  • the conductive pads 131 of the second pad group 1302 refer to the power pad Pwr', the ground pad Gnd', the address pad Di' and the output pad Ot'.
  • the maximum size L12 of the conductive pads 131 in the second pad group 1302 in the direction parallel to the substrate 120 is smaller, so that the corresponding second pad in the activation solution can be
  • the Pd 2+ consumption rate in the reaction area of the conductive pad 131 in the group 1302 is smaller, and thus the Pd 2+ diffusion rate is smaller, which can reduce the exposed step structure 1101 near the conductive pad 131 in the second pad group 1302
  • the speed of depositing the palladium layer slows down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thereby reducing the occurrence of abnormal growth phenomena, or even avoiding the occurrence of abnormal growth phenomena.
  • L12 ⁇ 1.5 ⁇ L22 therefore, it can be avoided that the maximum size L12 of the conductive pads 131 in the second pad group 1302 in the direction parallel to the substrate 120 is too small (for example, less than 1.5 ⁇ L22), thereby ensuring The reliability of the connection between the conductive pad 131 and the pin of the driver chip 300.
  • the maximum size L1 of the conductive pad 131 in the direction parallel to the substrate 120 is the same as that of the conductive pad 131 .
  • the distance between adjacent conductive pads 131 is 0.5 to 5 times of L3, that is, 0.5 ⁇ L3 ⁇ L1 ⁇ 5 ⁇ L3.
  • two adjacent conductive pads 131 are located in the same pad group 1300 .
  • the distance L3 between one conductive pad 131 and an adjacent conductive pad 131 is the minimum distance between them.
  • two adjacent conductive pads 131 in the same pad group 1300 may be respectively disposed on two conductive lines 110 .
  • the spacing between the two adjacent conductive pads 131 will be affected by the spacing between the two conductive lines 110 where the two adjacent conductive pads 131 are located.
  • two adjacent conductive pads 131 in the same pad group 1300 may be located on the same conductive line 110.
  • the driver chip 300 includes two ground pins Gnd.
  • the driver chip 300 includes two ground pins Gnd.
  • the second pad group 1302 connected to 300 includes two ground pads Gnd'.
  • the ground pins Gnd in the driver chip 300 are separated from each other. Therefore, the two ground pads Gnd' are spaced apart from each other. At this time, the two ground pads Gnd' can be disposed on the same conductive line 110.
  • the two ground pads Gnd' are arranged adjacent to each other, and the shape of the two ground pads Gnd' and the spacing between them may be limited by the sum of the line widths of the conductive lines 110 where the two ground pads Gnd' are located. /or line length. At this time, the smaller the line width and/or the line length of the conductive line 110 where the two ground pads Gnd' are located, the smaller the distance between the two ground pads Gnd' will be.
  • each conductive pad in any first pad group is basically the same as the relative positional relationship of each pin of an electronic component to be connected to the first pad group;
  • the relative positional relationship of each conductive pad in the two pad groups is basically the same as the relative positional relationship of each pin of an electronic component to be connected to the second pad group.
  • 0.5 ⁇ L3 ⁇ L1 ⁇ 5 ⁇ L3 can avoid L1 being too large (for example, greater than 5 ⁇ L3), which can make the Pd 2+ consumption rate in the reaction area in the activation solution smaller and the Pd 2+ diffusion in the solution The speed is smaller, which in turn can reduce the speed of depositing the palladium layer on the exposed step structure 1101 and slow down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thereby reducing the occurrence of abnormal growth phenomena and even avoiding the occurrence of abnormal growth phenomena. .
  • L1 can also be avoided from being too small (for example, less than 0.5 ⁇ L3), thereby ensuring the reliability of the pin connection between the conductive pad 131 and the electronic component.
  • the maximum dimension L1 of the conductive pad 131 in the direction parallel to the substrate 120 is greater than or equal to 105 ⁇ m and less than or equal to 350 ⁇ m.
  • the consumption speed of Pd 2+ is small, and the diffusion speed of Pd 2+ is small, which can slow down the speed of depositing the palladium layer on the exposed step structure 1101, thereby slowing down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thus Reduce the occurrence of abnormal growth phenomena, or even avoid abnormal growth phenomena.
  • L1 is too small (for example, less than 105 ⁇ m), resulting in lower reliability of the pin connection between the conductive pad 131 and the electronic component.
  • the “electronic component” here includes the above-mentioned functional component 200 and driver chip 300. In some embodiments of the present disclosure, by making L1 greater than or equal to 105 ⁇ m, the reliability of the pin connection between the conductive pad 131 and the electronic component can be ensured.
  • the maximum dimension L11 of the conductive pad 131 in the first pad group 1301 in a direction parallel to the substrate 120 is greater than or equal to 105 ⁇ m and less than or equal to 350 ⁇ m.
  • the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130 is greater than or equal to 7 ⁇ m and less than or equal to 50 ⁇ m.
  • the conductive pads 131 in the first pad group 1301 are rectangular.
  • the length L4 of the conductive pads 131 in the first pad group 1301 is greater than or equal to 2 ⁇ L21 and less than or equal to 25 ⁇ L21.
  • the length L4 of the conductive pads 131 in the first pad group 1301 is greater than or equal to 80 ⁇ m and less than or equal to 280 ⁇ m.
  • the value of L4 can be 102 ⁇ m, 162 ⁇ m, 264 ⁇ m, etc.
  • the width L5 of the conductive pads 131 in the first pad group 1301 is greater than or equal to L21 and less than or equal to 20 ⁇ L21.
  • the width L5 of the conductive pads 131 in the first pad group 1301 is greater than or equal to 45 ⁇ m and less than or equal to 220 ⁇ m.
  • the value of L5 can be 62 ⁇ m, 122 ⁇ m, 205 ⁇ m, etc.
  • the maximum dimension L12 of the conductive pad 131 in the second pad group 1302 in the direction parallel to the substrate 120 is greater than or equal to 105 ⁇ m and less than or equal to 190 ⁇ m.
  • the conductive pads 131 of the second pad group 1302 are square. At this time, the side length L6 of the conductive pads 131 in the second pad group 1302 is greater than or equal to 1.5 ⁇ L22 and less than or equal to 20 ⁇ L22.
  • L6 is greater than or equal to 70 ⁇ m and less than or equal to 140 ⁇ m.
  • the value of L6 can be 82 ⁇ m, 92 ⁇ m, 122 ⁇ m, etc.
  • the area size of the conductive pads 131 in at least two pad groups 1300 is positively correlated with the distance L3 between two adjacent conductive pads 131 .
  • the conduction can be reduced.
  • the Pd 2+ consumption rate in the reaction area corresponding to the pad group 1300 where the electric pad 131 is located can thereby reduce the Pd 2+ diffusion rate in the solution, thereby reducing the rate at which the palladium layer is deposited on the exposed step structure 1101 and slowing down
  • the subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180 speeds up the process, thereby reducing the occurrence of abnormal growth phenomena, or even avoiding the occurrence of abnormal growth phenomena.
  • the area of the conductive pad 131 in one of the pad groups 1300 is larger than the area of the conductive pad 131 in the other pad group 1300 , and the conductive pad 131 with the larger area is The distance L3 between the electrical pad 131 and the adjacent conductive pad 131 is greater than the distance L3 between two adjacent conductive pads 131 in another pad group 1300 .
  • the area of the conductive pad 131 in one of the pad groups 1300 is larger than the area of the conductive pad 131 in the other pad group 1300 , and the area is larger.
  • the distance L3 between the large conductive pad 131 and the adjacent conductive pad 131 is smaller than the distance L3 between two adjacent conductive pads 131 in another pad group 1300 .
  • the area of the conductive pad 131 is greater than or equal to 5000 ⁇ m 2 and less than or equal to 55000 ⁇ m 2 .
  • the area of the conductive pad 131 can be avoided from being too large.
  • the Pd 2+ consumption rate in the reaction area in the activation solution is slower, and the Pd 2+ diffusion rate in the solution is slower, which in turn reduces the rate at which the palladium layer is deposited on the exposed step structure 1101 and slows down subsequent catalytic growth and oxidation protection.
  • the speed of the layer 170 and the conductive functional layer 180 is thereby reduced or even prevented from occurring.
  • the area of the conductive pad 131 is made greater than or equal to 5000 ⁇ m 2 , the area of the conductive pad 131 can be avoided from being too small, thereby ensuring the reliability of the pin connection between the conductive pad 131 and the electronic component.
  • the area of the conductive pad 131 in the first pad group 1301 is greater than or equal to 5000 ⁇ m 2 and less than or equal to 55000 ⁇ m 2 .
  • the area of the conductive pad 131 in the first pad group 1301 is greater than or equal to 6200 ⁇ m 2 and less than or equal to 54700 ⁇ m 2 .
  • the area of the conductive pad 131 in the second pad group 1302 is greater than or equal to 5500 ⁇ m 2 and less than or equal to 15500 ⁇ m 2 .
  • the area of the conductive pad 131 in the second pad group 1302 is greater than or equal to 6600 ⁇ m 2 and less than or equal to 15000 ⁇ m 2 .
  • the distance L3 between two adjacent conductive pads 131 is greater than or equal to 70 ⁇ m and less than or equal to 214 ⁇ m, that is, 70 ⁇ m ⁇ L3 ⁇ 214 ⁇ m.
  • L3 can be avoided from being too small (for example, less than 70 ⁇ m), so that the Pd 2+ consumption rate in the reaction area in the activation solution is slower, and the Pd 2+ in the solution
  • the diffusion speed is slow, which can reduce the speed of depositing the palladium layer on the exposed step structure 1101 and slow down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thereby reducing the occurrence of abnormal growth phenomena and even avoiding abnormal growth. Phenomenon.
  • L3 ⁇ 214 ⁇ m it is possible to avoid that L3 is too large (for example, greater than 214 ⁇ m), resulting in an excessive distance between two adjacent conductive pads 131 , and the pad group where the two conductive pads 131 are located is too large.
  • the area occupied by 1300 is too large, which in turn causes the area of the wiring substrate 100 to be too large.
  • the occurrence of gold defects can be reduced by reducing the area of the conductive pad 131 and/or increasing the distance between two adjacent conductive pads 131.
  • other solutions can be used to reduce the occurrence of poor long-term gold.
  • FIG. 10 is a structural diagram of a wiring substrate 100 according to some embodiments.
  • the dotted frame indicated by P is the area covered by the orthographic projection of the first pin P of the functional element 200 on the conductive layer 130 .
  • the dotted frame indicated by N is the area covered by the orthographic projection of the second pin N of the functional element 200 on the conductive layer 130 .
  • the pattern formed by the orthographic projection of the conductive pad 131 on the substrate 120, and the pattern formed by the orthographic projection of the pins of the electronic components connected to the conductive pad 131 on the substrate 120 The shape is roughly the same.
  • the pattern formed by the orthographic projection of the conductive pad 131 on the substrate 120 is defined as the first pattern J
  • the pattern formed by the orthographic projection of the pins of the electronic components on the substrate 120 is defined as is the second graph K.
  • the above-mentioned conductive pad 131 is the first pole pad 131P or the second pole pad 131N in the first pad group 1301, and may also be the power pad Pwr' in the second pad group 1302.
  • the pins of the electronic component may be the first pin P or the second pin N of the functional component 200, or may be the power pin Pwr, the ground pin Gnd, the address pin Di, and the output pin in the driver chip 300. Any of Ot.
  • the second graphic K is located within the first graphic J.
  • both the first graphic J and the second graphic K are rectangles.
  • the first graphic J includes at least one first edge J1. It can be understood that when the first graphic J includes a first edge J1, the first graphic J is circular. In addition, when the first graphic J is a rectangle, the lengths of parts of the first edges J1 of the first graphic J are different. When the first graphic J is a square, the lengths of the plurality of first edges J1 of the first graphic J are the same.
  • the second graphic K includes at least one second edge K2. Among them, a first edge J1 and a second edge K2 are arranged opposite to each other. It can be understood that when the second graphic K includes a first edge J1, the second graphic K is circular. When the second graphic K is a rectangle, part of the second edge K2 of the second graphic K has different lengths. When the second graphic K is a square, the plurality of second edges K2 of the second graphic K have the same length.
  • the difference between the length Lj of the first edge J1 and the length Lk of the second edge K2 is greater than or equal to 2 ⁇ m and less than or equal to 4 ⁇ m, that is, 2 ⁇ m ⁇ Lj-Lk ⁇ 4 ⁇ m.
  • the length Lj of the first edge J1 is greater than the length Lk of the second edge K2.
  • the first edge J1 and the second edge K2 are illustrated below.
  • the pattern formed by the orthographic projection of the first electrode pad 131P on the substrate 120 and the pattern formed by the orthographic projection of the second electrode pad 131N on the substrate 120 the same shape and equal size.
  • the same shape and the same size means that the pattern formed by the orthographic projection of the first electrode pad 131P on the substrate 120 can be aligned with the third electrode pad 131P after being translated by a specified distance on the substrate 120 . Patterns formed by the orthographic projection of the diode pad 131N on the substrate 120 completely overlap.
  • the first graphic J includes two first first edges J11 and two second first edges J12.
  • the length of the first first edge J11 is greater than the length of the second first edge J12. length.
  • the second figure K includes two first second edges K21 and two second second edges K22.
  • the length of the first second edge K21 is greater than the length of the second second edge K22.
  • a first first edge J11 is arranged opposite to a first second edge K21
  • a second first edge J12 is arranged opposite to a second second edge K22.
  • the difference between the length Lj1 of the first first edge J11 and the length Lk1 of the first second edge K21 is greater than or equal to 2 ⁇ m and less than or equal to 4 ⁇ m, that is, 2 ⁇ m ⁇ Lj1 ⁇ Lk1 ⁇ 4 ⁇ m.
  • the length Lj2 of the second first edge J12 is greater than or equal to 2 ⁇ m and less than or equal to 4 ⁇ m than the length Lk2 of the second second edge K22, that is, 2 ⁇ m ⁇ Lj2 ⁇ Lk2 ⁇ 4 ⁇ m.
  • the speed of depositing the palladium layer on the step structure 1101 slows down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180, thereby reducing the occurrence of abnormal growth phenomena, or even avoiding the occurrence of abnormal growth phenomena.
  • the length Lj of the first edge J1 can be avoided by making the difference between the length Lj of the first edge J1 and the length Lk of the second edge K2 in the oppositely arranged first edge J1 and the second edge K2 greater than or equal to 2 ⁇ m.
  • the length is too small, which in turn causes the area of the conductive pad 131 to be too small, and the reliability of the connection between the conductive pad 131 of the first pad group 1301 and the pins of the functional component 200 cannot be guaranteed.
  • the wiring substrate 100 may include two conductive layers 130 or one conductive layer. Based on the embodiment in which the wiring substrate 100 includes one conductive layer 130 , the conductive pads 131 in the wiring substrate 100 will be described below. introduce.
  • FIG. 11 is a structural diagram of a wiring substrate 100 according to some embodiments.
  • Figure 12 is a partial enlarged view of F in Figure 11.
  • the second pad group 1302 is located on the source voltage line 112, wherein the source voltage line 112 passes through the gap between the ground pad Gnd' and the output pad Ot'.
  • ground pad Gnd' and the address pad Di' are respectively disposed opposite to two edges adjacent to the output pad Ot'.
  • the ground pad Gnd' and the address pad Di' are respectively arranged opposite to two adjacent edges of the power pad Pwr'.
  • Figure 13 is a partial enlarged view of G in Figure 2A.
  • the conductive layer 130 includes a plurality of conductive lines 110 , and the area of the conductive lines 110 exposed by the opening 141 is the conductive pad 131 ; in a cross-section perpendicular to the substrate and perpendicular to the extension direction of the conductive lines 110 , you can see the main surface 1102 of the conductive line 110 and the side surface 1103 connected to the main surface 1102, where the main surface 1102 is a surface of the conductive line 110 facing away from the substrate 120; the sandwich between the main surface 1102 and the side surface 1103 Angle H1 is greater than or equal to 105° and less than or equal to 145°.
  • H1 can be prevented from being too small (for example, less than 105°), so that H1 can be made smaller, and thus The probability of generating the step structure 1101 is smaller, so that the edge of the conductive line 110 is less likely to be exposed, thereby reducing the phenomenon of abnormal growth.
  • H2 refers to the side surface
  • the acute angle between 1103 and substrate 120 Therefore, the larger H2 is, the smaller H1 is, and the smaller the angle H2 between the side surface 1103 and the substrate 120 is, the better the protective layer 140 covers the side surface 1103 and the less likely the conductive line 110 is to be exposed.
  • the angle H1 between the side surface 1103 and the substrate 120 can be made less than or equal to 75°.
  • the angle H1 between the main surface 1102 and the side surface 1103 less than or equal to 145°, it is possible to avoid H1 being too large (for example, greater than 145°), resulting in greater process difficulty.
  • the angle H1 between the main surface 1102 and the side surface 1103 is greater than or equal to 115° and less than or equal to 140°.
  • At least two side surfaces 1103 of the plurality of side surfaces 1103 that are shorter than the conductive pads 131 of the conductive lines 110 are the first side surfaces 1103A; the two first side surfaces 1103A are connected by curved surfaces.
  • one conductive pad 131 has two first side surfaces 1103A that are relatively close to the conductive pad 131 .
  • the distance between the two first side surfaces 1103A and the edge of the conductive pad 131 is smaller than the distance between the other side surfaces 1103 and the edge of the conductive pad 131 . It should be noted that the distance between the two first side surfaces 1103A and the edge of the conductive pad 131 may be equal or unequal.
  • a first side surface 1103A of the conductive line 110 where the first electrode pad 131P is located and a first side surface 1103A of the conductive line 110 where the second electrode pad 131N is located are both located on the first electrode. between the bonding pad 131P and the second electrode pad 131N.
  • the side surfaces 1103 connected to both ends of the first side surface 1103A between the first electrode pad 131P and the second electrode pad 131N are both the first side surfaces 1103A.
  • the two first side surfaces 1103A of the conductive line 110 where the power pad Pwr' is located are respectively between the power pad Pwr' and the output pad Ot', and between the power pad Pwr' and the address pad Di'. between.
  • the two first side surfaces 1103A of the conductive line 110 where the output pad Ot' is located are respectively located between the output pad Ot' and the power pad Pwr', and between the output pad Ot' and the ground pad Gnd'.
  • the two first side surfaces 1103A of the conductive line 110 where the ground pad Gnd' is located are respectively located between the ground pad Gnd' and the output pad Ot', and between the ground pad Gnd' and the address pad Di'.
  • the two first side surfaces 1103A of the conductive line 110 where the address pad Di' is located are respectively located between the address pad Di' and the ground pad Gnd', and between the address pad Di' and the power pad Pwr'.
  • the two first side surfaces 1103A of the conductive line 110 where the output pad Ot' is located are respectively located Between the output pad Ot' and the ground pad Gnd', and between the output pad Ot' and the address pad Di'.
  • the two first side surfaces 1103A of the conductive line 110 where the address pad Di' is located are respectively located between the address pad Di' and the output pad Ot', and between the address pad Di' and the power pad Pwr'.
  • the two first side surfaces 1103A of the ground pad Gnd' are respectively located between the ground pad Gnd' and the power pad Pwr', and between the ground pad Gnd' and the output pad Ot'.
  • the two first side surfaces 1103A are connected through a curved surface, that is, the orthographic projection of the intersection of the two first side surfaces 1103A on the substrate 120 is the first rounded corner 1104, which can reduce the sharp edges of the conductive lines 110 and reduce the sharp edges of the conductive lines 110.
  • the two first side surfaces 1103A are connected through a curved surface, which can reduce static electricity accumulation in the conductive line 110 .
  • the radius R of the first fillet 1104 is greater than or equal to 20 ⁇ m and less than or equal to 30 ⁇ m.
  • the radius R of the first fillet 1104 is made greater than or equal to 20 ⁇ m, it is possible to avoid the situation where the radius R of the first fillet 1104 is too small (for example, less than 20 ⁇ m) and thereby cannot effectively prevent static electricity accumulation. appears, so that the conductive line 110 can have a better anti-static accumulation effect.
  • the radius R of the first fillet 1104 can be avoided from being too large (for example, greater than 30 ⁇ m), and thus the conductive pad can be avoided The distance between the edge of 131 and the edge of the first fillet 1104 is too small.
  • the backplane 1000 provided in some embodiments of the present disclosure includes the wiring substrate 100 provided in some of the above embodiments. Therefore, the backplane 1000 provided in some embodiments of the present disclosure includes the wiring substrate provided in some of the above embodiments. All the beneficial effects of 100 will not be repeated here.
  • Figure 14 is a structural diagram of a display device 2000 according to some embodiments.
  • the display device 2000 includes: a backlight module 500 and a liquid crystal display panel 600.
  • the backlight module 500 is the backlight module 500 provided in some of the above embodiments.
  • Board 1000, functional elements 200 include light emitting diodes.
  • the liquid crystal display panel 600 is located on the light emitting side of the backlight module 500 .
  • the display device 2000 provided by some embodiments of the present disclosure has all the beneficial effects of the backplane 1000 provided by some of the above embodiments, which will not be described again here.
  • the display device 2000 can display dynamic image information, such as videos or game screens, and can also display static image information, such as images or photos.
  • the main structure of the liquid crystal display panel 600 includes an array substrate 61 , an alignment substrate 62 , and a liquid crystal layer 63 disposed between the array substrate 61 and the alignment substrate 62 .
  • Each sub-pixel of the array substrate 61 includes a thin film transistor 611 and a pixel electrode 612 located on the first substrate 610 .
  • the thin film transistor 611 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulation layer. The source electrode and the drain electrode are respectively in contact with the active layer.
  • the pixel electrode 612 is electrically connected to the drain electrode of the thin film transistor 611.
  • the array substrate 61 further includes a common electrode 613 disposed on the first substrate 610 .
  • the pixel electrode 612 and the common electrode 613 may be disposed on the same layer.
  • both the pixel electrode 612 and the common electrode 613 have a comb-tooth structure including a plurality of strip-shaped sub-electrodes.
  • the pixel electrode 612 and the common electrode 613 may also be provided in different layers.
  • a first interlayer insulating layer 614 is provided between the pixel electrode 612 and the common electrode 613.
  • a second interlayer insulating layer 615 is also provided between the common electrode 613 and the thin film transistor 611.
  • the array substrate 61 does not include the common electrode 613.
  • the common electrode 613 may be located in the counter-cell substrate 62.
  • the array substrate 61 further includes a flat layer 616 disposed on the side of the thin film transistor 611 and the pixel electrode 312 away from the first substrate 610 .
  • the box-aligning substrate 62 includes a color filter layer 621 disposed on the second substrate 620 .
  • the box-aligning substrate 62 may also be called a color filter substrate (Color Filter, CF for short).
  • the color filter layer 621 at least includes a red photoresist unit, a green photoresist unit and a blue photoresist unit.
  • the red photoresist unit, the green photoresist unit and the blue photoresist unit are respectively aligned with the sub-pixels on the array substrate 61. right.
  • the cell substrate 62 also includes a black matrix pattern 622 disposed on the second substrate 620. The black matrix pattern 622 is used to separate the red photoresist unit, the green photoresist unit and the blue photoresist unit.
  • the light can be emitted through the light exit side of the backlight module 500 and illuminated to the liquid crystal layer 63 .
  • the intensity of light passing through the liquid crystal layer 63 can be adjusted, thereby adjusting the intensity of light irradiated to the cell substrate 62.
  • the box substrate 62 includes a color filter layer 621. In this way, by adjusting the intensity of light irradiated to the photoresist units of different colors, the display device 2000 can realize the display function of color images.
  • the liquid crystal display panel 600 further includes an upper polarizer 64 disposed on the side of the cell alignment substrate 62 away from the liquid crystal layer 63 and a lower polarizer 65 disposed on the side of the array substrate 61 away from the liquid crystal layer 63 .
  • Figure 15 is a structural diagram of a display device 3000 according to some embodiments.
  • some embodiments of the present disclosure also provide a display device 3000.
  • the display device 3000 includes: a display panel 700.
  • the display panel 700 includes the backplane 1000 provided in some of the above embodiments.
  • the display device 3000 provided by some embodiments of the present disclosure has all the beneficial effects of the backplane 1000 provided by some of the above embodiments, which will not be described again here.
  • the display device 3000 can display dynamic image information, such as videos or game screens, and can also display static image information, such as images or photos.
  • the display device 3000 may be an LED display, a Mini LED display, a Micro LED display, or the like. It can be understood that the plurality of LED chips in the backplane 1000 are used to emit red light, green light and blue light, so that the display device 3000 can achieve color display.
  • Figure 16 is a flow chart of a method of manufacturing a wiring substrate according to some embodiments.
  • some embodiments of the present disclosure also provide a method for preparing a wiring substrate, which is used to form the wiring substrate 100 provided in some of the above embodiments.
  • the preparation method of the wiring substrate includes the following steps S1 to S2.
  • a conductive layer 130 is formed on the substrate 120 , where the conductive layer 130 includes a plurality of pad groups 1300 , and one pad group 1300 includes a plurality of conductive pads 131 .
  • a protective layer 140 is formed on the side of the conductive layer 130 away from the substrate 120, and an opening 141 is formed on the protective layer 140.
  • the portion of the conductive layer 130 exposed to the opening 141 is conductive welding.
  • the maximum dimension L1 of the pad 131 and the conductive pad 131 in the direction parallel to the substrate 120 is less than or equal to 30 times the minimum distance L2 between the edge of the conductive pad 131 and the edge of the conductive layer 130 .
  • the maximum dimension L1 of the conductive pad 131 in the direction parallel to the substrate 120 is smaller, so that the Pd 2+ consumption rate in the reaction area in the activation solution is smaller, and the Pd 2+ consumption rate in the solution is smaller.
  • the diffusion speed of Pd 2+ is small, which in turn can reduce the speed of depositing the palladium layer on the exposed step structure 1101 and slow down the speed of subsequent catalytic growth of the oxidation protective layer 170 and the conductive functional layer 180 , thereby reducing the occurrence of abnormal growth phenomena and even avoiding them. Abnormal growth occurs.
  • Figure 17 is a flow chart of a method of manufacturing a wiring substrate according to some embodiments.
  • 18 to 22 are step diagrams of a method of manufacturing a wiring substrate according to some embodiments.
  • the step of forming the conductive layer 130 on the substrate 120 in S1 includes the following steps S11 to S15.
  • a conductive material is deposited on the substrate 120 to form an initial conductive layer 130'.
  • step S11 a deposition process may be used to form the initial conductive layer 130'.
  • a buffer layer 150 may also be formed on one side of the substrate 120, and the initial conductive layer 130' is formed on a side of the buffer layer 150 away from the substrate 120.
  • a photoresist layer 190 is formed on the side of the initial conductive layer 130' away from the substrate 120.
  • the photoresist layer 190 is exposed and developed to pattern the photoresist layer 190 .
  • the initial conductive layer 130' is etched based on the patterned photoresist layer 190 to form the conductive layer 130.
  • photoresist layer 190 includes positive photoresist. Please refer to Figure 20.
  • step S14 after the photoresist layer 190 is exposed, the photoresist layer 190 (see Figure 19) exposed to light is removed, thereby patterning the photoresist layer 190 to form Multiple glue lines 190'.
  • the cross-section of the glue line 190' is a trapezoid, that is, the line width of the glue line 190' gradually decreases along the first direction I1.
  • the direction pointed by the arrow I1 is the first direction.
  • the direction pointed by arrow I2 is the direction of the line width of the glue line 190'.
  • the direction in which the substrate 120 points to the initial conductive layer 130' is the first direction I1.
  • the conductive layer 130 formed in step S15 includes a plurality of conductive lines 110, and the conductive lines 110 have a right trapezoidal cross-section.
  • step S13 the greater the specified temperature, the greater the fluidity of the photoresist layer 190.
  • the bottom surface 1902 of the glue line 190' refers to a surface of the glue line 190' facing the substrate 120.
  • the side 1901 is connected to the bottom 1902.
  • step S15 the initial conductive layer 130' will be etched along the side surface 1901 of the glue line 190'. Therefore, please refer to FIG. 21, the side surface 1103 of the conductive line 110 formed in step S15 and the substrate 120 The angles H2 and H3 are approximately equal.
  • the specified temperature is greater than or equal to 125°C and less than or equal to 135°C, which can avoid the specified temperature being too high (for example, greater than 135°C), thereby making the fluidity of the photoresist layer 190 relatively high. Therefore, after exposure and development, the angle H3 between the side surface 1901 and the bottom surface 1902 of the glue line 190' is smaller, so that the angle H2 between the side surface 1103 of the conductive line 110 and the substrate 120 is smaller, so that the This allows the protective layer 140 to better cover the conductive wires 110. Therefore, the conductive wires 110 are not easily exposed, and abnormal growth can be reduced.
  • the specified temperature is too small (for example, less than 125° C.), which results in excessive fluidity of the photoresist layer 190 and greater process difficulty.
  • the specified temperature is equal to 130°C.
  • the angle H1 between the main surface 1102 and the side surface 1103 of the conductive line 110 formed in step S15 is greater than or equal to 105° and less than or equal to 145°.
  • the greater the thickness of the photoresist layer 190 the greater the angle H2 between the side surface 1103 and the substrate 120.
  • H2 is approximately 70°
  • H2 is approximately 55°
  • H2 is approximately 40°.
  • step S15 step S16 of removing the photoresist layer 190 is also included.
  • step S2 can be executed.
  • the protective layer 140 in the step of forming the protective layer 140 on the side of the conductive layer 130 away from the substrate 120, is formed through a chemical vapor deposition (English full name: Chemical Vapor Deposition, abbreviation: CVD) process.
  • CVD Chemical Vapor Deposition
  • the protective layer 140 formed by the chemical vapor deposition process has a high density. Therefore, the coverage of the conductive layer 130 by the protective layer 140 can be improved, thereby reducing the exposure of the conductive layer 130, thereby reducing abnormal growth phenomena.
  • the protective layer 140 can also be formed through a physical vapor deposition process (English full name: Physical Vapor Deposition, abbreviation: PVD).

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Abstract

一种布线基板（100），布线基板（100）包括衬底（120）、导电层（130）和保护层（140）。导电层（130）位于衬底（120）的一侧，导电层（130）中包括多个焊盘组（1300），一个焊盘组（1300）包括多个导电焊盘（131）。保护层（140）位于导电层（130）远离衬底（120）的一侧，保护层（140）中包括多个开口（141）；导电层（130）暴露于开口（141）的部分为导电焊盘（131）。其中，导电焊盘（131）在平行于衬底（120）的方向上的最大尺寸，小于或等于导电焊盘（131）的边缘到导电层（130）的边缘之间的最小距离的30倍。

Description

布线基板及制备方法、背板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种布线基板及制备方法、背板、显示装置。
背景技术
Mini LED(Mini Organic Light-Emitting Diode，迷你发光二极管)/Micro LED(Micro Organic Light-Emitting Diode，微型发光二极管)显示装置具有亮度高、显示画面清晰和功耗低等优点，应用前景较好。
发明内容
一方面，提供一种布线基板。所述布线基板包括衬底、导电层和保护层。所述导电层位于所述衬底的一侧，所述导电层中包括多个焊盘组，一个焊盘组包括多个导电焊盘。所述保护层位于所述导电层远离所述衬底的一侧，所述保护层中包括多个开口；所述导电层暴露于所述开口的部分为所述导电焊盘。其中，所述导电焊盘在平行于所述衬底的方向上的最大尺寸，大于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的1.5倍，且小于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
在一些实施例中，所述导电焊盘在平行于所述衬底的方向上的最大尺寸，为该导电焊盘与相邻的导电焊盘之间的距离的0.5～5倍。
在一些实施例中，所述导电焊盘在平行于所述衬底的方向上的最大尺寸大于或等于105μm，且小于或等于350μm。
在一些实施例中，所述导电焊盘的面积大于或等于5000μm 2，且小于或等于55000μm 2。
在一些实施例中，在同一个所述焊盘组中，相邻的两个导电焊盘之间的距离，大于或等于70μm，且小于或等于214μm。
在一些实施例中，所述导电层中包括多条导电线，导电线暴露于所述开口的部分为所述导电焊盘；所述导电线包括主表面以及与所述主表面相连的侧表面，其中，所述主表面为所述导电线背离所述衬底的一个表面；所述主表面与所述侧表面之间的夹角大于或等于105°，且小于或等于145°。
在一些实施例中，所述导电层中包括多条导电线，导电线暴露于所述开口的部分为所述导电焊盘；所述导电线包括主表面以及与所述主表面相连的多个侧表面，其中，所述主表面为所述导电线背离所述衬底的一个表面；所述多个侧表面中与所述导电线的导电焊盘距离较短的至少两个侧表面为第一 侧表面；两个所述第一侧表面之间通过曲面连接。
在一些实施例中，所述曲面在所述衬底上的正投影为第一圆角，所述第一圆角的半径大于或等于20μm，且小于或等于30μm。
在一些实施例中，所述布线基板包括多个器件区。所述多个焊盘组包括位于任一个器件区中的多个第一焊盘组和一个第二焊盘组；其中，所述第一焊盘组包括间隔设置的第一极焊盘和第二极焊盘；所述第二焊盘组至少包括间隔设置的电源焊盘、接地焊盘、地址焊盘和输出焊盘；所述布线基板还包括源电压线和驱动电压线。在同一个所述器件区内：所述电源焊盘电连接于所述源电压线；所述地址焊盘与另一个所述器件区内的输出焊盘电连接；所述多个第一焊盘组中，第一个第一焊盘组中的第一极焊盘与所述驱动电压线电连接，上一个第一焊盘组中的第二极焊盘与下一个第一焊盘组中的第一极焊盘电连接，最后一个第一焊盘组的第二极焊盘与所述输出焊盘电连接。其中，至少第一个第一焊盘组中的第一极焊盘、所述电源焊盘和所述接地焊盘中的至少一个，在平行于所述衬底的方向上的最大尺寸，小于或等于该焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
在一些实施例中，所述布线基板包括多个器件区和一个控制区。所述多个焊盘组包括位于任一个器件区中的多个第一焊盘组，所述第一焊盘组包括间隔设置的第一极焊盘和第二极焊盘。所述多个焊盘组还包括位于所述控制区内的第二焊盘组；所述第二焊盘组包括电源焊盘、接地焊盘、地址焊盘和输出焊盘。所述布线基板还包括源电压线和驱动电压线；所述电源焊盘电连接于所述源电压线。在同一个所述器件区内：所述多个第一焊盘组中，第一个第一焊盘组中的第一极焊盘与所述驱动电压线电连接，上一个第一焊盘组中的第二极焊盘与下一个第一焊盘组中的第一极焊盘电连接，最后一个第一焊盘组的第二极焊盘与所述输出焊盘电连接。其中，至少第一个第一焊盘组中的第一极焊盘，在平行于所述衬底的方向上的最大尺寸，小于或等于该第一极焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
在一些实施例中，所述导电层的数量为两个。第一个所述导电层位于所述衬底的一侧，部分所述导电线位于所述第一个所述导电层中；第二个所述导电层位于所述第一所述导电层远离所述衬底的一侧，另一部分所述导电线位于第二个所述导电层中。其中，第一个所述导电层中的一条导电线与位于第二个所述导电层中的至少一条导电线通过过孔连接，位于第二个所述导电层中的导电线暴露于所述开口的部分为所述导电焊盘。
在一些实施例中，所述布线基板还包括：氧化防护层和导电功能层。其 中，所述氧化防护层覆盖于所述导电焊盘远离所述衬底的一侧。所述导电功能层覆盖于所述氧化防护部远离所述衬底的一侧。
另一方面，提供一种背板。所述背板包括：多个功能元件、至少一个驱动芯片和如上述任一实施例所述的布线基板。所述布线基板中的多个焊盘组包括第一焊盘组和第二焊盘组；所述第一焊盘组与所述功能元件连接，所述第二焊盘组与所述驱动芯片连接。
又一方面，提供一种显示装置。所述显示装置包括：背光模组和液晶显示面板。其中，所述背光模组为如上一些实施例所提供的背板，所述功能元件包括发光二极管。所述液晶显示面板位于所述背光模组的出光侧。
又一方面，提供一种显示装置。所述显示装置包括：显示面板，所述显示面板包括以上一些实施例所提供的背板。
又一方面，提供一种布线基板的制备方法。所述布线基板的制备方法包括：在衬底上形成导电层，其中，所述导电层中包括多个焊盘组，一个焊盘组包括多个导电焊盘。在所述导电层远离所述衬底的一侧形成保护层，并在所述保护层上形成开口，其中，所述导电层暴露于所述开口的部分为所述导电焊盘；所述导电焊盘在平行于所述衬底的方向上的最大尺寸，小于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
在一些实施例中，在所述在衬底上形成导电层的步骤，包括：在所述衬底上沉积导电材料，以形成初始导电层。在所述初始导电层远离所述衬底的一侧形成光刻胶层。在指定温度下，烘烤所述光刻胶层，其中，所述指定温度大于或等于125℃，且小于或等于135℃。对所述光刻胶层进行曝光显影，以使得所述光刻胶层图案化。基于图案化的光刻胶层对所述初始导电层进行刻蚀，以形成所述导电层。
在一些实施例中，所述在所述导电层远离所述衬底的一侧形成保护层的步骤中，通过化学气相淀积工艺形成所述保护层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为根据一些实施例的背板的结构图；
图1B为根据一些实施例的驱动芯片的结构图；
图1C为根据一些实施例的背板的结构图；
图1D为根据一些实施例的功能元件的结构图；
图2A为根据一些实施例的布线基板的截面图；
图2B为根据一些实施例的布线基板的截面图；
图2C为根据一些实施例的布线基板的截面图；
图2D为根据一些实施例的背板的结构图；
图3为根据一些实施例的布线基板的结构图；
图4A为根据一些实施例的布线基板的截面图；
图4B为根据一些实施例的布线基板的截面图；
图4C为根据一些实施例的活化反应的原理图；
图5为根据一些实施例的布线基板的结构图；
图6为根据一些实施例的布线基板的结构图；
图7为根据一些实施例的布线基板的结构图；
图8为根据一些实施例的布线基板的结构图；
图9A为图7中D处的局部放大图；
图9B为图7中E处的局部放大图；
图10为根据一些实施例的布线基板的结构图；
图11为根据一些实施例的布线基板的结构图；
图12为图11中F处的局部放大图；
图13为图2A中G处的局部放大图；
图14为根据一些实施例的显示装置的结构图；
图15为根据一些实施例的显示装置的结构图；
图16为根据一些实施例的布线基板的制备方法的流程图；
图17为根据一些实施例的布线基板的制备方法的流程图；
图18为根据一些实施例的布线基板的制备方法的步骤图；
图19为根据一些实施例的布线基板的制备方法的步骤图；
图20为根据一些实施例的布线基板的制备方法的步骤图；
图21为根据一些实施例的布线基板的制备方法的步骤图；
图22为根据一些实施例的布线基板的制备方法的步骤图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一些实施例(some embodiments)”、、“示例(example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“大致”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内， 其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
图1A为根据一些实施例的背板1000的结构图。
请参阅图1A，本公开的一些实施例提供了一种背板1000，该背板1000包括布线基板100、多个功能元件200以及至少一个驱动芯片300。其中，多个功能元件200以及至少一个驱动芯片300均与布线基板100电连接，且布线基板100中设置有多条导电线110，多个功能元件200之间，以及功能元件200与驱动芯片300均可以通过导电线110电连接。
其中，需要说明的是，除了功能元件200和驱动芯片300，背板1000还可以包括其他的电子元件(图中未示出)，例如传感器芯片、电容、电阻、电感等。
请参阅图1A，在一些示例中，布线基板100中的多条导电线110包括源地址线111、源电压线112、驱动电压线113和公共电压线114。
图1B为根据一些实施例的驱动芯片300的结构图。
请参阅图1B，在一些示例中，驱动芯片300包括电源引脚Pwr、接地引脚Gnd、地址引脚Di和输出引脚Ot。
请再次参阅图1A，源地址线111与驱动芯片300的地址引脚Di连接。源地址线111被配置为传输第一输入信号，第一输入信号包括地址信号，以选通相应地址的驱动芯片300。例如，不同的驱动芯片300的地址可以相同或不同。第一输入信号可以为位宽为8bit包括地址信息的数字信号，通过解析 该第一输入信号可以获知待传输的地址。
源电压线112与驱动芯片300的电源引脚Pwr连接。源电压线112被配为传输第二输入信号，第二输入信号包括电源信号和/或载波通信信号，以向驱动芯片300提供电能和/或传输通信数据。例如，第二输入信号为电源信号和载波通信信号，第二输入信号不仅为驱动芯片300提供电能，还向驱动芯片300传输通信数据，该通信数据可用于控制相应的功能元件200的工作状态。
驱动电压线113与驱动芯片300的输出引脚Ot连接。多个功能元件200设置于驱动电压线113与驱动芯片300的输出引脚Ot连接的电路上。其中，驱动电压线113被配置为传输驱动电压，为功能元件200提供工作电压。驱动芯片300的输出引脚Ot可以提供驱动信号和/或中继信号，例如，驱动信号用于控制功能元件200的工作状态，中继信号用于给其他驱动芯片300提供第一输入信号。
公共电压线114与驱动芯片300的接地引脚Gnd连接。公共电压线114被配置为接收并传输公共电压信号，公共电压信号包括接地信号。
请参阅图1A，在一些示例中，背板1000包括多个器件区AA，其中，器件区AA包括一个控制区A2和与该控制区A2连接的至少一个子器件区A1。功能元件设置在子器件区A1，驱动芯片300设置在控制区A2，一个器件区AA中设置有多个功能元件200和一个驱动芯片300，其中，一个驱动芯片300用于控制一个多个功能元件200的工作状态。
图1C为根据一些实施例的另一种背板1000的结构图。
请参阅图1C，在一些示例中，背板1000中的多个器件区AA呈多行多列设置。在列方向X上相邻的两个器件区AA中，其中，一个器件区AA中驱动芯片300的地址引脚Di与另一个器件区AA中驱动芯片300的输出引脚Ot电连接。请参阅图1C，箭头X所指的方向为列方向X。
在一些示例中，一个器件区AA中设置有多个功能支路，其中，每个功能支路中包括多个串联的功能元件200，而多个功能支路并联设置。在另一些示例中，一个器件区AA中设置有一个功能支路，即此时一个器件区AA中的所有功能元件200串联设置。示例性的，一个功能支路中功能元件200的数量可以为4个、6个或9个等，还可以更多，在此不进行具体的限定。其中，一个器件区AA中串联设置的多个功能元件200，或者一个功能支路中串联设置的多个功能元件200电连接于驱动电压线113和输出引脚Ot之间。
在其他的一些示例中，一个器件区AA中可以设置有多个相互并联的功 能支路，而每个功能支路中至少包括一个功能元件200，当功能支路中包括多个功能元件200时，属于同一功能支路中的功能元件200之间串联连接，对各个功能支路中功能元件的数量不做限制；每个功能支路的两端分别电连接于驱动电压线113和输出引脚Ot。
图1D为根据一些实施例的功能元件200的仰视平面结构图。
请参阅图1D，在一些示例中，功能元件200具有两个引脚，分别为第一引脚P和第二引脚N。
请再次参阅图1C，在一个功能支路中，第一个功能元件200A的第一引脚P与驱动电压线113电连接，上一个功能元件200中的第二引脚N与下一个功能元件200中的第一引脚P电连接，最后一个功能元件200的第二引脚N与输出引脚Ot电连接。其中，上一个功能元件200与下一个功能元件200为相邻的两个功能元件200，并且上一个功能元件200与驱动电压线113之间的导电线110的长度大于下一个功能元件200与驱动电压线113之间的导电线110的长度。
示例性的，请参阅图1C，在同一个器件区AA内包括9个功能元件200，9个功能元件200依次为第一个功能元件200A……第八个功能元件200H和第九个功能元件200I。
可以理解的是，在第八个功能元件200H和第九个功能元件200I中，第八个功能元件200H是上一个功能元件200，而第九个功能元件200I是下一个功能元件200。其中，第八个功能元件200H的第二引脚N与第九个功能元件200I的第一引脚P电连接，而九个功能元件200I的第二引脚N与驱动芯片300的输出引脚Ot电连接。
下面对布线基板100进行介绍。
图2A为根据一些实施例的布线基板100的截面图。
请参阅图2A，本公开的一些实施例提供了一种布线基板100，该布线基板100中包括衬底120、导电层130和保护层140。其中，导电层130位于衬底120的一侧，保护层140位于导电层130远离衬底120的一侧。其中，保护层140中包括多个开口141，而导电层130暴露于开口141的部分为导电焊盘131。
示例性的，衬底120为柔性衬底，即可使得布线基板100以及背板1000实现弯曲。当然，衬底120也可以为硬性衬底。示例性的，衬底120的材料可以包括塑料、FR-4等级材料、树脂、玻璃、石英、聚酰亚胺或者聚甲基丙烯酸甲酯(英文全称：Polymethyl Methacrylate，英文简称PMMA)中的任一 个。
示例性的，保护层140可以为绝缘材料，例如氧化硅、氮化硅、氮氧化硅等。其中，保护层140可以对导电层130进行保护。
示例性的，一个导电层130可以包括多层材料层。例如导电层130包括铜(Cu)层和两个钼铌(MoNb)层，其中，两个钼铌层分别设置于铜层相背的两个表面。可以理解的是，铜层的一个表面朝向衬底120，另一个表面背离衬底120。此外，导电层130也可以仅由铜制成。
其中，导电层130中包括多条导电线110，而导电线110暴露于开口141的部分为导电焊盘131。其中，需要说明的是，可以通过刻蚀保护层形成开口141；在一些情况下，需要对导电层130被开口141暴露出的区域的表层为钼铌层的情况下，需要进一步对钼铌层进行刻蚀，使得铜层暴露，确保后续导电焊盘131的可焊接性。
请参阅图2A，在一些实施例中，布线基板包括两个导电层130。第一个导电层130A位于衬底120的一侧，部分导电线110位于第一个导电层130A中。其中，为了方便叙述，可以将位于第一个导电层130A中的导电线110称为信号线。示例性的，位于第一个导电层130A中的信号线包括上述源地址线111、源电压线112、驱动电压线113和公共电压线114。
第二个导电层130B位于第一个导电层130A远离衬底120的一侧，另一部分导电线110位于第二个导电层130B中。其中，为了方便叙述，将位于第二个导电层130B中的另一部分导电线110定义为转接线115。
其中，第一个导电层130A中的一条导电线110与位于第二个导电层130B中的至少一条导电线110通过过孔连接。示例性的，源地址线111、源电压线112、驱动电压线113和公共电压线114中的每一条信号线与至少一条转接线115通过过孔连接。
位于第二个导电层130B中的导电线110暴露于开口141的部分为导电焊盘131，即转接线115暴露于开口141的部分为导电焊盘131。
除了上述的导电层130和保护层140外，布线基板100中还包括其他膜层。下面基于布线基板100中包括两个导电层130的实施例，对布线基板100中的其他膜层进行介绍。
请参阅图2A，在一些示例中，衬底120的一侧设置有缓冲层(英文名称：Buffer)150，缓冲层150位于衬底120和第一个导电层130A之间。
第一个导电层130A远离衬底120的一侧形成有绝缘层160，绝缘层160位于第二个导电层130B与第一个导电层130A之间。示例性的，绝缘层160 包括依次设置于第一个导电层130A上的第一钝化层PVX1、第一树脂层OC1和第二钝化层PVX2。
其中，绝缘层160中形成有过孔，第二个导电层130B可以通过绝缘层160中的过孔与第一个导电层130A连接。
示例性的，第一钝化层PVX1可以由无机绝缘材料形成，例如SiN。
示例性的，第一钝化层PVX1、第二钝化层PVX2和保护层140的材料相同。
示例性的，第一树脂层OC1可以由树脂材料形成。
在上述一些实施例中，对布线基板100中包括两个导电层130的实施例进行了介绍，而在其他的一些实施例中，布线基板100中可以包括一个导电层130。
图2B为根据其他的一些实施例的布线基板100的截面图。
请参阅图2B，布线基板100包括依次层叠设置于衬底120之上的缓冲层150、导电层130和保护层140。其中，保护层140包括第三钝化层PVX3和第二树脂层OC2。
请参阅图2B，在一些示例中，导电层130可以为双层结构，此时，导电层130可以包括两个子导电层130C，两个子导电层130C可以在两次工艺形成，以此避免一道工艺所形成的导电层130过厚。
图2C为根据其他的一些实施例的布线基板100的截面图。
请参阅图2C，在另一些示例中，在布线基板100中还包括一个导电层130的情况下，导电层130还可以为单层结构。
此外，还需要说明的是，请再次参阅图2A，在布线基板100中过包括两个导电层130的情况下，导电层130也可以为单层结构。或者第一个导电层130A和/或第二个导电层130B包括两个子导电层130C。
请参阅图2A和图2B，导电层130中包括多个焊盘组1300，一个焊盘组1300包括多个导电焊盘131。其中，多个导电焊盘131间隔设置。
其中，一个焊盘组1300可以与一个电子元件电连接，其中，多个焊盘组1300可以分为多种，每种焊盘组1300与一种电子元件电连接，不同种焊盘组1300与不同种电子元件电连接。其中，每种焊盘组1300的数量可以为一个或多个。
示例性的，电子元件可以包括上述的功能元件200和驱动芯片300。具体的，功能元件可以为无机发光二极管，无机发光二极管的发光面积不超过300000μm 2，具体的，可以不超过40000μm 2；驱动芯片300其在衬底120上 的正投影面积不大于300000μm 2。图2D为根据一些实施例的背板1000的结构图。
请参阅图2D，背板1000还可以包括其他种类元件，例如电路板400。电路板400位于布线基板100的一侧。
布线基板100包括功能区BB和绑定区CC，其中，需要说明的是，在图2D中，BB和CC所指示的虚线框仅是为了示意功能区BB和绑定区CC的位置，并不对功能区BB和绑定区CC做进一步的限定。
上述多个器件区AA(如图1C所示)位于功能区BB中，因此，多个焊盘组1300(如图2A和2B所示)位于功能区BB中。
如图2A和2B所示，多个导电焊盘131中还包括电路板焊盘1310，电路板焊盘1310位于绑定区CC，电路板焊盘1310可以与电路板400的引脚绑定。
示例性的，功能元件200、驱动芯片300以及电路板400等电子元件可以通过表面组装技术(或称表面贴装技术，英文全称：Surface Mounted Technology，英文简称SMT)与导电焊盘131之间固定连接。示例性的，功能元件200的引脚以及驱动芯片300的引脚与导电焊盘131之间通过焊接工艺连接。
示例性的，使用锡基焊料焊接对功能元件200的引脚以及驱动芯片300的引脚进行焊接。在经过回流焊工艺后，锡基焊料与焊盘处的Cu层容易形成Cu 6Sn 5等金属间化合物(IMC层)。IMC层是焊盘与器件形成良好连接的标志，但IMC是脆性物质，其厚度过大将严重降低焊接处的可靠性，为防止焊接处产生过厚的IMC层，通过引入化镍金工艺作为焊盘结构中的阻挡层以阻止Cu-Sn化合物的快速生成。
请参阅图2A，在一些实施例中，布线基板100中的阻挡层还包括氧化防护层170和导电功能层180，其中，氧化防护层170覆盖于导电焊盘131远离衬底120的一侧，而导电功能层180覆盖于氧化防护层170远离衬底120的一侧。
通过在导电焊盘131远离衬底120的一侧设置氧化防护层170，从而能够对导电焊盘131起到保护的作用，减小导电焊盘131的氧化程度。在氧化防护层170远离导电焊盘131的一侧设置导电功能层180，从而能够对氧化防护层170起到保护的作用，也即是能够对导电焊盘131起到进一步的保护作用，减小导电焊盘131以及氧化防护层170的氧化程度，从而降低功能元件200、驱动芯片300与布线基板100之间的焊接难度，进一步提高功能元件200、驱动芯片300与布线基板100之间的连接可靠性。
示例性的，氧化防护层170的材料包括镍(Ni)。其中，镍为导电材料。镍能够与焊料中的材料(例如锡)发生化学反应，提高焊料在焊接时的浸润性，从而提高功能元件200、驱动芯片300与导电焊盘131之间的焊接牢固性，进一步提高功能元件200、驱动芯片300与布线基板100之间的连接可靠性。
示例性的，导电功能层180包括导电材料，例如：金(Au)。
下面基于氧化防护层170的材料包括镍、导电功能层180的材料包括金，对本公开一些实施例中的氧化防护层170和导电功能层180的形成过程进行介绍。
在一些示例中，可以采用化学镍金工艺形成氧化防护层170和导电功能层180。
在化学镍金工艺中，首先对布线基板100进行酸洗，然后将布线基板100置于包含Pd 2+的活化溶液中，此时，导电焊盘131中的Cu与活化溶液中的Pd 2+发生置换反应，生成了Cu 2+和Pd(钯)，其中Pd附着在Cu层背离衬底120的表面，形成钯层。而后将布线基板100置于主要成分是硫酸镍、次磷酸钠(还原剂，使镍离子还原为金属镍)、络合剂的溶液中，在焊盘的表面会生成一层磷镍合金层(也即是氧化防护层170)，由于磷镍合金层仍然易氧化，焊料与发生氧化的磷镍合金层焊接困难且不可靠，因此最后还需要将布线基板100浸入含有金离子溶液中，在磷镍合金层表面形成浸金层(也即是导电功能层180)，浸金层中的金颗粒可填塞化镍金层中的空隙，以降低磷镍合金层的氧化概率，从而以减弱导电焊盘131的氧化程度。之后，电子元件通过焊料经过回流焊工艺，焊接在表面具有化镍金层(包括上述氧化防护层170和导电功能层180)的导电焊盘131上。
图3为根据一些实施例的布线基板100的结构图。
请参阅图3，在化学镍金工艺后，不仅导电焊盘131处形成了氧化防护层170(如图2A所示)和导电功能层180(如图2A所示)，在导电焊盘131附近的导电线110的边缘还形成了氧化防护层170和导电功能层180，在本公开中的实施例，为了便于叙述，将导电线110的边缘处的形成了氧化防护层170和导电功能层180的现象称为异常生长现象。而将氧化防护层170和/或导电功能层180形成于导电线110的边缘处的区域称为异常区。如图3所示，虚线框所框出来的即为异常区。
经本公开的发明人研究发现，异常生长现象的发生的原因如下：
图4A为根据一些实施例的布线基板100的截面图。图4B为根据一些实施例的布线基板100的截面图。
请参阅图4A，导电线110的边缘处具有段差结构1101，段差结构1101处需要被保护层140覆盖，而段差结构1101通常会使得覆盖在此处的保护层140出现屋顶结构(Tip)，进而发生断裂，从而使得保护层140在段差结构1101处出现保护缺失，导致段差结构1101部分区域暴露。因此，在化学镍金工艺中，段差结构1101暴露的区域浸润在活化溶液中，导致在段差结构1101处出现氧化防护层170和/或导电功能层180的异常生长。
请参阅图4B，段差结构1101(可参阅图4A)处的氧化防护层170和导电功能层180在段差结构1101处扩展成球形；在一些情况下，氧化防护层170与段差结构1101并不是完全接触的，即二者之间具有间隙，而由于空隙的存在，为水氧侵蚀导电线110提供的路径。
请再次参阅图3，部分异常生长的氧化防护层170和/或导电功能层180沿着导电线110的边缘连接成条状。
其中，尤其是的氧化防护层170和/或导电功能层180沿着导电线110的边缘异常生长并连接成条状的部分容易脱落，脱落时会对导电线110的其他位置产生拉力，导致导电线110中位于异常区附近的部分在拉力的作用下一同脱落，使得导电线110发生断裂，从而使得连接于该导电线110的功能元件200失效。除此之外，脱落的异常生长若搭接导电焊盘131上，则会导电焊盘131所在区域发生短路，最终导致电连接该导电焊盘131的功能元件200无法正常工作。
请再次参阅图3，在一种实现方式中，导电焊盘131在平行于衬底120的方向上的最大尺寸L1，远远大于导电焊盘131的边缘到导电层130的边缘之间的最小距离L2。
首先需要说明的是，导电焊盘131在衬底120上的正投影可以为长方形、正方形、五边形等其他的多边形。在一些示例中，导电焊盘131在衬底120上的正投影还可以为圆形。在导电焊盘131为圆形的情况下，导电焊盘131在平行于衬底120的方向上的最大尺寸则为该圆形的直径。在导电焊盘131为凸多边形的情况下，请参阅图4B，导电焊盘131在平行于衬底120的方向上的最大尺寸则为该导电焊盘131的对角线的长度。
此外，还需要说明的是，请参阅图3，导电层130中包括导电线110，其中，导电焊盘131位于导电线110的端部区域，导电线110除了导电焊盘131所在位置的表面裸露以外，导电线110的其他区域的表面均被其他膜层(例如保护层)覆盖，导电层130的边缘指的是包括导电焊盘131的导电线110的边缘。导电焊盘131的边缘到导电层130的边缘之间的最小距离L2指的是， 该导电焊盘131的边缘与其所在的导电线110的边缘之间的最小距离。导电线110具有多个边缘，其中一个或多个边缘与导电焊盘131的边缘之间的距离最小。
图4C为根据一些实施例的活化反应的原理图。其中，需要说明的是，在图4C中箭头表示离子的运动方向。
请参阅图4C，在活化反应中，Pd 2+是起沉镍重要的催化剂，活化溶液中反应区域的Pd 2+快速消耗并沉积，而其余区域中的Pd 2+扩散汇集到反应区域，对反应区域中的Pd 2+进行补充。其中，需要说明的是，反应区域为导电焊盘131附近的区域。而导电焊盘131的面积越大且L1的取值越大，反应区域的Pd 2+消耗越快，Pd 2+扩散速度越大，越易在裸露的段差结构1101(如图4A所示)沉积钯层，进而后续越容易催化生长氧化防护层170和导电功能层180。
在上述的实现方式中，L1远大于L2，且导电焊盘131的面积过大。从而导致活化溶液中的反应区域的Pd 2+消耗过快，溶液中Pd 2+扩散速度过大，进而在裸露的段差结构1101会快速沉积钯层，后续催化生长氧化防护层170和导电功能层180，从而发生异常生长现象。
基于此，请参阅图5，图5为根据一些实施例的布线基板100的结构图。在本公开的一些实施例中所提供的布线基板100中，导电焊盘131在平行于衬底120的方向上的最大尺寸L1，大于或等于导电焊盘131的边缘到导电层130的边缘之间的最小距离L2的1.5倍，且小于或等于导电焊盘131的边缘到导电层130的边缘之间的最小距离L2的30倍，即1.5·L2≤L1≤30·L2。
示例性的，2·L2≤L1≤28·L2。
示例性的，1.5·L2≤L1≤7.5·L2。
示例性的，8·L2≤L1≤28·L2。
示例性的，2.5·L2≤L1≤11·L2。
示例性的，10·L2≤L1≤27·L2。其中，L1≤30·L2，因此，导电焊盘131在平行于衬底120的方向上的最大尺寸L1较小，从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较小，溶液中Pd 2+扩散速度较小，进而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少甚至避免异常生长现象的发生。
除此之外，L1≥1.5·L2，因此，可以避免导电焊盘131在平行于衬底120的方向上的最大尺寸L1过小(例如小于1.5·L2)，以此保证导电焊盘131与电子元件的引脚连接的可靠性。
图6为根据一些实施例的布线基板100的结构图。
请参阅图6，在一些实施例中，布线基板100包括多个器件区AA。多个焊盘组1300包括位于任一个器件区AA中的多个第一焊盘组1301和一个第二焊盘组1302。
其中，需要说明的是，背板1000包括布线基板100，布线基板100中的器件区AA与背板1000中的器件区AA为同一区域。
图7为根据一些实施例的布线基板100的结构图。在图7中示出了一个第一焊盘组1301和一个第二焊盘组1302。
请参阅图7，第一焊盘组1301包括间隔设置的第一极焊盘131P和第二极焊盘131N。其中，可以理解地，第一焊盘组1301中的导电焊盘131的数量不限于两个。也即，在一些示例中，第一焊盘组1301可以仅包括第一极焊盘131P和第二极焊盘131N；而在其他的一些示例中，第一焊盘组1301还可以包括其他的导电焊盘131。
在一些示例中，第一极焊盘131P和第二极焊盘131N在衬底120上的正投影可以为圆形或正方形、长方形以及五边形等多边形。
第一极焊盘131P可以与功能元件200的第一引脚P连接，第二极焊盘131N可以与功能元件200的第二引脚N连接。其中，图7中未示出功能元件200以及功能元件200的第一引脚P和第二引脚N，可参阅图1D。
其中，第一极焊盘131P的面积大于第一引脚P的面积，而第二极焊盘131N大于第二引脚N的面积，进而可以保证功能元件200与布线基板100连接的可靠性。
请参阅图7，第二焊盘组1302至少包括间隔设置的电源焊盘Pwr’、接地焊盘Gnd’、地址焊盘Di’和输出焊盘Ot’。其中，第二焊盘组1302与驱动芯片300连接。电源焊盘Pwr’与驱动芯片300的电源引脚Pwr连接，接地焊盘Gnd’与驱动芯片300的接地引脚Gnd连接，地址焊盘Di’与驱动芯片300的地址引脚Di连接，输出焊盘Ot’与驱动芯片300的输出引脚Ot连接。
在一些示例中，电源焊盘Pwr’、接地焊盘Gnd’、地址焊盘Di’和输出焊盘Ot’在衬底120上的正投影可以为圆形或正方形、长方形以及五边形等多边形。
在一些示例中，地址焊盘Di’和输出焊盘Ot’分别与电源焊盘Pwr’相邻的两个边缘相对设置，此外，地址焊盘Di’和输出焊盘Ot’还分别与接地焊盘Gnd’相邻的两个边缘相对设置。
请再次参阅图6，布线基板100还包括源地址线111、源电压线112、驱 动电压线113和公共电压线114。
在同一个器件区AA内：电源焊盘Pwr’电连接于源电压线112；地址焊盘Di’与另一个器件区AA内的输出焊盘Ot’电连接。其中，电源焊盘Pwr’与源电压线112电连接，接地焊盘Gnd’与公共电压线114电连接，地址焊盘Di’与源地址线111电连接，输出焊盘Ot’与驱动电压线113电连接。
在布线基板100包括两个导电层130的情况下，导电焊盘131位于第二个导电层130B中，此时，电源焊盘Pwr’通过转接线115(如图7所示)与源电压线112电连接，接地焊盘Gnd’通过转接线115与公共电压线114电连接，地址焊盘Di’通过转接线115与源地址线111电连接，输出焊盘Ot’通过转接线115与驱动电压线113电连接。
请参阅图6，在同一个器件区AA内：多个第一焊盘组1301中，第一个第一焊盘组1301A中的第一极焊盘131P与驱动电压线113电连接，而第一个第一焊盘组1301A中的第一极焊盘131P与第一个功能元件200A的第一引脚P(如图1C所示)连接，进而使得第一个功能元件200A的第一引脚P与驱动电压线113电连接。
在一些示例中，多个器件区AA呈多行多列排布，其中，一列器件区AA中的多个第一个第一焊盘组1301A中的第一极焊盘131P与同一条驱动电压线113连接，因此，多个第一个第一焊盘组1301A中的第一极焊盘131P并联设置。
请参阅图6，在同一个器件区AA内：上一个第一焊盘组1301中的第二极焊盘131N与下一个第一焊盘组1301中的第一极焊盘131P电连接，最后一个第一焊盘组1301的第二极焊盘131N与输出焊盘Ot’电连接。其中，需要说明的是，上一个第一焊盘组1301与下一个第一焊盘组1301指的是相邻的两个第一焊盘组1301。
其中，在同一个器件区AA内可以设置有一个或多个功能支路，其中，一个功能支路中具有一个第一个功能元件200A(如图1C所示)，可以理解是，在同一个器件区AA内可以具有一个或多个第一个第一焊盘组1301A。
在布线基板100包括两个导电层130的情况下，上一个第一焊盘组1301中的第二极焊盘131N与下一个第一焊盘组1301中的第一极焊盘131P分别设置于一条转接线115的两端。
示例性的，请参阅图6，在同一个器件区AA内包括9个第一焊盘组1301，9个第一焊盘组1301依次为第一个第一焊盘组1301A……第八个第一焊盘组1301H和第九个第一焊盘组1301I。其中，第九个第一焊盘组1301I即为最后 一个第一焊盘组1301。
可以理解的是，在第八个第一焊盘组1301H和第九个第一焊盘组1301I中，第八个第一焊盘组1301H是上一个第一焊盘组1301，而第九个第一焊盘组1301I是下一个第一焊盘组1301。其中，第八个第一焊盘组1301H的第二极焊盘131N与第九个第一焊盘组1301I的第一极焊盘131P电连接。
其中，第一焊盘组1301中的第一极焊盘131P和第二极焊盘131N相邻设置，且第一极焊盘131P和第二极焊盘131N彼此绝缘，二者需要通过功能元件200电连接。
在一些实施例中，至少第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’中的至少一个，在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。可以理解的是，此处的“该焊盘”指的是上述至少第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’中的任意一个。
在活化反应中，活化溶液可以为阴极，导电层130可以为阳极。由于导电层130中的Cu失去电子形成了Cu 2+，Cu所失去的电子可以在导电线110中流动。此时连接于同一条驱动电压线113中的多个第一个第一焊盘组1301A中的第一极焊盘131P发生电化学并联反应，即多个第一个第一焊盘组1301A中的第一极焊盘131P并联设置。因此，多个第一个第一焊盘组1301A中的第一极焊盘131P所失去的电子在驱动电压线113中流动。可以理解的是，在布线基板100包括两个导电层130的情况下，多个第一个第一焊盘组1301A中的第一极焊盘131P所失去的电子还在与驱动电压线113连接的转接线115中流动。
根据并联电路原理可知，并联电路的总电路的电流等于各支路的电流之和，因此，与导电线110所电连接的导电焊盘131的数量越多，该导电线110中的电流越大。其中由于驱动电压线113所电连接的导电焊盘131的数量较多，大于其他一些导电线110所电连接的导电焊盘131的数量，因此，驱动电压线113中的电流较大，进而驱动电压线113所电连接的第一个第一焊盘组1301A中的第一极焊盘131P中的电流较大。而电流越大，置换反应速度越快，即形成钯层的速度越快，进而后续越容易形成氧化防护层170和导电功能层180。因此，第一个第一焊盘组1301A中的第一极焊盘131P周围的保护层缺失区域(即段差结构1101暴露的区域)更容易发生异常生长现象。
同理，多个第二焊盘组1302中的电源焊盘Pwr’均电连接于源电压线112， 因此，多个电源焊盘Pwr’并联设置，进而源电压线112中的电流较大，该源电压线112所电连接的多个电源焊盘Pwr’的置换反应速度较快，即形成钯层的速度越快，进而后续越容易形成氧化防护层170和导电功能层180。因此，电源焊盘Pwr’中周围的保护层缺失区域(即段差结构1101暴露的区域)更容易发生异常生长现象。
同理，多个第二焊盘组1302中的接地焊盘Gnd’均电连接于公共电压线114，因此，多个接地焊盘Gnd’并联设置，进而公共电压线114中的电流较大，该公共电压线114所电连接的多个接地焊盘Gnd’的置换反应速度较快，即形成钯层的速度较快，进而后续越容易形成氧化防护层170和导电功能层180。因此，接地焊盘Gnd’周围的保护层缺失区域(即段差结构1101暴露的区域)更容易发生异常生长现象。
因此，在本公开的一些实施例中，使得至少第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’中的至少一个，在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。可以减少第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’中的至少一个的附近的保护层缺失区域发生异常生长现象。
在一些示例中，可以仅使得第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’，在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。
在其他的一些示例中，可以使得第一个第一焊盘组1301A中的第一极焊盘131P、电源焊盘Pwr’和接地焊盘Gnd’中的部分，在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。
在另一些示例中，还可以使得布线基板100中的所有导电焊盘131在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。
以上对布线基板100中包括器件区AA包括一个子器件区A1和一个控制区A2的实施例进行了介绍。下面，对器件区AA包括至少两个子器件区A1和一个控制区A2进行介绍。
图8为根据一些实施例的布线基板100的结构图。
请参阅图8，在其他的一些示例中，器件区AA包括至少两个子器件区 A1和一个控制区A2。
多个焊盘组1300包括位于任一个子器件区A1中的多个第一焊盘组1301，第一焊盘组1301包括间隔设置的第一极焊盘131P和第二极焊盘131N。第一焊盘组1301用于与功能元件200连接。
多个焊盘组1300还包括位于控制区A2内的第二焊盘组1302；第二焊盘组1302包括电源焊盘Pwr’、接地焊盘Gnd’、地址输入焊盘Din’、地址输出焊盘Dio’和至少两个输出焊盘(Ot1’和Ot2’等)。其中，电源焊盘Pwr’电连接于源电压线112。其中，属于两个不同器件区AA中的一个器件区AA内的控制区A2内的地址输出焊盘Dio’与另一个器件区AA内的控制区A2内的地址输入焊盘Din’连接。
在同一个子器件区A1内：多个第一焊盘组1301中，第一个第一焊盘组1301A中的第一极焊盘131P与驱动电压线113电连接，上一个第一焊盘组1301中的第二极焊盘131N与下一个第一焊盘组1301中的第一极焊盘131P电连接，最后一个第一焊盘组1301I的第二极焊盘131N与一个输出焊盘Otx’电连接，其中x可以为大于或等于2的正整数。其中，多个子器件区A1中每个子器件区A1的最后一个第一焊盘组1301I的第二极焊盘131N分别与控制区A2中的一个输出焊盘Otx’连接。示例性的，当器件区AA包括两个子器件区A1时，此时输出焊盘Ot2’即为输出焊盘Otx’，其中一个子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N连接于输出焊盘Ot1’，另一个子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N连接于输出焊盘Ot2’。
其中，至少第一个第一焊盘组1301A中的第一极焊盘131P，在平行于衬底120的方向上的最大尺寸，小于或等于该第一极焊盘131P的边缘到导电层130的边缘之间的最小距离的30倍。
属于同一器件区AA的多个子器件区A1中的每个子器件区A1的第一个第一焊盘组1301A中的第一极焊盘131P并联设置，经上文可知，一条导电线110中并联导电焊盘131的数量越多，该导电线110中的导电焊盘131的置换反应速度越快，即形成钯层的速度越快，进而后续越容易形成氧化防护层170和导电功能层180。因此，第一个第一焊盘组1301A中的第一极焊盘131P的附近的保护层缺失区域(即段差结构1101暴露的区域)更容易发生异常生长现象。
通过使得第一个第一焊盘组1301A中的第一极焊盘131P，在平行于衬底120的方向上的最大尺寸L1，小于或等于该第一极焊盘131P的边缘到导电层 130的边缘之间的最小距离的30倍，可以减少第一个第一焊盘组1301A中的第一极焊盘131P的附近的保护层缺失区域发生异常生长现象。
在另一些实施例中，布线基板100中可以包括一个器件区AA，该器件区AA中包括多个子器件区A1和一个控制区A2。
多个焊盘组1300包括位于任一个子器件区A1中的多个第一焊盘组1301。示例性的，一个子器件区A1中设置有一个发光支路。
多个焊盘组1300还包括位于控制区A2内的第二焊盘组1302；第二焊盘组1302包括电源焊盘Pwr’、接地焊盘Gnd’、地址焊盘Di’和多个输出焊盘Ot’，其中，输出焊Ot’的数量与发光支路的数量相同。
其中，在同一个子器件区A1内：多个第一焊盘组1301中，第一个第一焊盘组1301A中的第一极焊盘131P与驱动电压线113电连接，上一个第一焊盘组1301中的第二极焊盘131N与下一个第一焊盘组1301中的第一极焊盘131P电连接，最后一个第一焊盘组1301I的第二极焊盘131N与一个输出焊盘Ot’电连接。其中，需要说明的是，所有子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N分别连接于不同的输出焊盘Ot’。
除了上述使得每个子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N分别连接于不同的输出焊盘Ot’的实施例外，还可以使得控制区A2仅设置有一个输出焊Ot’。此时，每个子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N连接于同一个输出焊盘Ot’。此时，多个子器件区A1中的最后一个第一焊盘组1301I的第二极焊盘131N并联设置，因此，最后一个第一焊盘组1301I的第二极焊盘131N附近的保护层缺失区域容易发生异常生长现象。
在一些示例中，可以使得最后一个第一焊盘组1301的第二极焊盘131N，在平行于衬底120的方向上的最大尺寸L1，小于或等于该导电焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。
在一些示例中，可以使得第一个第一焊盘组1301A中的第一极焊盘131P和/或最后一个第一焊盘组1301的第二极焊盘131N，在平行于衬底120的方向上的最大尺寸L1，小于或等于该焊盘的边缘到导电层130的边缘之间的最小距离L2的30倍。图9A为图7中D处的局部放大图，图9A示出了一个第一焊盘组1301。
在一些示例中，第一焊盘组1301中的导电焊盘131，在平行于衬底120的方向上的最大尺寸L11，大于或等于该导电焊盘131的边缘到导电层130的边缘之间的最小距离L21的1.5倍，且小于或等于该导电焊盘131的边缘到 导电层130的边缘之间的最小距离L21的28倍，即1.5·L21≤L11≤28·L21。其中，可以理解的是，在一些示例中，第一焊盘组1301中的导电焊盘131指的是第一极焊盘131P和第二极焊盘131N。
其中，L11≤28·L21，因此，第一焊盘组1301中的导电焊盘131在平行于衬底120的方向上的最大尺寸L11较小，从而可以使得活化溶液中对应于第一焊盘组1301中导电焊盘131的反应区域的Pd 2+消耗速度较小，Pd 2+扩散速度较小，进而可以减小第一焊盘组1301中导电焊盘131附近的裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
此外，L11≥1.5·L21，因此，可以避免第一焊盘组1301中的导电焊盘131在平行于衬底120的方向上的最大尺寸L11过小(例如小于1.5·L21)，以此保证导电焊盘131与功能元件200的引脚连接的可靠性。
示例性的，2.3·L21≤L11≤28·L21。
示例性的，3·L21≤L11≤10·L21。
示例性的，2.3·L21≤L11≤7·L21。
示例性的，9·L21≤L11≤28·L21。
示例性的，2·L21≤L11≤15·L21。
示例性的，12μm≤L21≤50μm。
图9B为图7中E处的局部放大图。
请参阅图9B，在一些示例中，第二焊盘组1302中的导电焊盘131，在平行于衬底120的方向上的最大尺寸L12，大于或等于该导电焊盘131的边缘到导电层130的边缘之间的最小距离L22的1.5倍，且小于或等于该导电焊盘131的边缘到导电层130的边缘之间的最小距离L22的26倍，即1.5·L22≤L12≤26·L22。其中，可以理解的是，在一些示例中，第二焊盘组1302的导电焊盘131指的是电源焊盘Pwr’、接地焊盘Gnd’、地址焊盘Di’和输出焊盘Ot’。
其中，L12≤26·L22，因此，第二焊盘组1302中的导电焊盘131在平行于衬底120的方向上的最大尺寸L12较小，从而可以使得活化溶液中对应于第二焊盘组1302中导电焊盘131的反应区域的Pd 2+消耗速度较小，进而Pd 2+扩散速度较小，进而可以减小第二焊盘组1302中导电焊盘131附近的裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
此外，L12≥1.5·L22，因此，可以避免第二焊盘组1302中的导电焊盘131在平行于衬底120的方向上的最大尺寸L12过小(例如小于1.5·L22)，以此保证导电焊盘131与驱动芯片300的引脚连接的可靠性。
示例性的，1.5·L22≤L12≤5·L22。
示例性的，5·L22≤L12≤11·L22。
示例性的，2.5·L22≤L12≤5.5·L22。
示例性的，2.5·L22≤L12≤7·L22。
示例性的，2.5·L22≤L12≤15·L22。
示例性的，15·L22≤L12≤25·L22。
示例性的，7μm≤L22≤50μm。
请再次参阅图9A和图9B，在一些实施例中，在同一个焊盘组1300中，导电焊盘131在平行于衬底120的方向上的最大尺寸L1，为该导电焊盘131与相邻的导电焊盘131之间的距离L3的0.5～5倍，即0.5·L3≤L1≤5·L3。其中，相邻的两个导电焊盘131位于同一个焊盘组1300中。一个导电焊盘131与相邻的导电焊盘131之间的距离L3，为二者之间的最小距离。
在一些示例中，同一个焊盘组1300中相邻的两个导电焊盘131可以分别设置于两条导电线110上。此时，相邻的两个导电焊盘131之间的间距会受到与上述相邻的两个导电焊盘131所在的两根导电线110之间的间距的影响，此时，相邻的两个导电焊盘131所在的导电线110之间的距离越大，相邻的两个导电焊盘131之间的距离可以设置的越大。
在另一些示例中，同一个焊盘组1300中相邻的两个导电焊盘131可以位于同一条导电线110上，例如驱动芯片300包括两个接地引脚Gnd，对应的，与该驱动芯片300所连接的第二焊盘组1302中包括两个接地焊盘Gnd’。其中，驱动芯片300中的接地引脚Gnd彼此分离，因此，两个接地焊盘Gnd’彼此之间设置有间隔。此时，两个接地焊盘Gnd’可以设置于同一条导电线110上。此时，两个接地焊盘Gnd’相邻设置，并且两个接地焊盘Gnd’的形状以及二者之间的间距可能受限于两个接地焊盘Gnd’所在导电线110的线宽和/或线长。此时，两个接地焊盘Gnd’所在导电线110的线宽和/或线长越小，两个接地焊盘Gnd’之间的距离相对越小。
可以理解的是，任一个第一焊盘组中各个导电焊盘的相对位置关系，和待与该第一焊盘组连接的一个电子元件的各个引脚的相对位置关系基本相同；任一个第二焊盘组中各个导电焊盘的相对位置关系，和待与该第二焊盘组连接的一个电子元件的各个引脚的相对位置关系基本相同。
其中，0.5·L3≤L1≤5·L3，进而可以避免L1过大(例如大于5·L3)，从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较小，溶液中Pd 2+扩散速度较小，进而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。此外，还可以避免L1过小(例如小于0.5·L3)，以此保证导电焊盘131与电子元件的引脚连接的可靠性。
请参阅图9A和图9B，在一些实施例中，导电焊盘131在平行于衬底120的方向上的最大尺寸L1大于或等于105μm，且小于或等于350μm。
其中，105μm≤L1≤350μm，因此，可以避免L1的取值过大，例如(大于350μm)。经上文可知，L1越大，活化溶液中的反应区域的Pd 2+消耗速度越快，因此，在本公开的一些实施例中，通过使得L1≤105μm，可以使得活化溶液中的反应区域的Pd 2+消耗速度较小，Pd 2+扩散速度较小，进而可以减慢裸露的段差结构1101沉积钯层的速度，从而减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
此外，还可以避免L1过小(例如小于105μm)，导致导电焊盘131与电子元件的引脚连接的可靠性较低，可以理解的是，此处的“电子元件”包括上述的功能元件200和驱动芯片300。在本公开的一些实施例中，通过使得L1大于或等于105μm，可以保证导电焊盘131与电子元件的引脚连接的可靠性。
请参阅图9A，在一些示例中，第一焊盘组1301中导电焊盘131在平行于衬底120的方向上的最大尺寸L11，大于或等于105μm，且小于或等于350μm。
在一些示例中，导电焊盘131的边缘到导电层130的边缘之间的最小距离L2大于等于7μm，小于或等于50μm。
示例性的，第一焊盘组1301中的导电焊盘131为长方形。
在一些示例中，第一焊盘组1301中的导电焊盘131的长L4大于或等于2·L21，且小于或等于25·L21。
在一些示例中，第一焊盘组1301中的导电焊盘131的长L4大于或等于80μm，且小于或等于280μm。
示例性的，L4的取值可以为102μm、162μm以及264μm等。
在一些示例中，第一焊盘组1301中的导电焊盘131的宽L5大于或等于L21，且小于或等于20·L21。
在一些示例中，第一焊盘组1301中的导电焊盘131的宽L5大于或等于45μm，且小于或等于220μm。
示例性的，L5的取值可以为62μm、122μm以及205μm等。
示例性的，12μm≤L21≤50μm。
请参阅图9B，在一些示例中，第二焊盘组1302中导电焊盘131在平行于衬底120的方向上的最大尺寸L12，大于或等于105μm，且小于或等于190μm。
在一些示例中，第二焊盘组1302的导电焊盘131为正方形，此时，第二焊盘组1302中导电焊盘131的边长L6大于或等于1.5·L22，且小于或等于20·L22。
在一些示例中，L6大于或等于70μm，且小于或等于140μm。
示例性的，L6的取值可以为82μm、92μm以及122μm等。
示例性的，7μm≤L22≤50μm。
在一些实施例中，至少两个焊盘组1300中导电焊盘131的面积的大小，与相邻的两个导电焊盘131之间的距离L3，呈正相关关系。
其可以理解为：导电焊盘131的面积越大，该导电焊盘131与相邻的导电焊盘131之间的距离L3越大。
其中，相邻的两个导电焊盘131之间的距离L3越大，相邻的两个导电焊盘131所在的焊盘组1300所对应的反应区域的越大，此时，焊盘组1300所对应的反应区域内的Pd 2+消耗速度越慢。而导电焊盘131的面积越大，该导电焊盘131所对应的反应区域内的Pd 2+消耗越快，进而该导电焊盘131所在的焊盘组1300所对应的反应区域内的Pd 2+消耗速度越快。
因此，在本公开的一些实施例中，通过在导电焊盘131的面积较大的情况下，使得该导电焊盘131与相邻的导电焊盘131之间的距离L3较大，可以降低导电焊盘131所在的焊盘组1300所对应的反应区域内的Pd 2+消耗速度，进而可以降低溶液中Pd 2+扩散速度，从而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
在一些示例中，在指定的两个焊盘组1300中，其中一个焊盘组1300中导电焊盘131的面积大于另一个焊盘组1300中导电焊盘131的面积，而面积较大的导电焊盘131与相邻的导电焊盘131之间的距离L3，大于另一个焊盘组1300中相邻的两个导电焊盘131之间的距离L3。
而在另一些示例中，在其他指定的两个焊盘组1300中，其中一个焊盘组 1300中导电焊盘131的面积大于另一个焊盘组1300中导电焊盘131的面积，而面积较大的导电焊盘131与相邻的导电焊盘131之间的距离L3，小于另一个焊盘组1300中相邻的两个导电焊盘131之间的距离L3。
在一些实施例中，导电焊盘131的面积大于或等于5000μm 2，且小于或等于55000μm 2。
其中，通过使得导电焊盘131的面积小于或等于55000μm 2，可以避免导电焊盘131的面积过大。从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较慢，溶液中Pd 2+扩散速度较慢，进而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
此外，通过使得导电焊盘131的面积大于或等于5000μm 2，可以避免导电焊盘131的面积过小，进而可以保证导电焊盘131与电子元件的引脚连接的可靠性。
在一些示例中，第一焊盘组1301中导电焊盘131的面积大于或等于5000μm 2，且小于或等于55000μm 2。示例性的，第一焊盘组1301中导电焊盘131的面积大于或等于6200μm 2，且小于或等于54700μm 2。
在一些示例中，第二焊盘组1302中导电焊盘131的面积大于或等于5500μm 2，且小于或等于15500μm 2。
示例性的，第二焊盘组1302中导电焊盘131的面积大于或等于6600μm 2，且小于或等于15000μm 2。
在一些实施例中，在同一个焊盘组1300中，相邻的两个导电焊盘131之间的距离L3，大于或等于70μm，且小于或等于214μm，即70μm≤L3≤214μm。
由上文可知，L3的取值越大，活化溶液中的反应区域的Pd 2+消耗速度越慢。而本公开的一些实施例中，通过使得L3≥70μm，从而可以避免L3过小(例如小于70μm)，从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较慢，溶液中Pd 2+扩散速度较慢，从而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
此外，通过使得L3≤214μm，从而可以避免L3过大(例如大于214μm)，导致相邻的两个导电焊盘131之间的距离过大，所述两个导电焊盘131所在的焊盘组1300所占用的面积过大，进而导致布线基板100的面积过大。
在上面的一些实施例中，介绍了可以通过减小导电焊盘131的面积和/或增大相邻的两个导电焊盘131之间的距离，减少长金不良的现象发生，除此 之外，还可以通过其他的方案来减少长金不良的现象发生。
下面，对导电焊盘131的面积与该导电焊盘131所连接的电子元件的引脚的尺寸的之间的关系进行介绍。
图10为根据一些实施例的布线基板100的结构图。其中，P所指示的虚线框为功能元件200的第一引脚P在导电层130上的正投影所覆盖的区域。N所指示的虚线框为功能元件200的第二引脚N在导电层130上的正投影所覆盖的区域。
在一些示例中，导电焊盘131在衬底120上的正投影所形成的图形，与该导电焊盘131所连接的电子元件的引脚在在衬底120上的正投影所形成的图形，形状大致相同。其中，为了方便叙述，将导电焊盘131在衬底120上的正投影所形成的图形定义为第一图形J，将电子元件的引脚在在衬底120上的正投影所形成的图形定义为第二图形K。此外，可以理解的是，上述导电焊盘131为第一焊盘组1301中的第一极焊盘131P或第二极焊盘131N，还可以为第二焊盘组1302中电源焊盘Pwr’、接地焊盘Gnd’、地址焊盘Di’、输出焊盘Ot’中的任一个。而电子元件的引脚可以为功能元件200的第一引脚P或第二引脚N，还可以为驱动芯片300中的电源引脚Pwr、接地引脚Gnd、地址引脚Di、输出引脚Ot中的任一个。
其中，第二图形K位于第一图形J之内。示例性的，第一图形J和第二图形K均为长方形。
在一些示例中，第一图形J包括至少一个第一边沿J1，可以理解的是，当第一图形J包括一个第一边沿J1时，第一图形J为圆形。此外，当第一图形J为长方形时，第一图形J的部分第一边沿J1的长度不同。当第一图形J为正方形时，第一图形J的多个第一边沿J1的长度相同。
而第二图形K包括至少一个第二边沿K2。其中，一条第一边沿J1与一条第二边沿K2相对设置。可以理解的是，当第二图形K包括一个第一边沿J1时，第二图形K为圆形。当第二图形K为长方形时，第二图形K的部分第二边沿K2的长度不同。当第二图形K为正方形时，第二图形K的多个第二边沿K2的长度相同。
其中，在相对设置的第一边沿J1和第二边沿K2中，第一边沿J1的长度Lj与第二边沿K2的长度Lk的差值，大于或等于2μm，且小于或等于4μm，即2μm≤Lj－Lk≤4μm。其中，第一边沿J1的长度Lj大于第二边沿K2的长度Lk。
下面以导电焊盘131为第一焊盘组1301的第一极焊盘131P或第二极焊 盘131N为例，对第一边沿J1和第二边沿K2进行示例性说明。
其中，同一个第一焊盘组1301中的，第一极焊盘131P在衬底120上的正投影所形成的图形和第二极焊盘131N在衬底120上的正投影所形成的图形，型状相同，大小相等。其中可以理解的是，“型状相同，大小相等”指的是，将第一极焊盘131P在衬底120上的正投影所形成的图形在衬底120上平移指定距离后，能够与第二极焊盘131N在衬底120上的正投影所形成的图形完全重叠。
请参阅图10，第一图形J包括两条第一个第一边沿J11和两条第二个第一边沿J12，其中，第一个第一边沿J11的长度大于第二个第一边沿J12的长度。第二图形K包括两条第一个第二边沿K21和两条第二个第二边沿K22，第一个第二边沿K21的长度大于第二个第二边沿K22的长度。其中，一条第一个第一边沿J11与一条第一个第二边沿K21边沿相对设置，一条第二个第一边沿J12与一条第二个第二边沿K22相对设置。
其中，第一个第一边沿J11的长度Lj1与第一个第二边沿K21的长度Lk1的差值，且大于或等于2μm，小于或等于4μm，即2μm≤Lj1－Lk1≤4μm。第二个第一边沿J12的长度Lj2比第二个第二边沿K22的长度Lk2，大于或等于2μm，且小于或等于4μm，即2μm≤Lj2－Lk2≤4μm。
通过使得在相对设置的第一边沿J1和第二边沿K2中，第一边沿J1的长度Lj与第二边沿K2的长度Lk的差值小于或等于4μm，可以避免第一边沿J1的长度过大导致第一焊盘组1301的导电焊盘131的面积过大，从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较慢，溶液中Pd 2+扩散速度较慢，进而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。此外，通过使得在相对设置的第一边沿J1和第二边沿K2中，第一边沿J1的长度Lj与第二边沿K2的长度Lk的差值大于或等于2μm可以避免第一边沿J1的长度Lj的长度过小，进而导致导电焊盘131的面积过小，无法保证第一焊盘组1301的导电焊盘131与功能元件200的引脚的连接的可靠性。
经上文可知，布线基板100中可以包括两个导电层130，也可以包括一个导电层，下面基于布线基板100中包括一个导电层130的实施例，对布线基板100中的导电焊盘131进行介绍。
图11为根据一些实施例的布线基板100的结构图。图12为图11中F处的局部放大图。
请参阅图11和图12，第二焊盘组1302位于源电压线112上，其中，源电压线112穿过接地焊盘Gnd’与输出焊盘Ot’之间的间隙。
在一些示例中，接地焊盘Gnd’和地址焊盘Di’分别与输出焊盘Ot’相邻的两个边缘相对设置。此外，接地焊盘Gnd’和地址焊盘Di’分别与电源焊盘Pwr’相邻的两个边缘相对设置。
图13为图2A中G处的局部放大图。
在一些实施例中，导电层130中包括多条导电线110，导电线110被开口141暴露出的区域即为导电焊盘131；在垂直于衬底且垂直于导电线110延伸方向的截面上，可以看到导电线110的主表面1102以及与主表面1102相连的侧表面1103，其中，主表面1102为导电线110背离衬底120的一个表面；主表面1102与侧表面1103之间的夹角H1大于或等于105°，且小于或等于145°。
其中，主表面1102与侧表面1103之间的夹角H1越大，越容易产生段差结构1101，进而越容易使得导电线110的边缘暴露。
在本公开的一些实施例中，通过使得主表面1102与侧表面1103之间的夹角H1大于或等于105°，可以避免H1过小(例如小于105°)，从而可以使得H1较小，进而产生段差结构1101的几率较小，从而可以使得导电线110的边缘暴露的几率较小，进而能够减少异常生长的现象。
除此之外，侧表面1103与衬底120之间的夹角H2与主表面1102与侧表面1103之间的夹角H1互补，即H1+H2＝180°，其中，H2指的是侧表面1103与衬底120之间的所夹的锐角。因此，H2越大，H1就越小，而侧表面1103与衬底120之间的夹角H2越小，保护层140对侧表面1103的覆盖效果越好，导电线110越不容易暴露。在本公开一些实施例中，通过使得主表面1102与侧表面1103之间的夹角H1大于或等于105°，进而可以使得侧表面1103与衬底120之间的夹角H1小于或等于75°，进而可以避免侧表面1103与衬底120之间的夹角过大(例如大于75°)，从而可以保证保护层140对侧表面1103的覆盖效果，进而可以减小导电线110暴露的发生率，从而可以减少异常生长现象。
在本公开的一些实施例中，通过使得主表面1102与侧表面1103之间的夹角H1小于或等于145°，可以避免H1过大(例如大于145°)，导致工艺难度较大。
在一些示例中，主表面1102与侧表面1103之间的夹角H1大于或等于115°，且小于或等于140°。
请再次参阅图9A，在一些实施例中，多个侧表面1103中与导电线110的导电焊盘131距离较短的至少两个侧表面1103为第一侧表面1103A；两个第一侧表面1103A之间由曲面连接。
在一些示例中，一个导电焊盘131具有两个与该导电焊盘131距离较近的第一侧表面1103A。两个第一侧表面1103A与导电焊盘131的边缘之间的距离小于其他侧表面1103与导电焊盘131的边缘之间的距离。其中，需要说明的是，两个第一侧表面1103A与导电焊盘131的边缘之间的距离可以相等，也可以不等。
请参阅图9A，第一极焊盘131P所在的导电线110中的一个第一侧表面1103A与第二极焊盘131N所在的导电线110中的一个第一侧表面1103A，均位于第一极焊盘131P与第二极焊盘131N之间。
在一些示例中，位于第一极焊盘131P和第二极焊盘131N之间的第一侧表面1103A的两端所连接的侧表面1103均为第一侧表面1103A。
请参阅图9B，电源焊盘Pwr’所在导电线110的两个第一侧表面1103A分别位于电源焊盘Pwr’和输出焊盘Ot’之间、电源焊盘Pwr’和地址焊盘Di’之间。
输出焊盘Ot’所在导电线110的两个第一侧表面1103A分别位于输出焊盘Ot’和电源焊盘Pwr’之间、输出焊盘Ot’和接地焊盘Gnd’之间。
接地焊盘Gnd’所在导电线110的两个第一侧表面1103A分别位于接地焊盘Gnd’和输出焊盘Ot’之间、接地焊盘Gnd’和地址焊盘Di’之间。
地址焊盘Di’所在导电线110的两个第一侧表面1103A分别位于地址焊盘Di’和接地焊盘Gnd’之间，地址焊盘Di’和电源焊盘Pwr’之间。
请参阅图12，在源电压线112穿过接地焊盘Gnd’与输出焊盘Ot’之间的间隙的情况下，输出焊盘Ot’所在导电线110的两个第一侧表面1103A分别位于输出焊盘Ot’与接地焊盘Gnd’之间、输出焊盘Ot’与地址焊盘Di’之间。地址焊盘Di’所在导电线110的两个第一侧表面1103A分别位于地址焊盘Di’与输出焊盘Ot’之间、地址焊盘Di’与电源焊盘Pwr’之间。而接地焊盘Gnd’的两个第一侧表面1103A分别位于接地焊盘Gnd’与电源焊盘Pwr’之间、接地焊盘Gnd’与输出焊盘Ot’之间。
其中，两个第一侧表面1103A通过曲面连接，即两个第一侧表面1103A的交汇处在衬底120上的正投影为第一圆角1104，可以减少导电线110的尖锐边缘，在背板1000的使用过程中，尖锐边缘容易产生静电积累。在本公开的一些实施例中，两个第一侧表面1103A通过曲面连接，可以减少导电线110 中的静电积累。
在一些实施例中，第一圆角1104的半径R大于或等于20μm，且小于或等于30μm。
在本公开的一些实施例中，通过使得第一圆角1104的半径R大于或等于20μm，可以避免第一圆角1104的半径R过小(例如小于20μm)，从而不能有效防静电积累的情况出现，从而可以使得导电线110具有较好的防静电积累的效果。
此外，第一圆角1104的半径R越大，导电焊盘131的边缘与第一圆角1104的边缘越近。在本公开的一些实施例中，通过使得曲面或第一圆角1104的半径R小于或等于30μm，可以避免第一圆角1104的半径R过大(例如大于30μm)，进而可以避免导电焊盘131的边缘与第一圆角1104的边缘的距离过小。
本公开的一些实施例中所提供的背板1000包括以上一些实施例所提供的布线基板100，因此，本公开的一些实施例中所提供的背板1000包括以上一些实施例所提供的布线基板100的全部有益效果，在此不再赘述。
图14为根据一些实施例的显示装置2000的结构图。
请参阅图14，本公开的一些实施例还提供了一种显示装置2000，显示装置2000包括：背光模组500和液晶显示面板600，其中，背光模组500为以上一些实施例所提供的背板1000，功能元件200包括发光二极管。液晶显示面板600位于背光模组500的出光侧。其中，本公开的一些实施例所提供的显示装置2000具有以上一些实施例所提供的背板1000的全部有益效果，在此不进行赘述。
可以理解地，显示装置2000可以显示动态图像信息，例如视频或者游戏画面，也可以显示静态图像信息，例如图像或者照片。
请参阅图14，在一些实施例中，液晶显示面板600的主要结构包括阵列基板61、对盒基板62以及设置在阵列基板61和对盒基板62之间的液晶层63。
阵列基板61的每个亚像素均包括位于第一衬底610上的薄膜晶体管611和像素电极612。薄膜晶体管611包括有源层、源极、漏极、栅极及栅绝缘层，源极和漏极分别与有源层接触，像素电极612与薄膜晶体管611的漏极电连接。在一些实施例中，阵列基板61还包括设置在第一衬底610上的公共电极613。像素电极612和公共电极613可以设置在同一层，在此情况下，像素电极612和公共电极613均为包括多个条状子电极的梳齿结构。像素电极612 和公共电极613也可以设置在不同层，在此情况下，如图14所示，像素电极612和公共电极613之间设置有第一层间绝缘层614。在公共电极613设置在薄膜晶体管611和像素电极612之间的情况下，如图14所示，公共电极613与薄膜晶体管611之间还设置有第二层间绝缘层615。而在另一些实施例中，阵列基板61不包括公共电极613，此时，公共电极613可以位于对盒基板62中。
如图14所示，阵列基板61还包括设置在薄膜晶体管611和像素电极312远离第一衬底610一侧的平坦层616。
如图14所示，对盒基板62包括设置在第二衬底620上的彩色滤光层621，在此情况下，对盒基板62也可以称为彩膜基板(Color Filter，简称CF)。其中，彩色滤光层621至少包括红色光阻单元、绿色光阻单元以及蓝色光阻单元，红色光阻单元、绿色光阻单元以及蓝色光阻单元分别与阵列基板61上的亚像素一一正对。对盒基板62还包括设置在第二衬底620上的黑矩阵图案622，黑矩阵图案622用于将红色光阻单元、绿色光阻单元以及蓝色光阻单元间隔开。
可以理解地，光线能够经由背光模组500的出光侧射出，并照射至液晶层63。通过调节液晶层63中液晶分子的排布方式，能够对透过液晶层63的光线强度起到调节作用，从而对照射至对盒基板62的光线强度起到调节作用。而对盒基板62包括彩色滤光层621，这样一来，通过调节照射至不同颜色光阻单元的光线强度，就能够使得显示装置2000实现彩色图像的显示功能。
如图14所示，液晶显示面板600还包括设置在对盒基板62远离液晶层63一侧的上偏光片64以及设置在阵列基板61远离液晶层63一侧的下偏光片65。
图15为根据一些实施例的显示装置3000的结构图。
请参阅图15，本公开的一些实施例还提供了一种显示装置3000，该显示装置3000包括：显示面板700，显示面板700包括以上一些实施例所提供的背板1000。其中，本公开的一些实施例所提供的显示装置3000具有以上一些实施例所提供的背板1000的全部有益效果，在此不进行赘述。
可以理解地，显示装置3000可以显示动态图像信息，例如视频或者游戏画面，也可以显示静态图像信息，例如图像或者照片。
在一些实施例中，显示装置3000可以为LED显示器、Mini LED显示器或者Micro LED显示器等。可以理解地，背板1000中的多个LED芯片用于发红色光、绿色光和蓝色光，使得显示装置3000能够实现彩色显示。
图16为根据一些实施例的布线基板的制备方法的流程图。
请参阅图16，本公开的一些实施例还提供了一种布线基板的制备方法，用于形成以上一些实施例所提供的布线基板100。该布线基板的制备方法包括以下步骤S1～S2。
S1、请参阅图2A和图2B，在衬底120上形成导电层130，其中，导电层130中包括多个焊盘组1300，一个焊盘组1300包括多个导电焊盘131。
S2、请参阅图2A和图2B，在导电层130远离衬底120的一侧形成保护层140，并在保护层140上形成开口141，其中，导电层130暴露于开口141的部分为导电焊盘131，导电焊盘131在平行于衬底120的方向上的最大尺寸L1，小于或等于导电焊盘131的边缘到导电层130的边缘之间的最小距离L2的30倍。
其中，L1≤30·L2，因此，导电焊盘131在平行于衬底120的方向上的最大尺寸L1较小，从而可以使得活化溶液中的反应区域的Pd 2+消耗速度较小，溶液中Pd 2+扩散速度较小，进而可以减小裸露的段差结构1101沉积钯层的速度，减慢后续催化生长氧化防护层170和导电功能层180的速度，从而减少异常生长现象的发生，甚至避免发生异常生长现象。
图17为根据一些实施例的布线基板的制备方法的流程图。图18～图22为根据一些实施例的布线基板的制备方法的步骤图。
请参阅图17，在一些实施例中，在S1、在衬底120上形成导电层130的步骤，包括：以下步骤S11～S15。
S11、请参阅图18，在衬底120上沉积导电材料，以形成初始导电层130’。
其中，在步骤S11中，可以采用沉积工艺形成初始导电层130’。
请参阅图18，在形成初始导电层130’之前，还可以在衬底120的一侧形成缓冲层150，而初始导电层130’形成于缓冲层150远离衬底120的一侧。
S12、请参阅图19，在初始导电层130’远离衬底120的一侧形成光刻胶层190。
S13、在指定温度下，烘烤光刻胶层190，其中，指定温度大于或等于125℃，且小于或等于135℃。
S14、请参阅图20，对光刻胶层190进行曝光显影，以使得光刻胶层190图案化。
S15、请参阅图21，基于图案化的光刻胶层190对初始导电层130’进行刻蚀，以形成导电层130。
在一些示例中，光刻胶层190包括正性光刻胶。请参阅图20，在步骤S14 中，对光刻胶层190曝光处理后，受到光线照射的光刻胶层190(可参阅图19)被去除，进而可以使得光刻胶层190图案化，形成多条胶线190’。
其中，曝光显影后，胶线190’的截面呈正梯形，即胶线190’沿着第一方向I1线宽逐渐减小，如图13所示，箭头I1所指的方向为第一方向。箭头I2所指的方向为胶线190’的线宽的方向。其中，衬底120指向初始导电层130’的方向即为第一方向I1。在步骤S15中所形成的导电层130包括多条导电线110，导电线110的截面呈正梯形。
其中，在步骤S13中，指定温度越大，光刻胶层190的流动性越大，曝光显影后，如图20所示，胶线190’的侧面1901与底面1902之间夹角H3越小，其中，胶线190’的底面1902指的是胶线190’朝向衬底120的一个表面。而侧面1901与底面1902连接。
在步骤S15中，会沿着胶线190’的侧面1901对初始导电层130’进行刻蚀，因此，请参阅图21，在步骤S15中所形成的导电线110的侧表面1103与衬底120之间的夹角H2与H3大致相等。
在本公开的一些实施例中，指定温度大于或等于125℃，且小于或等于135℃，进而可以避免指定温度过大(例如大于135℃)，从而可以使得光刻胶层190的流动性较大，进而使得曝光显影后，胶线190’的侧面1901与底面1902之间夹角H3较小，从而使得导电线110的侧表面1103与衬底120之间的夹角H2较小，从而可以使得保护层140对导电线110的覆盖性较好，因此，导电线110不容易裸露，可以减少异常生长现象。
此外，导电线110的侧表面1103与衬底120之间的夹角H2与主表面1102与侧表面1103之间的夹角H1互补，即H1+H2＝180°。因此，H2越小，H1越大。因此，通过使得指定温度小于或等于135℃，可以使得H1具有较大值，导电线110的边缘不容易产生段差结构，因此，保护层140对导电线110的边缘的覆盖性较好，导电线110的边缘不容易裸露，进而可以减少异常生长现象。
除此此外，还可以避免指定温度过小(例如小于125℃)，导致光刻胶层190的流动性过大，工艺难度较大。
在一些示例中，指定温度等于130℃。
在一些示例中，在步骤S15中所形成的导电线110的主表面1102与侧表面1103之间的夹角H1大于或等于105°，且小于或等于145°。
此外，光刻胶层190的厚度越大，侧表面1103与衬底120之间的夹角H2越大。示例性的，光刻胶层190的厚度为7μm时，H2大约为70°；当光 刻胶层190的厚度为3～4μm时，H2大约为55°；当光刻胶层190的厚度为2μm时，H2大约为40°。
此外，在步骤S15后，还包括步骤S16、去除光刻胶层190。
在步骤S16后，则可以执行步骤S2。
在一些实施例中，在导电层130远离衬底120的一侧形成保护层140的步骤中，通过化学气相淀积(英文全称：Chemical Vapor Deposition，简称：CVD)工艺形成保护层140。
其中，采用化学气相淀积工艺所形成保护层140的致密性较高，因此，可以提高保护层140对导电层130的覆盖性，进而可以减少导电层130裸露，从而可以减少异常生长现象。
在其他的一些实施例中，还可以通过物理气相沉积工艺(英文全称：Physical Vapor Deposition，简称：PVD)形成保护层140。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种布线基板，包括：
    衬底；
    导电层，位于所述衬底的一侧，所述导电层中包括多个焊盘组，一个焊盘组包括多个导电焊盘；
    保护层，位于所述导电层远离所述衬底的一侧，所述保护层中包括多个开口；所述导电层暴露于所述开口的部分为所述导电焊盘；
    其中，所述导电焊盘在平行于所述衬底的方向上的最大尺寸，大于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的1.5倍，且小于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
  2. 根据权利要求1所述的布线基板，其中，
    所述导电焊盘在平行于所述衬底的方向上的最大尺寸，为该导电焊盘与相邻的导电焊盘之间的距离的0.5～5倍。
  3. 根据权利要求1或2所述的布线基板，其中，
    所述导电焊盘在平行于所述衬底的方向上的最大尺寸大于或等于105μm，且小于或等于350μm。
  4. 根据权利要求1～3中任一项所述的布线基板，其中，
    所述导电焊盘的面积大于或等于5000μm 2，且小于或等于55000μm 2。
  5. 根据权利要求1～4中任一项所述的布线基板，其中，
    在同一个所述焊盘组中，相邻的两个导电焊盘之间的距离，大于或等于70μm，且小于或等于214μm。
  6. 根据权利要求1～5中任一项所述的布线基板，其中，
    所述导电层中包括多条导电线，导电线暴露于所述开口的部分为所述导电焊盘；
    所述导电线包括主表面以及与所述主表面相连的侧表面，其中，所述主表面为所述导电线背离所述衬底的一个表面；
    所述主表面与所述侧表面之间的夹角大于或等于105°，且小于或等于145°。
  7. 根据权利要求1～6中任一项所述的布线基板，其中，
    所述导电层中包括多条导电线，导电线暴露于所述开口的部分为所述导电焊盘；
    所述导电线包括主表面以及与所述主表面相连的多个侧表面，其中，所述主表面为所述导电线背离所述衬底的一个表面；
    所述多个侧表面中与所述导电线的导电焊盘距离较短的至少两个侧表面为第一侧表面；两个所述第一侧表面之间通过曲面连接。
  8. 根据权利要求7所述的布线基板，其中，
    所述曲面在所述衬底上的正投影为第一圆角，所述第一圆角的半径大于或等于20μm，且小于或等于30μm。
  9. 根据权利要求1～8中任一项所述的布线基板，其中，
    所述布线基板包括多个器件区；
    所述多个焊盘组包括位于任一个器件区中的多个第一焊盘组和一个第二焊盘组；其中，所述第一焊盘组包括间隔设置的第一极焊盘和第二极焊盘；所述第二焊盘组至少包括间隔设置的电源焊盘、接地焊盘、地址焊盘和输出焊盘；
    所述布线基板还包括源电压线和驱动电压线；
    在同一个所述器件区内：所述电源焊盘电连接于所述源电压线；所述地址焊盘与另一个所述器件区内的输出焊盘电连接；所述多个第一焊盘组中，第一个第一焊盘组中的第一极焊盘与所述驱动电压线电连接，上一个第一焊盘组中的第二极焊盘与下一个第一焊盘组中的第一极焊盘电连接，最后一个第一焊盘组的第二极焊盘与所述输出焊盘电连接；
    其中，至少第一个第一焊盘组中的第一极焊盘、所述电源焊盘和所述接地焊盘中的至少一个，在平行于所述衬底的方向上的最大尺寸，小于或等于该焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
  10. 根据权利要求1～8中任一项所述的布线基板，其中，
    所述布线基板包括多个子器件区和一个控制区；
    所述多个焊盘组包括位于任一个子器件区中的多个第一焊盘组，所述第一焊盘组包括间隔设置的第一极焊盘和第二极焊盘；
    所述多个焊盘组还包括位于所述控制区内的第二焊盘组；所述第二焊盘组包括电源焊盘、接地焊盘、地址焊盘和输出焊盘；
    所述布线基板还包括源电压线和驱动电压线；
    所述电源焊盘电连接于所述源电压线；
    在同一个所述子器件区内：所述多个第一焊盘组中，第一个第一焊盘组中的第一极焊盘与所述驱动电压线电连接，上一个第一焊盘组中的第二极焊盘与下一个第一焊盘组中的第一极焊盘电连接，最后一个第一焊盘组的第二极焊盘与所述输出焊盘电连接；
    其中，至少第一个第一焊盘组中的第一极焊盘，在平行于所述衬底的方 向上的最大尺寸，小于或等于该第一极焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
  11. 根据权利要求7～10中任一项所述的布线基板，其中，
    所述导电层的数量为两个；
    第一个所述导电层位于所述衬底的一侧，部分所述导电线位于所述第一个所述导电层中；
    第二个所述导电层位于所述第一所述导电层远离所述衬底的一侧，另一部分所述导电线位于第二个所述导电层中；
    其中，第一个所述导电层中的一条导电线与位于第二个所述导电层中的至少一条导电线通过过孔连接，位于第二个所述导电层中的导电线暴露于所述开口的部分为所述导电焊盘。
  12. 根据权利要求1～11中任一项所述的布线基板，还包括：
    氧化防护层，覆盖于所述导电焊盘远离所述衬底的一侧；
    导电功能层，覆盖于所述氧化防护部远离所述衬底的一侧。
  13. 一种背板，包括：
    多个功能元件；
    至少一个驱动芯片；
    权利要求1～12中任一项所述的布线基板，所述布线基板中的多个焊盘组包括第一焊盘组和第二焊盘组；所述第一焊盘组与所述功能元件连接，所述第二焊盘组与所述驱动芯片连接。
  14. 一种显示装置，包括：
    背光模组，所述背光模组为权利要求13所述的背板，所述功能元件包括发光二极管；
    液晶显示面板，位于所述背光模组的出光侧。
  15. 一种显示装置，包括：
    显示面板，所述显示面板包括如权利要求13所述的背板。
  16. 一种布线基板的制备方法，包括：
    在衬底上形成导电层，其中，所述导电层中包括多个焊盘组，一个焊盘组包括多个导电焊盘；
    在所述导电层远离所述衬底的一侧形成保护层，并在所述保护层上形成开口，其中，所述导电层暴露于所述开口的部分为所述导电焊盘；所述导电焊盘在平行于所述衬底的方向上的最大尺寸，小于或等于所述导电焊盘的边缘到所述导电层的边缘之间的最小距离的30倍。
  17. 根据权利要求16所述的布线基板的制备方法，其中，
    在所述在衬底上形成导电层的步骤，包括：
    在所述衬底上沉积导电材料，以形成初始导电层；
    在所述初始导电层远离所述衬底的一侧形成光刻胶层；
    在指定温度下，烘烤所述光刻胶层，其中，所述指定温度大于或等于125℃，且小于或等于135℃；
    对所述光刻胶层进行曝光显影，以使得所述光刻胶层图案化；
    基于图案化的光刻胶层对所述初始导电层进行刻蚀，以形成所述导电层。
  18. 根据权利要求16或17所述的布线基板的制备方法，其中，
    所述在所述导电层远离所述衬底的一侧形成保护层的步骤中，通过化学气相淀积工艺形成所述保护层。
PCT/CN2022/096478 2022-05-31 2022-05-31 布线基板及制备方法、背板、显示装置 WO2023230923A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024858A (ja) * 2004-07-09 2006-01-26 Audio Technica Corp プリント配線板の製造方法およびプリント配線板
US20120247823A1 (en) * 2011-03-31 2012-10-04 Ibiden Co., Ltd. Package-substrate-mounting printed wiring board and method for manufacturing the same
CN205946344U (zh) * 2016-08-23 2017-02-08 合肥鑫晟光电科技有限公司 一种测试点结构及pcb板
CN108990266A (zh) * 2018-09-21 2018-12-11 郑州云海信息技术有限公司 一种pcb板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006024858A (ja) * 2004-07-09 2006-01-26 Audio Technica Corp プリント配線板の製造方法およびプリント配線板
US20120247823A1 (en) * 2011-03-31 2012-10-04 Ibiden Co., Ltd. Package-substrate-mounting printed wiring board and method for manufacturing the same
CN205946344U (zh) * 2016-08-23 2017-02-08 合肥鑫晟光电科技有限公司 一种测试点结构及pcb板
CN108990266A (zh) * 2018-09-21 2018-12-11 郑州云海信息技术有限公司 一种pcb板

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