WO2021248555A1 - 薄膜晶体管、阵列基板及其制造方法 - Google Patents

薄膜晶体管、阵列基板及其制造方法 Download PDF

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Publication number
WO2021248555A1
WO2021248555A1 PCT/CN2020/097537 CN2020097537W WO2021248555A1 WO 2021248555 A1 WO2021248555 A1 WO 2021248555A1 CN 2020097537 W CN2020097537 W CN 2020097537W WO 2021248555 A1 WO2021248555 A1 WO 2021248555A1
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Prior art keywords
layer
hole
contact
active layer
interlayer insulating
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PCT/CN2020/097537
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English (en)
French (fr)
Inventor
龚吉祥
张毅先
鲜于文旭
Original Assignee
武汉华星光电半导体显示技术有限公司
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Priority to US16/978,786 priority Critical patent/US11817462B2/en
Publication of WO2021248555A1 publication Critical patent/WO2021248555A1/zh
Priority to US18/379,195 priority patent/US20240038787A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield

Definitions

  • This application relates to the field of display, and in particular to a thin film transistor, an array substrate and a manufacturing method thereof.
  • LTPS LTPS Low Temperature Poly-silicon
  • TFT film transistor
  • LTPO low temperature polycrystalline oxide
  • LTPO combines the advantages of both LTPS and metal oxides (such as indium gallium zinc oxide) to form a solution with fast response speed and low power consumption.
  • metal oxides such as indium gallium zinc oxide
  • the purpose of the present application is to provide a method for manufacturing an array substrate, an array substrate, and a thin film transistor that can reduce the use of photomasks, is simple to manufacture, and has low cost.
  • the application provides a thin film transistor, which includes:
  • An active layer corresponding to the gate arrangement
  • the source electrode and the drain electrode are arranged at both ends of the active layer and electrically connected to the active layer;
  • An interlayer insulating layer is arranged between the active layer and the source and drain electrodes, stepped contact holes are opened in the interlayer insulating layer, and the source and drain electrodes are respectively filled in The contact hole is electrically connected to the active layer.
  • the contact hole is composed of a first contact through hole and a second contact through hole that are communicated with each other, and the first contact through hole is located at a distance from the second contact through hole to the active layer.
  • the aperture of the first contact through hole is larger than the second contact through hole, the first contact through hole has a first smooth curved surface at one end away from the active layer, and the second contact through hole is far away from the One end of the active layer has a second smooth curved surface.
  • the second contact via extends to the active layer.
  • the thin film transistor further includes a light shielding layer disposed under the active layer and a buffer layer disposed between the light shielding layer and the active layer, and the second contact through hole It penetrates the active layer and extends into the buffer layer.
  • the present application provides an array substrate, which includes: a substrate and a first thin film transistor and a second thin film transistor disposed on the substrate; wherein the first thin film transistor includes:
  • the first active layer is arranged corresponding to the first gate
  • a first source electrode and a first drain electrode are arranged at both ends of the first active layer and electrically connected to the first active layer;
  • the first interlayer insulating layer is disposed between the first active layer and the first source and first drain electrodes, and stepped contact holes are opened in the first interlayer insulating layer, the The first source electrode and the first drain electrode are respectively filled in the contact hole and electrically connected to the first active layer;
  • the second thin film transistor includes:
  • a second active layer corresponding to the second gate, and located on the side of the second active layer away from the substrate;
  • a second source electrode and a second drain electrode are arranged at both ends of the second active layer and electrically connected to the second active layer;
  • the second interlayer insulating layer is disposed between the second active layer and the first source and first drain,
  • the first drain and the second source are electrically connected through a first connecting metal layer.
  • the array substrate further includes a light-shielding layer disposed between the substrate and the first thin film transistor, and the first source electrode and the light-shielding layer are electrically connected through a second connecting metal layer. connect.
  • the material of the first active layer is low-temperature polysilicon
  • the material of the second active layer is a metal oxide semiconductor material
  • the contact hole is composed of a first contact through hole and a second contact through hole that communicate with each other, and the first contact through hole is located at the second contact through hole away from the first active
  • the aperture of the first contact through hole is larger than that of the second contact through hole
  • the first contact through hole has a first smooth curved surface at one end away from the first active layer
  • the second contact through An end of the hole away from the active layer has a second smooth curved surface.
  • the second contact via extends to the first active layer.
  • the thin film transistor further includes a light shielding layer disposed under the first active layer and a buffer layer disposed between the light shielding layer and the first active layer, and the first active layer Two contact vias penetrate the active layer and extend into the buffer layer.
  • the present application also provides a manufacturing method of an array substrate, which includes the following steps:
  • a first substrate is provided, wherein the first substrate includes a substrate, a first active layer disposed on the substrate, and a second active layer disposed on the substrate, wherein the first active layer Two active layers are located on the first active layer on the side away from the substrate, a first interlayer insulating layer is provided between the first active layer and the second active layer, and the second has A second interlayer insulating layer is provided on the source layer;
  • a photoresist layer is coated on the first substrate, and the photoresist layer is patterned using a half-tone mask, wherein the photoresist layer is formed at positions corresponding to both ends of the first active layer.
  • the photoresist layer is removed, and a source-drain metal layer is formed on the second interlayer insulating layer.
  • the source-drain metal layer includes a first source, a first drain, a second source, and a second drain.
  • An electrode, a first connection metal layer, the first source electrode and the first drain electrode respectively fill a first contact via hole and the second contact via hole communicating with the first contact via hole,
  • the second source electrode and the second drain electrode are respectively filled with one third contact through hole, and the first drain electrode and the second source electrode are electrically connected through the first connection metal layer.
  • the second contact via extends from the first interlayer insulating layer to the first active layer.
  • the first substrate further includes a first gate metal layer and a first light-shielding layer disposed on the substrate, and the first gate metal layer corresponds to the first active Layer arrangement, the first light-shielding layer is located under the first gate metal layer and the first active layer, the first gate metal layer includes a light-shielding layer connecting electrode, and the light-shielding layer connects the electrode and the first active layer.
  • the first light shielding layer is electrically connected, wherein,
  • a third photoresist layer is formed at a position corresponding to the light-shielding layer connection electrode.
  • the first interlayer insulating layer is etched at the position of the fourth contact via to form a fifth contact via, and the light shielding layer connection electrode is exposed to the fifth contact Through holes,
  • the source-drain metal layer further includes a second connecting metal layer, and the second connecting metal layer
  • the fourth contact through hole and the fifth contact through hole communicating with the fourth contact through hole are filled and electrically connected to the first source electrode.
  • the photoresist layer is a forward photoresist
  • the halftone mask includes a light-transmitting area, a semi-light-transmitting area, and a non-light-transmitting area
  • the light-transmitting area has a light transmittance of 100. %
  • the light transmittance of the semi-transmissive area is 40%-70%
  • the light transmittance of the non-transmissive area is 0%.
  • the material of the first active layer is low-temperature polysilicon
  • the material of the second active layer is a metal oxide semiconductor material
  • the manufacturing method of the array substrate of the present application uses a half-tone mask to form contact vias for electrically connecting the first thin film transistor and the second thin film transistor by using only a one-step photomask process, thereby reducing The photomask manufacturing process improves production efficiency and reduces costs.
  • the array substrate manufactured by the manufacturing method of the array substrate of the present application has smooth arcs at the ports of the first source and the first drain contacting the through holes, which can effectively prevent disconnection due to excessively deep through holes. The line situation occurs.
  • FIG. 1(a)-FIG. 1(g) are step diagrams of the manufacturing method of the array substrate according to the first embodiment of the application.
  • FIG. 2 is a schematic cross-sectional view of a display panel according to a second embodiment of this application.
  • FIG. 3 is a schematic diagram of the contact hole of the display panel in FIG. 2.
  • the first embodiment of the present application provides a manufacturing method of an array substrate, which includes the following steps:
  • the first substrate 100a includes a substrate 10, a first active layer 21 and a first gate metal layer 22 provided on the substrate 10 are provided on the first active layer 21 and the first gate metal layer 22
  • the first interlayer insulating layer 30, the second active layer 41 and the second gate metal layer 42 disposed on the first interlayer insulating layer 30, are disposed on the second active layer 41 and the second gate metal layer 42 on the second interlayer insulating layer 50.
  • the substrate 10 is a transparent substrate, which can be made of flexible materials such as polyimide.
  • the first active layer 21 is disposed on the side of the first gate metal layer 22 close to the substrate 10.
  • a first gate insulating layer is provided between the first active layer 21 and the first gate metal layer 22.
  • the second active layer 41 is disposed on the side of the second gate metal layer 42 close to the substrate 10.
  • a second gate insulating layer is provided between the second active layer 41 and the second gate metal layer 42. Therefore, the thin film transistor to be subsequently formed is a bottom-gate thin film transistor.
  • the type of thin film transistors to be subsequently formed is not limited, and it may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the first gate metal layer 22 is disposed on the side of the first active layer 21 close to the substrate 10.
  • the second gate metal layer 42 is disposed on the side of the second active layer 41 close to the substrate 10.
  • the material of the first active layer 21 is low-temperature polysilicon, for example, N-type doped low-temperature polysilicon.
  • the material of the second active layer 41 is a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO) , Indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium zinc tin oxide (IZTO), indium tin oxide (ITO), etc.
  • the first gate metal layer 22 includes a first gate 221, a second light shielding layer 222 and a light shielding layer connection electrode 223.
  • the first gate electrode 221 is provided corresponding to the first active layer 21.
  • the second light-shielding layer 222 and the light-shielding layer connection electrode 223 are respectively located on both sides of the first gate 221.
  • the second gate metal layer 42 includes a second gate 422.
  • the second gate electrode 422 is provided corresponding to the second active layer 41.
  • the second light shielding layer 222 is used to shield the second gate 422 from light.
  • the first substrate 100a further includes a first light-shielding layer 60 disposed on the substrate 10.
  • the first light-shielding layer 60 is located under the first gate metal layer 22 and the first active layer 21, and the light-shielding layer connection electrode 223 is provided by The through holes in the first gate light shielding layer and the buffer layer are electrically connected to the first light shielding layer 60.
  • the first light shielding layer 60 is used to shield the first gate 221 from light. It can be understood that a buffer layer or the like may also be provided between the substrate 10 and the first light-shielding layer 60.
  • the materials of the first gate metal layer 22, the second gate metal layer 42 and the first light shielding layer 60 may be, for example, tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti) , Copper niobium (CuNb) alloy, etc., can also be, for example, a laminate of copper (Cu) and molybdenum (Mo), a laminate of copper (Cu) and molybdenum-titanium (MoTi) alloys, copper (Cu) and titanium (Ti) Laminated layers of aluminum (Al) and molybdenum (Mo), laminated layers of molybdenum (Mo) and tantalum (Ta), laminated layers of molybdenum (Mo) and tungsten (W), molybdenum (Mo)-aluminum ( Al)-molybdenum (Mo) laminates, etc.
  • the materials of the first interlayer insulating layer 30, the second interlayer insulating layer 50, the first gate insulating layer, and the second gate insulating layer may be, for example, SiOx, SiNx, or a stack of SiNx and SiOx, or the like.
  • a photoresist layer 200 is coated on the first substrate 100a, and a halftone mask 300 is used to pattern the photoresist layer 200.
  • the step of patterning includes exposing and developing the photoresist layer 200 using the halftone mask 300.
  • two first through holes 201 are formed on the photoresist layer 200 at positions corresponding to both ends of the first active layer 21.
  • two first through holes 201 are formed on the photoresist layer 200 at positions scheduled to be the source and drain of the first active layer 21.
  • Two first blind holes 202 are formed at the positions of the photoresist layer 200 corresponding to the two ends of the second active layer 41.
  • two first blind holes 202 are formed on the photoresist layer 200 at positions scheduled to be the source and drain of the second active layer 41.
  • the height of the first blind hole 202 accounts for 40%-70% of the thickness of the photoresist layer 300.
  • the third through hole 203 is also formed at the position of the photoresist layer 200 corresponding to the light shielding layer connection electrode 223.
  • the photoresist layer 200 can be a positive photoresist or a negative photoresist. In this embodiment, the photoresist layer 200 may be a positive photoresist layer.
  • the halftone mask 300 includes a light-transmitting area 301, a semi-light-transmitting area 302, and a non-light-transmitting area 303.
  • the light transmittance of the light-transmitting area is 100%.
  • the light transmittance of the semi-transmissive area 302 is 40%-70%, and the light transmittance of the non-transmissive area 303 is 0%.
  • etching is performed at the position of the first through hole 201 to remove the second interlayer insulating layer 50 to form the first contact through hole 51.
  • the first interlayer insulating layer 30 is exposed to the first contact via 51.
  • the second interlayer insulating layer 50 is etched at the position of the third through hole 203 to form the fourth contact through hole 53, wherein the first interlayer insulating layer 30 is exposed to the fourth contact through hole 53.
  • ashing is performed on the patterned photoresist layer 200, so that the first blind hole 202 forms a second through hole 202a.
  • This ashing process uses oxygen or a gas containing oxygen. The ashing process makes the photoresist layer 200 thinner, so that the first blind hole 202 forms the second through hole 202a.
  • etching is performed at the position of the first contact via 51 to remove the first interlayer insulating layer 30 to form the second contact via 31.
  • the second interlayer insulating layer 50 is etched and removed at the position of the second through hole 202 a to form the third contact through hole 52.
  • the first active layer 21 is exposed to the second contact via 31.
  • the second active layer 41 is exposed to the third contact via 52.
  • the first interlayer insulating layer 30 is etched at the position of the fourth contact via 53 to form the fifth contact via 32, and the light shielding layer connection electrode 223 is exposed to the fifth contact via 32.
  • the second contact via 31 exposes the upper surface of the first active layer 21. In another embodiment, the second contact via 31 extends from the first interlayer insulating layer 30 to the first active layer 21. The so-called “extending to the first active layer 21" may pass through a part of the first active layer 21, or may pass through the first active layer 21. The second contact via 31 can also penetrate the first active layer 21 and the buffer layer below it, as long as it is not shorted to the first light shielding layer 60. In other embodiments of the present application, the second contact via 31 penetrates the interlayer insulating layer 30 and the first gate insulating layer, exposing the first active layer 21.
  • the source-drain metal layer 70 includes a first source 71, a first drain 72, a second source 73, a second drain 74, a first connecting metal layer 75 and a second connecting metal layer 76.
  • the first source 71 and the first drain 72 respectively fill a first contact through hole 51 and a second contact through hole 31 communicating with the first contact through hole 51.
  • the source and drain metal layer 70 is electrically connected to the first active layer 21 in the second contact via 31. That is, side contact.
  • the second source 73 and the second drain 74 respectively fill a third contact via 52.
  • the first drain 72 and the second source 73 are electrically connected through the first connecting metal layer 75.
  • the second connection metal layer 76 fills the fourth contact via 53 and the fifth contact via 32 communicating with the fourth contact via 53 and is electrically connected to the first source 71.
  • the first light shielding layer 60 is electrically connected to the first source 71 via the light shielding layer connection electrode 223 and the second connection metal layer 76.
  • the second interlayer insulating layer 50 located at the end of the first contact through hole 51 away from the first interlayer insulating layer 30 includes a first smooth curved surface 50a located at the second
  • the first interlayer insulating layer 30 in the contact through hole 31 close to the end of the second interlayer insulating layer 50 includes a second smooth curved surface 30a.
  • the first smooth curved surface 50a and the second smooth curved surface 30a have smooth arcs, which are not obtuse-angled morphologies generated by two etchings. This smooth arc can ensure that when the source and drain metal layer 70 covers the first contact via 51 and the second contact via 31, it can effectively prevent the occurrence of disconnection due to the excessive depth of the via.
  • the array substrate 100 further includes a third active layer disposed on the second interlayer insulating layer.
  • a fourth interlayer insulating layer is provided on the third active layer.
  • the array substrate 100 can be manufactured in the same manner. Specifically, a second semi-transmissive area is added to the half-tone mask, and the light transmittance of the semi-transmissive area is lower than the light-transmitting area 302 of the plate.
  • the materials of the first active layer 21 and the second active layer 41 are not limited, as long as the first active layer 21 and the second active layer 41 are different from the array substrate 100.
  • the array substrate manufacturing method of the present application is used to connect the first thin film transistor and the second thin film transistor.
  • the second embodiment of the present application further provides a display panel 1, which includes an array substrate 100 and a light emitting part 200 disposed on the array substrate 100.
  • the array substrate 100 can be manufactured using the manufacturing method of the first embodiment.
  • the array substrate 100 includes a substrate 10 and a first thin film transistor T1 and a second thin film transistor T2 disposed on the substrate 10.
  • the first thin film transistor T1 is located on the side of the second thin film transistor T2 close to the substrate 10.
  • the substrate 10 is a transparent substrate, which can be made of flexible materials such as polyimide.
  • the first thin film transistor T1 includes a first gate 221, a first active layer 21, a first source 71, a first drain 72, and a first interlayer insulating layer 30.
  • the first active layer 21 is provided corresponding to the first gate 221.
  • a first gate insulating layer is also provided between the first gate 221 and the first active layer 21.
  • the first source 71 and the first drain 72 are disposed at both ends of the first active layer 21 and are electrically connected to the first active layer 21.
  • the first interlayer insulating layer 30 is disposed between the first active layer 21 and the first source 71 and the first drain 72. Stepped contact holes 30a are opened in the first interlayer insulating layer 30.
  • the first source 71 and the first drain 72 are respectively filled in the contact hole 30 a and electrically connected to the first active layer 21.
  • the contact hole 30a is composed of a first contact through hole 51 and a second contact through hole 31 that communicate with each other.
  • the first contact via 51 is located on the side of the second contact via 31 away from the first active layer 21.
  • the hole diameter of the first contact through hole 51 is larger than that of the second contact through hole 31.
  • the first contact via 51 is formed in the second interlayer insulating layer 50 at positions corresponding to both ends of the first active layer 30.
  • the second contact via 31 is formed in the first interlayer insulating layer 30.
  • the first active layer 21 is exposed to the second contact via 31.
  • the second through hole 51 extends to the first active layer 51.
  • the first source 71 and the first drain 72 respectively fill a first contact through hole 51 and a second contact through hole 31 communicating with the first contact through hole 51.
  • the source and drain metal layer 70 is electrically connected to the first active layer 21 in the second contact via 31. That is, side contact.
  • first smooth curved surface 51 a One end of the first through hole 31 away from the first active layer 21 has a first smooth curved surface 51 a.
  • the second contact through hole 31 has a second smooth curved surface 31 a away from the first active layer 21.
  • the first smooth curved surface 50a and the second smooth curved surface 30a have smooth arcs, which are not obtuse-angled morphologies generated by two etchings. This smooth arc can ensure that when the source and drain metal layer 70 covers the first contact via 51 and the second contact via 31, it can effectively prevent the occurrence of disconnection due to the excessive depth of the via.
  • the first thin film transistor T1 further includes a first light shielding layer 60 disposed between the substrate 10 and the first thin film transistor T1, and a first light shielding layer 60 disposed between the first light shielding layer 60 and the first active layer 21. Buffer layer 80.
  • the first light shielding layer 60 is used to shield the first gate 221 from light.
  • the second through hole 51 penetrates the first active layer 51 and extends into the buffer layer 80.
  • the first source 71 and the first light shielding layer 60 are electrically connected through the second connecting metal layer 76.
  • the array substrate 100 further includes a light-shielding layer connection electrode 223 provided on the same layer as the first gate electrode 221.
  • the first light shielding layer 60 is electrically connected to the first source 71 via the light shielding layer connection electrode 223 and the second connection metal layer 76. As a result, the electric field caused by the ions under the low-temperature polysilicon can be shielded, so that the electrical properties of the thin film transistor are more stable.
  • the second thin film transistor T2 is disposed on the first interlayer insulating layer 30.
  • the second thin film transistor T2 includes a second gate 422, a second active layer 41, a second source 73, a second drain 74, and a second interlayer insulating layer 50.
  • the second active layer 41 is disposed corresponding to the second gate 422 and is located on the side of the second active layer 41 away from the substrate 10.
  • a second gate insulating layer is also provided between the second gate 422 and the second active layer 41.
  • the second source 73 and the second drain 74 are disposed at both ends of the second active layer 41 and are electrically connected to the second active layer 41.
  • the second interlayer insulating layer 50 is disposed between the second active layer 41 and the first source 73 and the first drain 74.
  • the first drain 72 and the second source 73 are electrically connected through the first connecting metal layer 75.
  • the array substrate 100 may further include a second light shielding layer 222 between the second thin film transistor T2 and the substrate 10.
  • the second light shielding layer 222 is used to shield the second gate 422 from light.
  • the second light-shielding layer 222 and the light-shielding layer connection electrode 223 are respectively located on both sides of the first gate 221.
  • a third contact via 52 is formed in the second interlayer insulating layer 50 at positions corresponding to both ends of the second active layer 41, and the second active layer 41 Exposed to the third contact via 52.
  • a fourth contact via 53 is formed at a position of the second interlayer insulating layer 50 corresponding to the light shielding layer connection electrode 223.
  • the first interlayer insulating layer 30 is exposed to the fourth contact via 53.
  • a fifth contact through hole 32 is formed in the first interlayer insulating layer 30 at a position corresponding to the fourth contact through hole 53, and the light shielding layer connection electrode 223 is exposed to the fifth contact through hole 32.
  • the fourth contact through hole 53 communicates with the fifth contact through hole 32.
  • the second source 73 and the second drain 74 respectively fill a third contact via 52.
  • the second connection metal layer 76 fills the fourth contact via 53 and the fifth contact via 32 communicating with the fourth contact via 53 and is electrically connected to the first source 71.
  • the first active layer 21 is disposed on the side of the first gate 221 close to the substrate 10.
  • the second active layer 41 is disposed on the side of the second gate 422 close to the substrate 10. That is, the first thin film transistor T1 and the second thin film transistor T2 of this embodiment are both bottom-gate thin film transistors.
  • the type of thin film transistors to be subsequently formed is not limited, and it may be a bottom gate thin film transistor or a top gate thin film transistor.
  • the material of the first active layer 21 is low-temperature polysilicon, for example, N-type doped low-temperature polysilicon.
  • the material of the second active layer 41 is a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO) , Indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), indium zinc tin oxide (IZTO), indium tin oxide (ITO), etc.
  • IGZO indium gallium zinc oxide
  • IGTO indium gallium zinc tin oxide
  • IGZTO indium gallium zinc tin oxide
  • ITO indium tin oxide
  • the plurality of light emitting parts 200 may be arranged in an array.
  • the light emitting part 200 may be, for example, an organic light emitting diode light emitting part or a micro light emitting diode chip or the like.
  • the organic light emitting diode light emitting part 200 may include an anode layer provided on the driving circuit layer 20, and a hole injection layer, a hole transport layer, an electron transport layer, an organic light emitting material layer, an electron injection layer, and Cathode layer.
  • the anode layer is electrically connected to the first drain 71.
  • the manufacturing method of the array substrate of the present application uses a half-tone mask to form contact vias for electrically connecting the first thin film transistor and the second thin film transistor by using only a one-step photomask process, thereby reducing The photomask manufacturing process improves the production efficiency and reduces the cost.
  • the array substrate manufactured by the manufacturing method of the array substrate of the present application has smooth arcs at the ports of the first source and the first drain contacting the through holes, which can effectively prevent disconnection due to excessively deep through holes. The line situation occurs.

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Abstract

本申请提供一种阵列基板的制造方法、阵列基板以及薄膜晶体管。薄膜晶体管包括：栅极；有源层，对应于栅极设置；源极和漏极，设置于有源层两端并与有源层电连接；以及层间绝缘层，设置于有源层与源极和漏极之间，层间绝缘层中开设有台阶状的接触孔，源极和漏极分别填充于接触孔中并与有源层电连接。

Description

薄膜晶体管、阵列基板及其制造方法 技术领域
本申请涉及显示领域，尤其涉及一种薄膜晶体管、阵列基板及其制造方法。
 背景技术
在现有的有机发光二极管（Organic Light-Emitting Diode，OLED）显示器件中，为了实现低功耗，一种主流技术是在驱动薄膜晶体管（Thin film transistor，TFT）和开关薄膜晶体管中采用低温多晶硅（LTPS Low Temperature Poly-silicon，LTPS）作为有源层。但是LTPS的载流子迁移率较大，存在漏电流较高的问题。在此基础上，产生了低温多晶氧化物(Low Temperature Polycrystalline-Si Oxide，LTPO)技术。LTPO结合了LTPS和金属氧化物（如铟镓锌氧化物）两者的优点，形成了一种响应速度快，功耗低的解决方案。然而，LTPO因为同时采用了两种有源层，导致制造过程中所需要的光罩数量增加，制程更为复杂，成本也随之升高。
 技术问题
有鉴于此，本申请目的在于提供一种能够减少光罩的使用，制造简单，成本低的阵列基板的制造方法、阵列基板以及薄膜晶体管。
 技术解决方案
本申请提供一种薄膜晶体管，其包括：
栅极；
有源层，对应于所述栅极设置；
源极和漏极，设置于所述有源层两端并与所述有源层电连接；以及
层间绝缘层，设置于所述有源层与所述源极和所述漏极之间，所述层间绝缘层中开设有台阶状的接触孔，所述源极和漏极分别填充于所述接触孔中并与所述有源层电连接。
在一种实施方式中，所述接触孔由相互连通的第一接触通孔和第二接触通孔构成，所述第一接触通孔位于所述第二接触通孔远离所述有源层一侧，所述第一接触通孔的孔径大于所述第二接触通孔，所述第一接触通孔远离所述有源层一端具有第一光滑曲面，所述第二接触通孔远离所述有源层一端具有第二光滑曲面。
在一种实施方式中，所述第二接触通孔延伸至所述有源层。
在一种实施方式中，所述薄膜晶体管还包括设置于所述有源层下方的遮光层和设置于所述遮光层与所述有源层之间的缓冲层，所述第二接触通孔穿透所述有源层延伸至所述缓冲层中。
本申请提供一种阵列基板，其包括：衬底和设置于所述衬底上的第一薄膜晶体管和第二薄膜晶体管；其中，所述第一薄膜晶体管包括：
第一栅极；
第一有源层，对应于所述第一栅极设置；
第一源极和第一漏极，设置于所述第一有源层两端并与所述第一有源层电连接；以及
第一层间绝缘层，设置于所述第一有源层与所述第一源极和第一漏极之间，所述第一层间绝缘层中开设有台阶状的接触孔，所述第一源极和第一漏极分别填充于所述接触孔中并与所述第一有源层电连接；
所述第二薄膜晶体管包括：
第二栅极；
第二有源层，对应于所述第二栅极设置，且位于所述第二有源层远离所述衬底一侧；
第二源极和第二漏极，设置于所述第二有源层两端并与所述第二有源层电连接；以及
第二层间绝缘层，设置于所述第二有源层与所述第一源极和第一漏极之间，
所述第一漏极与所述第二源极通过第一连接金属层电连接。
在一种实施方式中，所述阵列基板还包括设置于所述衬底与所述第一薄膜晶体管之间的遮光层，所述第一源极与所述遮光层通过第二连接金属层电连接。
在一种实施方式中，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为金属氧化物半导体材料。
在一种实施方式中，所述接触孔由相互连通的第一接触通孔和第二接触通孔构成，所述第一接触通孔位于所述第二接触通孔远离所述第一有源层一侧，所述第一接触通孔的孔径大于所述第二接触通孔，所述第一接触通孔远离所述第一有源层一端具有第一光滑曲面，所述第二接触通孔远离所述有源层一端具有第二光滑曲面。
在一种实施方式中，所述第二接触通孔延伸至所述第一有源层。
在一种实施方式中，所述薄膜晶体管还包括设置于所述第一有源层下方的遮光层和设置于所述遮光层与所述第一有源层之间的缓冲层，所述第二接触通孔穿透所述有源层延伸至所述缓冲层中。
本申请还提供一种阵列基板的制造方法，其包括以下步骤：
提供一第一基板，其中，所述第一基板包括衬底，设置于所述衬底上的第一有源层，设置于所述衬底上的第二有源层，其中，所述第二有源层位于第一有源层位于远离所述衬底一侧，所述第一有源层与所述第二有源层之间设置有第一层间绝缘层，所述第二有源层上设置有第二层间绝缘层；
在所述第一基板上涂布光阻层，使用半色调掩模对所述光阻层进行图案化，其中，在所述光阻层对应于所述第一有源层两端的位置形成第一通孔，在所述光阻层对应于所述第二有源层两端的位置形成第一盲孔；
在所述第一通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第一接触通孔，其中，所述第一层间绝缘层暴露于所述第一接触通孔；
对图案化的所述光阻层进行灰化处理，使所述第一盲孔形成第二通孔；
在所述第一接触通孔的位置进行蚀刻除去所述第一层间绝缘层以形成与所述第一接触通孔相连通的第二接触通孔，在所述第二通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第三接触通孔，其中，所述第一有源层暴露于所述第二接触通孔，所述第二有源层暴露于所述第三接触通孔；
除去所述光阻层，在所述第二层间绝缘层上形成源漏极金属层，所述源漏极金属层包括第一源极、第一漏极、第二源极、第二漏极、第一连接金属层，所述第一源极和所述第一漏极分别填充一个所述第一接触通孔和与该第一接触通孔相连通的所述第二接触通孔，所述第二源极和所述第二漏极分别填充一个所述第三接触通孔，所述第一漏极与所述第二源极通过所述第一连接金属层电连接。
在一种实施方式中，所述第二接触通孔从所述第一层间绝缘层延伸至所述第一有源层。
在一种实施方式中，所述第一基板还包括设置于所述衬底上的第一栅极金属层和第一遮光层，所述第一栅极金属层对应于所述第一有源层设置，所述第一遮光层位于所述第一栅极金属层和所述第一有源层下方，所述第一栅极金属层包括遮光层连接电极，所述遮光层连接电极与所述第一遮光层电连接，其中，
在所述第一基板上涂布光阻层，使用半色调掩模对所述光阻层进行图案化的步骤中，在所述光阻层对应于所述遮光层连接电极的位置形成第三通孔；
在所述第一通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第一接触通孔的步骤中，在所述第三通孔的位置蚀刻所述第二层间绝缘层以形成第四接触通孔，其中，所述第一层间绝缘层暴露于所述第四接触通孔；
在所述第一接触通孔的位置进行蚀刻除去所述第一层间绝缘层以形成第二接触通孔，在所述第二通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第三接触通孔的步骤中，在所述第四接触通孔的位置蚀刻所述第一层间绝缘层以形成第五接触通孔，所述遮光层连接电极暴露于所述第五接触通孔，
在除去所述光阻层，在所述第二层间绝缘层上形成源漏极金属层的步骤中，所述源漏极金属层还包括第二连接金属层，所述第二连接金属层填充所述第四接触通孔和与所述第四接触通孔相连通的第五接触通孔并与所述第一源极电连接。
在一种实施方式中，所述光阻层为正向光阻，所述半色调掩模包括透光区域，半透光区域以及非透光区域，所述透光区域的透光率为100%；所述半透光区域透光率为40%-70%；所述非透光区域的透光率为0%。
在一种实施方式中，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为金属氧化物半导体材料。
 有益效果
相较于现有技术，本申请的阵列基板的制造方法通过使用半色调掩模，仅利用一步光罩制程就形成用于电连接第一薄膜晶体管和第二薄膜晶体管的接触通孔，减少了光罩制程，提高了生产效率，降低了成本。此外，通过本申请的阵列基板的制造方法制造出的阵列基板以的第一源极和第一漏极的接触通孔的端口处拥有平滑的弧度，可以有效防止由于通孔过深而导致断线的情况发生。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1（a）-图1（g）为本申请第一实施方式的阵列基板的制造方法的步骤图。
图2为本申请第二实施方式的显示面板的剖面示意图。
图3为图2中的显示面板的接触孔的示意图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请一并参考图1（a）至图1（g），本申请第一实施方式提供一种阵列基板的制造方法，其包括以下步骤：
S1：请参考图1（a），提供一第一基板100a。其中，第一基板100a包括衬底10，设置于衬底10上的第一有源层21和第一栅极金属层22，设置于第一有源层21和第一栅极金属层22上的第一层间绝缘层30，设置于第一层间绝缘层30上的第二有源层41和第二栅极金属层42，设置于第二有源层41和第二栅极金属层42上的第二层间绝缘层50。
衬底10为透明基板，其可以采用聚酰亚胺等柔性材料。
第一有源层21设置于第一栅极金属层22靠近衬底10一侧。第一有源层21和第一栅极金属层22之间设置有第一栅极绝缘层。第二有源层41设置于第二栅极金属层42靠近衬底10一侧。第二有源层41和第二栅极金属层42之间设置有第二栅极绝缘层。由此，后续形成的薄膜晶体管为底栅型薄膜晶体管。然而，在本申请中，不限定后续形成的薄膜晶体管的类型，可以是底栅型薄膜晶体管，也可以是顶栅型薄膜晶体管。在顶栅型薄膜晶体管中，第一栅极金属层22设置于第一有源层21靠近衬底10一侧。第二栅极金属层42设置于第二有源层41靠近衬底10一侧。
在本实施方式中，第一有源层21的材料为低温多晶硅，例如为N型掺杂的低温多晶硅。第二有源层41的材料为金属氧化物半导体材料，例如铟镓锌氧化物(IGZO)、铟镓锌锡氧化物（IGZTO）、铟锌氧化物（IZO）、镓铟氧化物（IGO）、铟镓锌氧化物(IGZO)、铟镓锡氧化物（IGTO）、铟镓锌锡氧化物（IGZTO）、铟锌锡氧化物（IZTO）、铟锡氧化物（ITO）等。
第一栅极金属层22包括第一栅极221、第二遮光层222以及遮光层连接电极223。第一栅极221对应于第一有源层21设置。第二遮光层222与遮光层连接电极223分别位于第一栅极221两侧。
第二栅极金属层42包括第二栅极422。第二栅极422对应于第二有源层41设置。第二遮光层222用于对第二栅极422进行遮光。
另外，第一基板100a还包括设置于衬底10上的第一遮光层60，第一遮光层60位于第一栅极金属层22和第一有源层21下方，遮光层连接电极223通过设置于第一栅极遮光层与缓冲层中的通孔与第一遮光层60电连接。第一遮光层60用于对第一栅极221进行遮光。可以理解，衬底10与第一遮光层60之间还可以设置缓冲层等。
第一栅极金属层22、第二栅极金属层42以及第一遮光层60的材料例如可以为钽(Ta)、钨(W)、钼(Mo)、铝(Al)、钛（Ti）、铜铌（CuNb）合金等，也可以为例如铜（Cu）和钼(Mo)的叠层、铜（Cu）和钼钛（MoTi）合金的叠层、铜（Cu）和钛（Ti）的叠层、铝（Al）和钼（Mo）的叠层以及钼（Mo）和钽（Ta）的叠层、钼（Mo）和钨(W)的叠层、钼（Mo）-铝(Al)-钼(Mo)的叠层等。
第一层间绝缘层30、第二层间绝缘层50、第一栅极绝缘层和第二栅极绝缘层的材料可以是例如，SiOx、SiNx、或者SiNx和SiOx的层叠体等。
S2：请参考图1（b）至图1（c），在第一基板100a上涂布光阻层200，使用半色调掩模300对光阻层200进行图案化。图案化的步骤包括使用半色调掩模300对光阻层200曝光，显影。通过曝光，显影在光阻层200上对应于第一有源层21两端的位置形成两个第一通孔201。换句话说，在光阻层200上预定为第一有源层21的源漏极的位置形成两个第一通孔201。在光阻层200对应于第二有源层41两端的位置形成两个第一盲孔202。换句话说，在光阻层200上预定为第二有源层41的源漏极的位置形成两个第一盲孔202。第一盲孔202的高度占光阻层300的厚度的40%-70%。
在此步骤中，还在光阻层200对应于遮光层连接电极223的位置形成第三通孔203。
光阻层200可以是正向光阻，也可以是负向光阻。在本实施方式中，光阻层200可以是正向光阻层。半色调掩模300包括透光区域301，半透光区域302以及非透光区域303。透光区域的透光率为100%。半透光区域302透光率为40%-70%，非透光区域303的透光率为0%。
S3：请参考图图1（c）至1（d），在第一通孔201的位置进行蚀刻除去第二层间绝缘层50以形成第一接触通孔51。第一层间绝缘层30暴露于第一接触通孔51。在此步骤中，在第三通孔203的位置蚀刻第二层间绝缘层50以形成第四接触通孔53，其中，第一层间绝缘层30暴露于第四接触通孔53。
S4：请参考图1（d）至1（e），对图案化的光阻层200进行灰化处理，使第一盲孔202形成第二通孔202a。该灰化处理利用氧气或者含有氧气的气体。灰化处理使光阻层200减薄，从而使第一盲孔202形成第二通孔202a。
S5：请参考图1（f），在第一接触通孔51的位置进行蚀刻除去第一层间绝缘层30以形成第二接触通孔31。在第二通孔202a的位置进行蚀刻除去第二层间绝缘层50以形成第三接触通孔52。第一有源层21暴露于第二接触通孔31。第二有源层41暴露于第三接触通孔52。在此步骤中，在第四接触通孔53的位置蚀刻第一层间绝缘层30以形成第五接触通孔32，遮光层连接电极223暴露于第五接触通孔32。
在一个实施方式中，第二接触通孔31暴露出第一有源层21的上表面。在另一个实施方式中，第二接触通孔31从第一层间绝缘层30延伸至第一有源层21。所谓“延伸至第一有源层21”可以是穿过部分第一有源层21，也可以是贯穿第一有源层21。第二接触通孔31还可以贯穿第一有源层21及其下方的缓冲层，只要不与第一遮光层60短接即可。在本申请其他实施方式中，第二接触通孔31贯穿层间绝缘层30以及第一栅极绝缘层，暴露出第一有源层21。
S6：请参考图1（g），除去光阻层200，在第二层间绝缘层50上形成源漏极金属层70以形成第一薄膜晶体管T1和第二薄膜晶体管T2，获得阵列基板100。
源漏极金属层70包括第一源极71、第一漏极72、第二源极73、第二漏极74、第一连接金属层75和第二连接金属层76。第一源极71和第一漏极72分别填充一个第一接触通孔51和与该第一接触通孔51相连通的第二接触通孔31。源漏极金属层70与第一有源层21在第二接触通孔31内电连接。也就是侧边连接（side contact）。第二源极73和第二漏极74分别填充一个第三接触通孔52。第一漏极72与第二源极73通过第一连接金属层75电连接。第二连接金属层76填充第四接触通孔53和与第四接触通孔53相连通的第五接触通孔32并与第一源极71电连接。第一遮光层60经由遮光层连接电极223、第二连接金属层76与第一源极71电连接。由此，能够屏蔽低温多晶硅下层离子带来的电场，使得薄膜晶体管电性更为稳定。
此外，在根据上述方法制造出的阵列基板100中，位于第一接触通孔51内远离第一层间绝缘层30的一端的第二层间绝缘层50包括第一光滑曲面50a，位于第二接触通孔31内靠近第二层间绝缘层50的一端的第一层间绝缘层30包括第二光滑曲面30a。第一光滑曲面50a和第二光滑曲面30a拥有平滑的弧度，并非为两次刻蚀生成的钝角形貌。此平滑的弧度可以保证源漏极金属层70在覆盖该第一接触通孔51和第二接触通孔31时，可以有效防止由于通孔过深而导致断线的情况发生。
在本申请其他实施方式中，阵列基板100还包括设置于所述第二层间绝缘层上的第三有源层。第三有源层上设置有第四层间绝缘层。为了电连接第二有源层与第三有源层，可以使用同样的方式进行阵列基板100的制造。具体地，在半色调掩模上增加一个第二半透光区，该半透光区的透光率小于板透光区302。通过上述蚀刻、灰化、蚀刻的步骤，可以获得第二有源层与第三有源层的接触通孔，并通过源漏极金属层电连接二者。在本申请其他实施方式中，不限定第一有源层21和第二有源层41的材料，只要是第一有源层21和第二有源层41与不同层的阵列基板100均可以使用本申请的阵列基板制造方法来连接第一薄膜晶体管和第二薄膜晶体管。
请参考图2和图3，本申请第二实施方式还提供一种显示面板1，其包括阵列基板100和设置于阵列基板100上的发光部200。
该阵列基板100可以利用第一实施方式的制造方法制造。
阵列基板100包括：衬底10，设置于衬底10上的第一薄膜晶体管T1和第二薄膜晶体管T2。第一薄膜晶体管T1位于第二薄膜晶体管T2靠近衬底10一侧。
衬底10为透明基板，其可以采用聚酰亚胺等柔性材料。
第一薄膜晶体管T1包括第一栅极221、第一有源层21、第一源极71、第一漏极72以及第一层间绝缘层30。第一有源层21对应于第一栅极221设置。第一栅极221与第一有源层21之间还设置有第一栅极绝缘层。第一源极71和第一漏极72设置于第一有源层21两端并与第一有源层21电连接。第一层间绝缘层30设置于第一有源层21与第一源极71和第一漏极72之间。第一层间绝缘层30中开设有台阶状的接触孔30a。第一源极71和第一漏极72分别填充于接触孔30a中并与第一有源层21电连接。接触孔30a由相互连通的第一接触通孔51和第二接触通孔31构成。第一接触通孔51位于第二接触通孔31远离第一有源层21一侧。第一接触通孔51的孔径大于第二接触通孔31。
请一并参考图1（a）至图1（g），第一接触通孔51形成于第二层间绝缘层50中对应于第一有源层30两端的位置。第二接触通孔31形成于第一层间绝缘层30中。第一有源层21暴露于第二接触通孔31。
在一个实施方式中，第二通孔51延伸至第一有源层51。第一源极71和第一漏极72分别填充一个第一接触通孔51和与该第一接触通孔51相连通的第二接触通孔31。源漏极金属层70与第一有源层21在第二接触通孔31内电连接。也就是侧边连接（side contact）。
第一通孔31远离第一有源层21一端具有第一光滑曲面51a。第二接触通孔31远离第一有源层21具有第二光滑曲面31a。第一光滑曲面50a和第二光滑曲面30a拥有平滑的弧度，并非为两次刻蚀生成的钝角形貌。此平滑的弧度可以保证源漏极金属层70在覆盖该第一接触通孔51和第二接触通孔31时，可以有效防止由于通孔过深而导致断线的情况发生。
在一个实施方式中，第一薄膜晶体管T1还包括设置于衬底10与第一薄膜晶体管T1之间的第一遮光层60和设置于第一遮光层60与第一有源层21之间的缓冲层80。第一遮光层60用于对第一栅极221进行遮光。第二通孔51穿透第一有源层51延伸至缓冲层80中。第一源极71与第一遮光层60通过第二连接金属层76电连接。阵列基板100还包括于第一栅极221同层设置的遮光层连接电极223。第一遮光层60经由遮光层连接电极223、第二连接金属层76与第一源极71电连接。由此，能够屏蔽低温多晶硅下层离子带来的电场，使得薄膜晶体管电性更为稳定。
第二薄膜晶体管T2设置于第一层间绝缘层上30。第二薄膜晶体管T2包括第二栅极422、第二有源层41、第二源极73、第二漏极74以及第二层间绝缘层50。第二有源层41对应于第二栅极422设置，且位于第二有源层41远离衬底10一侧。第二栅极422与第二有源层41之间还设置有第二栅极绝缘层。第二源极73和第二漏极74设置于第二有源层41两端并与第二有源层41电连接。第二层间绝缘层50设置于第二有源层41与第一源极73和第一漏极74之间。第一漏极72与第二源极73通过第一连接金属层75电连接。
阵列基板100还可以包括位于第二薄膜晶体管T2与衬底10之间的第二遮光层222。第二遮光层222用于对第二栅极422进行遮光。第二遮光层222与遮光层连接电极223分别位于第一栅极221两侧。
请一并参考图1（a）至图1（g），在第二层间绝缘层50对应于第二有源层41两端的位置形成有第三接触通孔52，第二有源层41暴露于第三接触通孔52。在第二层间绝缘层50对应于遮光层连接电极223的位置形成有第四接触通孔53。第一层间绝缘层30暴露于第四接触通孔53。在第一层间绝缘层30中对应于第四接触通孔53的位置形成有第五接触通孔32，遮光层连接电极223暴露于第五接触通孔32。第四接触通孔53与第五接触通孔32相连通。第二源极73和第二漏极74分别填充一个第三接触通孔52。第二连接金属层76填充第四接触通孔53和与第四接触通孔53相连通的第五接触通孔32并与第一源极71电连接。
第一有源层21设置于第一栅极221靠近衬底10一侧。第二有源层41设置于第二栅极422靠近衬底10一侧。即，本实施方式的第一薄膜晶体管T1和第二薄膜晶体管T2均为底栅型薄膜晶体管。然而，在本申请中，不限定后续形成的薄膜晶体管的类型，可以是底栅型薄膜晶体管，也可以是顶栅型薄膜晶体管。在本实施方式中，第一有源层21的材料为低温多晶硅，例如为N型掺杂的低温多晶硅。第二有源层41的材料为金属氧化物半导体材料，例如铟镓锌氧化物(IGZO)、铟镓锌锡氧化物（IGZTO）、铟锌氧化物（IZO）、镓铟氧化物（IGO）、铟镓锌氧化物(IGZO)、铟镓锡氧化物（IGTO）、铟镓锌锡氧化物（IGZTO）、铟锌锡氧化物（IZTO）、铟锡氧化物（ITO）等。
多个发光部200可以呈阵列排布。发光部200例如可以是有机发光二极管发光部也可以是微发光二极管芯片等。有机发光二极管发光部200可以包括设置于驱动电路层20上的阳极层，依次层叠设置于阳极层上的空穴注入层、空穴传输层、电子传输层、有机发光材料层、电子注入层以及阴极层。阳极层与第一漏极71电连接。
相较于现有技术，本申请的阵列基板的制造方法通过使用半色调掩模，仅利用一步光罩制程就形成用于电连接第一薄膜晶体管和第二薄膜晶体管的接触通孔，减少了光罩制程，提高了生产效率，降低了成本。此外，通过本申请的阵列基板的制造方法制造出的阵列基板以的第一源极和第一漏极的接触通孔的端口处拥有平滑的弧度，可以有效防止由于通孔过深而导致断线的情况发生。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (15)

  1. 一种薄膜晶体管，包括：
    栅极；
    有源层，对应于所述栅极设置；
    源极和漏极，设置于所述有源层两端并与所述有源层电连接；以及
    层间绝缘层，设置于所述有源层与所述源极和所述漏极之间，所述层间绝缘层中开设有台阶状的接触孔，所述源极和漏极分别填充于所述接触孔中并与所述有源层电连接。
  2. 如权利要求1所述的薄膜晶体管，其中，所述接触孔由相互连通的第一接触通孔和第二接触通孔构成，所述第一接触通孔位于所述第二接触通孔远离所述有源层一侧，所述第一接触通孔的孔径大于所述第二接触通孔，所述第一接触通孔远离所述有源层一端具有第一光滑曲面，所述第二接触通孔远离所述有源层一端具有第二光滑曲面。
  3. 如权利要求1所述的薄膜晶体管，其中，所述第二接触通孔延伸至所述有源层。
  4. 如权利要求3所述的薄膜晶体管，其中，所述薄膜晶体管还包括设置于所述有源层下方的遮光层和设置于所述遮光层与所述有源层之间的缓冲层，所述第二接触通孔穿透所述有源层延伸至所述缓冲层中。
  5. 一种阵列基板，包括：衬底和设置于所述衬底上的第一薄膜晶体管和第二薄膜晶体管；其中，所述第一薄膜晶体管包括：
    第一栅极；
    第一有源层，对应于所述第一栅极设置；
    第一源极和第一漏极，设置于所述第一有源层两端并与所述第一有源层电连接；以及
    第一层间绝缘层，设置于所述第一有源层与所述第一源极和第一漏极之间，所述第一层间绝缘层中开设有台阶状的接触孔，所述第一源极和第一漏极分别填充于所述接触孔中并与所述第一有源层电连接；
    所述第二薄膜晶体管包括：
    第二栅极；
    第二有源层，对应于所述第二栅极设置，且位于所述第二有源层远离所述衬底一侧；
    第二源极和第二漏极，设置于所述第二有源层两端并与所述第二有源层电连接；以及
    第二层间绝缘层，设置于所述第二有源层与所述第一源极和第一漏极之间，
    所述第一漏极与所述第二源极通过第一连接金属层电连接。
  6. 如权利要求5所述的阵列基板，其中，所述阵列基板还包括设置于所述衬底与所述第一薄膜晶体管之间的遮光层，所述第一源极与所述遮光层通过第二连接金属层电连接。
  7. 如权利要求5所述的阵列基板，其中，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为金属氧化物半导体材料。
  8. 如权利要求5所述的阵列基板，其中，所述接触孔由相互连通的第一接触通孔和第二接触通孔构成，所述第一接触通孔位于所述第二接触通孔远离所述第一有源层一侧，所述第一接触通孔的孔径大于所述第二接触通孔，所述第一接触通孔远离所述第一有源层一端具有第一光滑曲面，所述第二接触通孔远离所述有源层一端具有第二光滑曲面。
  9. 如权利要求5所述的阵列基板，其中，所述第二接触通孔延伸至所述第一有源层。
  10. 如权利要求9所述的阵列基板，其中，所述薄膜晶体管还包括设置于所述第一有源层下方的遮光层和设置于所述遮光层与所述第一有源层之间的缓冲层，所述第二接触通孔穿透所述有源层延伸至所述缓冲层中。
  11. 一种阵列基板的制造方法，其包括以下步骤：
    提供一第一基板，其中，所述第一基板包括衬底，设置于所述衬底上的第一有源层，设置于所述衬底上的第二有源层，其中，所述第二有源层位于第一有源层位于远离所述衬底一侧，所述第一有源层与所述第二有源层之间设置有第一层间绝缘层，所述第二有源层上设置有第二层间绝缘层；
    在所述第一基板上涂布光阻层，使用半色调掩模对所述光阻层进行图案化，其中，在所述光阻层对应于所述第一有源层两端的位置形成第一通孔，在所述光阻层对应于所述第二有源层两端的位置形成第一盲孔；
    在所述第一通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第一接触通孔，其中，所述第一层间绝缘层暴露于所述第一接触通孔；
    对图案化的所述光阻层进行灰化处理，使所述第一盲孔形成第二通孔；
    在所述第一接触通孔的位置进行蚀刻除去所述第一层间绝缘层以形成与所述第一接触通孔相连通的第二接触通孔，在所述第二通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第三接触通孔，其中，所述第一有源层暴露于所述第二接触通孔，所述第二有源层暴露于所述第三接触通孔；
    除去所述光阻层，在所述第二层间绝缘层上形成源漏极金属层，所述源漏极金属层包括第一源极、第一漏极、第二源极、第二漏极、第一连接金属层，所述第一源极和所述第一漏极分别填充一个所述第一接触通孔和与该第一接触通孔相连通的所述第二接触通孔，所述第二源极和所述第二漏极分别填充一个所述第三接触通孔，所述第一漏极与所述第二源极通过所述第一连接金属层电连接。
  12. 如权利要求11所述的阵列基板的制造方法，其中，所述第二接触通孔从所述第一层间绝缘层延伸至所述第一有源层。
  13. 如权利要求11所述的阵列基板的制造方法，其中，所述第一基板还包括设置于所述衬底上的第一栅极金属层和第一遮光层，所述第一栅极金属层对应于所述第一有源层设置，所述第一遮光层位于所述第一栅极金属层和所述第一有源层下方，所述第一栅极金属层包括遮光层连接电极，所述遮光层连接电极与所述第一遮光层电连接，其中，
    在所述第一基板上涂布光阻层，使用半色调掩模对所述光阻层进行图案化的步骤中，在所述光阻层对应于所述遮光层连接电极的位置形成第三通孔；
    在所述第一通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第一接触通孔的步骤中，在所述第三通孔的位置蚀刻所述第二层间绝缘层以形成第四接触通孔，其中，所述第一层间绝缘层暴露于所述第四接触通孔；
    在所述第一接触通孔的位置进行蚀刻除去所述第一层间绝缘层以形成第二接触通孔，在所述第二通孔的位置进行蚀刻除去所述第二层间绝缘层以形成第三接触通孔的步骤中，在所述第四接触通孔的位置蚀刻所述第一层间绝缘层以形成第五接触通孔，所述遮光层连接电极暴露于所述第五接触通孔，
    在除去所述光阻层，在所述第二层间绝缘层上形成源漏极金属层的步骤中，所述源漏极金属层还包括第二连接金属层，所述第二连接金属层填充所述第四接触通孔和与所述第四接触通孔相连通的第五接触通孔并与所述第一源极电连接。
  14. 如权利要求13所述的阵列基板的制造方法，其中，所述光阻层为正向光阻，所述半色调掩模包括透光区域，半透光区域以及非透光区域，所述透光区域的透光率为100%；所述半透光区域透光率为40%-70%；所述非透光区域的透光率为0%。
  15. 如权利要求11所述的阵列基板的制造方法，其中，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为金属氧化物半导体材料。
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