WO2015085641A1 - 阵列基板及其制作方法及应用该阵列基板的液晶显示面板 - Google Patents

阵列基板及其制作方法及应用该阵列基板的液晶显示面板 Download PDF

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WO2015085641A1
WO2015085641A1 PCT/CN2013/091251 CN2013091251W WO2015085641A1 WO 2015085641 A1 WO2015085641 A1 WO 2015085641A1 CN 2013091251 W CN2013091251 W CN 2013091251W WO 2015085641 A1 WO2015085641 A1 WO 2015085641A1
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Prior art keywords
substrate
thickness
layer
electrode
thin film
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PCT/CN2013/091251
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English (en)
French (fr)
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徐向阳
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深圳市华星光电技术有限公司
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Priority to US14/236,867 priority Critical patent/US9612497B2/en
Publication of WO2015085641A1 publication Critical patent/WO2015085641A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • G02F2202/103—Materials and properties semiconductor a-Si

Definitions

  • the present invention relates to liquid crystal display technology, and more particularly to - and a display panel to which the array substrate is applied.
  • Liquid crystal display has many advantages such as thin body, power saving, no radiation, etc., and has been widely used. With the development of liquid crystal display device industry, its performance is also getting higher and higher, such as High resolution, high brightness, wide viewing angle, low power consumption, etc., and their corresponding technologies have been continuously developed. Most of the liquid crystal display devices on the market are backlight type liquid crystal display devices, which include a liquid crystal display panel and a baddight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, and control the liquid crystal molecules to change direction by applying a driving voltage on the two glass substrates, and refract the light of the backlight module to generate a picture.
  • a liquid crystal display panel comprises a color filter (CF) substrate, a thin film transistor (TFT) substrate, and a liquid crystal (LC) material sandwiched between the color filter substrate and the thin film transistor substrate.
  • the sealant composition the molding process generally includes: front array (Array) process (film, yellow, etching and stripping), middle box (Cell) process (thin film transistor substrate and color filter substrate Fit) and rear module assembly process (drive circuit (IC) is pressed with printed circuit board).
  • liquid crystal display panels on the mainstream market can be divided into three categories, namely TN (twisted nematic) / STN (super twisted nematic), IPS (intraboard switching) ZFFS (edge switching) and VA ( Vertical alignment) type.
  • the edge switching display panel is superior to the twisted nematic display panel in terms of viewing angle, and is superior to the in-panel switching display panel in terms of liquid crystal transmission efficiency, and thus is not only applied on a small device, but also in a medium and large monitor.
  • the scope of application on television sets is also growing.
  • the edge switching type display panel drives the liquid crystal by a fringe electric field phenomenon between a common electrode (COM ITO ) and a pixel electrode (Pixel ITO ).
  • COM ITO common electrode
  • Pixel ITO pixel electrode
  • This change in AC is mainly achieved by the voltage on the common electrode, so the uniformity of the voltage on the common electrode directly affects the display quality of the picture. If the voltage on the common electrode is not uniform, greenish and flicker will appear on the screen.
  • Another object of the present invention is to provide a liquid crystal display panel in which a black matrix is formed on an array substrate, which reduces the parasitic capacitance between the common electrode and the gate line and the data line, and is advantageous for increasing the voltage on the common electrode. It improves the green spot and flicker of the screen and improves the green spot and flicker of the screen.
  • the present invention provides an array substrate, including: a first substrate, a gate line formed on the first substrate, and a data line formed on the first substrate, formed in the first a thin film transistor array on a substrate, a pixel electrode formed on the thin film transistor array, a first passivation layer formed on the pixel electrode and the thin film transistor array, and a black formed on the first passivation layer a matrix, and a common electrode formed on the black matrix and the first passivation layer.
  • the thin film transistor array includes: a * electrode formed on the first substrate, a gate insulating layer formed on the first substrate and the gate, and a semiconductor layer formed on the cabinet insulating layer.
  • a source/drain formed on the semiconductor layer, the gate is formed of chromium, molybdenum, aluminum, and copper, and the germanium-pole insulating layer is deposited from silicon by plasma enhanced chemical vapor deposition.
  • the semiconductor layer is formed by hydrogenated amorphous silicon deposition ⁇ 3 ⁇ 4.
  • the pixel electrode and the common electrode are respectively a transparent conductive layer, and the pixel electrode and the common electrode are both made of indium tin oxide or indium zinc oxide, and the first substrate is a glass substrate or a plastic substrate.
  • the thickness of the gate insulating layer is 2000 ⁇ 5000 ⁇
  • the thickness of the gate is 2000 ⁇ 5000 ⁇
  • the thickness of the semiconductor layer is 2000 ⁇ 4000 ⁇
  • the thickness of the first passivation layer is 100 ⁇ 6000 ⁇ .
  • the thickness of the source/drain is 1000 to 6000 A
  • the thickness of the pixel electrode is 100 to 100 ⁇
  • the thickness of the common electrode is 100 to 100 ⁇
  • the thickness of the black matrix is 0, 2 to: L0 um.
  • Step 2 forming a shed, a line, a data line, and a thin film transistor array on the first substrate;
  • Step 3 forming a pixel electrode on the thin film transistor array;
  • Step 4 depositing a first passivation layer on the pixel electrode, the data line and the thin film transistor array;
  • Step 5 forming a black matrix on the first passivation layer
  • Step 6 Form a common electrode on the black matrix and the first passivation layer.
  • the step 2 includes the following steps:
  • Step 21 forming a first metal layer on the first substrate, and performing a first photolithography process on the first metal layer in a predetermined pattern to form a cabinet and a drain line;
  • Step 4 Form a first passivation layer 38 on the pixel electrode 36, the data line 34, and the thin film transistor array.
  • the first passivation layer 38 has a thickness of 2000 to 5000A.
  • the color filter substrate 50 includes: a second substrate 61, a color filter 62 formed on the second substrate 61, and a second blunt formed on the color filter 62 and the second substrate 61.
  • the common electrode 44 is located above the data line 34 and the gate line, and a black matrix 42 is added between the common electrode 44 and the data line 34 and the gate line, which is advantageous for increasing the distance between them. Further, the parasitic capacitance between the common electrode 44 and the cabinet line and the data line 34 is reduced, which is advantageous for improving the uniformity of the voltage on the common electrode 44.
  • the thickness of each of the other film layers is specifically as follows: the first passivation layer 38 has a thickness of 2000-5000 A, the semiconductor layer 56 has a thickness of 100-6000 A, and the source/drain The thickness of the pixel electrode 36 is ⁇ 00 ⁇ 1000 ⁇ , the thickness of the common electrode 44 is iOO ⁇ iOOOA, and the thickness of the black matrix 42 is 0. 2 ⁇ i, 0um.

Abstract

一种阵列基板，该阵列基板包括：第一基板（32）、形成于第一基板（32）上的栅极线、形成于第一基板（32）上的数据线（34）、形成于第一基板（32）上的薄膜晶体管阵列、形成于薄膜晶体管阵列上的像素电极（36）、形成于像素电极（36）、数据线（34）与薄膜晶体管阵列上的第一钝化层（38）、形成于第一钝化层（38）上的黑色矩阵（42）、以及形成于黑色矩阵（42）与第一钝化层（38）上的公共电极（44）。该阵列基板将黑色矩阵形成于阵列基板上，减小了公共电极与栅极线、数据线之间的寄生电容，有利于提高公共电极上电压的均匀性。

Description

本发明涉及液晶显示技术 尤其涉及- 及应用该阵列基板的显示面板。
液晶显示装置 ( Liquid Crystal Display, LCD )具有机身薄、 省电、 无 辐射等众多优点， 得到了广泛的应用， 并随着液晶显示装置产业的发展， 其要求性能也越来越高， 如高分辨率、 高亮度、 广视角、 低功耗等性能， 且其相应的技术也持续被开发出来。 现有市场上的液晶显示装置大部分为 背光型液晶显示装置， 其包括液晶显示面板及背光模组 （baddight module ) 。 液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液 晶分子， 通过在两片玻璃基板上施加驱动电压来控制液晶分子改变方向， 将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩色滤光膜（Color Filter, CF )基板、 薄膜晶体 管 （Thin Film Transistor, TFT)基板、 夹于彩色滤光膜基板与薄膜晶体管基 板之间的液晶 ( Liquid Crystal , LC )材料及密封胶框 ( Sealant )组成， 其 成型工艺一般包括： 前段阵列 （Array ) 制程 （薄膜、 黄光、 蚀刻及剥 膜） 、 中段成盒 （Cell ) 制程 （薄膜晶体管基板与彩色滤光膜基板贴合） 及后段模组组装制程（驱动电路（IC ) 与印刷电路板压合） 。
就目前主流市场上的液晶显示面板而言， 可分为三大类， 分别是 TN (扭曲向列） /STN (超级扭曲向列） ， IPS (板内切换） ZFFS (边缘切 换）及 VA (垂直配向） 型。 边缘切换显示面板在视角方面比扭曲向列显 示面板优秀, 以及在液晶透过效率方面比板内切换显示面板优秀， 因此不 仅在小型设备上的应用 （application ) , 在中、 大型的监视器、 电视机上 的适用范围也越来越广。
边缘切换型显示面板是利用公共电极（COM ITO )和像素电极（Pixel ITO ) 间的边缘电场 （ fringe electric field )现象驱动液晶。 为了消除直流残 留带来的残影， 一般采用交流模式进行驱动。 这种交流变化主要是通过公 共电极上的电压来实现的， 因此公共电极上电压的均匀性直接影响到画面 的显示质量。 如果公共电极上的电压不均匀， 屏幕画面就会出现绿斑 ( Greenish )及闪烁 ( Flicker )等现象。 发明内容
本发明的目的在于提供一种阵列基板， 利用形成其上的黑色矩阵来减 小公共电极与栅极线、 数据线之间的寄生电容， 有利于提高公共电极上电 压的均勾性， 及改善了屏幕画面的绿斑及闪烁现象。
本发明的另一目的在于提供一种阵列基板的制作方法， 制作简单快 捷， 利用该方法制作的阵列基板有利于改善液晶显示面板的显示质量。
本发明的又一目的在于提供一种液晶显示面板， 将黑色矩阵形成于阵 列基板上， 减小了公共电极与柵极线、 数据线之闾的寄生电容， 有利于提 高公共电极上电压的均勾性， 及改善了屏幕画面的绿斑及闪烁现象， 改善 了屏幕画面的绿斑及闪烁现象。
为实现上述目的， 本发明提供一种阵列基板， 包括： 一第一基板、 形 成于所述第一基板上的栅极线、 形成于所述第一基板上的数据线、 形成于 所述第一基板上的薄膜晶体管阵列、 形成于所述薄膜晶体管阵列上的像素 电极、 形成于所述像素电极与薄膜晶体管阵列上的第一钝化层、 形成于所 述第一钝化层上的黑色矩阵、 以及形成于所述黑色矩阵与第一钝化层上的 公共电极。
所述薄膜晶体管阵列包括： 形成于所述第一基板上的 *极、 形成于所 述第一基板与柵极上的栅极绝缘层、 形成于所述櫥极绝缘层上的半导体 层。 形成于所述半导体层上的源 /漏极， 所述柵极由铬、 钼、 铝及铜形成， 所述楣 -极绝缘层通过等离子体增强化学气相沉积法由硅沉积而成， 所述半 导体层由氢化非晶硅沉积 τ¾形成。
所述像素电极与公共电极分别为一透明导电层， 所述像素电极与公共 电极均由氧化铟锡或氧化铟锌制成， 所述第一基板为玻璃基板或塑料基 板。
所述柵极绝缘层的厚度为 2000〜5000Α， 所述栅极的厚度为 2000〜5000Α， 所述半导体层的厚度为 2000〜4000Α , 所述第 - 钝化层的厚 度为 100〜6000Α， 所述源 /漏极的厚度为 1000〜6000A， 所述.像素电极的厚 度为 100〜100θΑ, 所述公共电极的厚度为 100〜100θΑ, 所述黑色矩阵的厚 度为 0,2〜： L0um。
本发明还提供一种阵列基板的制作方法， 包括以下步骤：
步骤 1、 提供 第- 基板；
步骤 2、 在所述第一基板上形成棚 ·极线、 数据线及薄膜晶体管阵列； 步骤 3、 在所述薄膜晶体管阵列上形成像素电极； 步骤 4、 在所述像素电极、 数据线与薄膜晶体管阵列上沉积形成第一 钝化层；
步骤 5、 在所述第一钝化层上形成黑色矩阵；
步骤 6、 在所述黑色矩阵与第一钝化层上形成公共电极。
所述步骤 2包括以下步骤：
步骤 21、 在所述第一基板上形成第一金属层， 并对该第一金属层按预 定图案进行第一光刻制程， 以形成櫥极与櫪极线；
步骤 22、 通过等离子增强化学气相沉积法在所述第一基板及栅极与栅 极线上沉积硅以形成柵极绝缘层；
步骤 23、 通过等离子增强化学气相沉积法在所述柵极绝缘层上沉积氢 化非晶硅以形成半导体层， 并按预定图案对该半导体层进行第二光刻制 程；
步骤 24、 在所述半导体层与栅极绝缘层上形成第二金属层， 并按预定 图案对该第二金属层进行第三光刻制程， 以形成源 /漏极与数据线， 进而形 成薄 ,膜晶 .体管阵歹l。
所述步骤 3 中在所述薄膜晶体管阵列上形成一透明导电层， 并按预定 图案对该透明导电层进行第四光刻制程， 以形成像素电极；
所述步骤 4 中通过等离子增强化学气相沉积法在所述 _素电极、 数据 线与薄膜晶体管阵列上沉积形成一保护膜， 并按预定图案对该保护膜进行 第五光刻制程， 以形成第一钝化层；
所述步骤 5 中通过 覆制程在所述第一钝化层上形成一定厚度的黑色 矩阵， 并对该黑色矩阵进行第六光刻制程；
所述步骤 6 中在所述黑色矩阵与第一钝化层上形成一透明导电层， 并 按预定图案对该透明导电层进行第七光刻制程， 以形成公共电极。
所述第一基板为玻璃基板或塑料基板， 所述柵极绝缘层的厚度为 2000
〜5000_A.， 所述柵极的厚度为 2000〜5000_A.， 所述第一钝化层的厚度为 2000 〜500θΑ， 所述半导体层的厚度为 .00〜6000A， 所述源 /漏极的厚度为 1000~6000A, 所述.像素电极的厚度为 100〜100θΑ， 所述公共电极的厚度为 100〜i000A， 所述黑色矩阵的厚度为 0,2〜！ L0um。
本发明还提供一种液晶显示面板， 包括： 一阵列基板， 一彩色滤光片 基板、 以及密封于阵列基板与彩色滤光片基板之闾的液晶材料； 所述阵列 基板包括: 一第一基板、 形成于所述第一基板上的栅极线、 形成于所述第 一基板上的数据线、 形成于所述第一基板上的薄膜晶体管阵列、 形成于所 述薄膜晶体管阵列上的像素电极、 形成于所述像素电极、 数据线与薄膜晶 体管阵列上的第一钝化层、 形成于所述第一钝化层上的黑色矩阵、 以及形 成于所述黑色矩阵与第一钝化层上的公共电极； 所述彩色滤光片基板包 括： 第二基.板、 形成于所述第二基板上的彩色滤光片、 形成于所述彩色滤 光片与第二基板上的第二钝化层、 以及形成于第二钝化层上的间隔层。
所述薄膜晶体管阵列包括： 形成于所述第一基板上的柵极、 形成于所 述第一基板与柵极上的柵极绝缘层、 形成于所述柵极绝缘层上的半导体 层、 形成于所述半导体层上的源 /漏极， 所述栅极由铬、 4目, 铝及铜形成， 所述栅极绝缘层通过等离子体增强化学气相沉积法由硅沉积而成， 所述半 导体层由氢化非晶硅沉积而形成；
所述像素电极与公共电极分别为一透明导电层， 所述像素电极与公共 电极均由氧化铟锡或氧化铟锌制成， 所述第一基板为玻璃基板或塑料基 板；
所述櫥极绝缘层的厚度为 2000〜5000Α , 所述栅极的厚度为 2000-5000A, 所述半导体层的厚度为 2000'、4000A, 所述第一钝化层的厚 度为 100〜6000A , 所述源 /漏极的厚度为 1000〜6000_A.， 所述像素电极的厚 度为 〗00〜100θΑ, 所述公共电极的厚度为 〗00〜100ί)Α, 所述黑色矩阵的厚 度为 0.2〜1.0um;
所述第二基板为玻璃基板或塑料基板， 所述彩色滤光片包括： 红色滤 光片、 蓝色滤光片及绿色滤光片。
本发明的有益效果： 本发明的阵列基板及其制作方法及应用该阵列基 板的液晶显示面板， 将黑色矩阵形成于阵列基板上， 增大了公共电极与数 据线及櫥极线之间的距离， 进而减小了公共电极与柵极线、 数据线之间的 寄生电容， 有利于提高公共电极上电压的均匀性， 及改善了屏幕画面的绿 斑及闪烁现象， 且该阵列基板制作方法较为简单„
为了能更进一步了解本发明的特征以及技术内容， 请参阔以下有关本 发明的详细说明与附图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 为本发明阵列基板的俯视图；
图 2为图 ί中 A Α的剖面图； 图 3为图 i中 B- B的剖面图；
图 4为本发明阵列基板的制作方法的步骤流程图；
图 5至图 11为本发明阵列基板的制作方法的工艺流程图；
图 2为本发明液晶显示面板的结构示意图。
八 ^ ί进.二步阐述本发明所釆取.的技术手段及.其效果， 以下结合本发明 的优选实施例及其附图进行详 ·细描述.0
请参阅图 1 至图 3， 本发明提供一种阵列基板， 该阵列基板应用于边 缘切换型显示面板中， 其具体包括： 一第一基板 32、 形成于所述第一基板 32上的栅 线 （未图示） 、 形成于所述第一基板 32上的数据线 34、 形成 于所述第一基板 32 上的薄膜晶体管阵列 （未标示） 、 形成于所述薄膜晶 体管阵列上的像素电极 36、 形成于所述像素电极 36、 数据线 34与薄膜晶 体管阵列上的第一钝化层 38、 形成于所述第一钝化层 38 上的黑色矩阵 42. 以及形成于所述黑色矩阵 42与第一钝化层 38上的公共电极 44。 所述 公共电极 44位于所述数据线 34、 栅极线的上面, 且在公共电极 44与数据 线 34、 柵极线之间加入了黑色矩阵 42 , 有利于增大它钔之间的距离， 进 而减小了公共电极 44与栅极线、 数据线 34之间的寄生电容， 有利于提高 公共电极 44上电压的均匀性。
具体的， 所述薄膜晶体管阵列包括： 形成于所述第一基板 32 上的栅 极 52、 形成于所述第一基板 32与楣-极 52上的柵极绝缘层 54、 形成于所 述棚 _极绝缘层 54上的半导体层 56、 形成于所述半导体层 56上的源 /漏极 58。 所述栅极 52 的厚度为 2000-5000Α, 所述栅极绝缘层 54 的厚度为 2000-5000Α, 所述櫪极 52由鉻（ Cr ) 、 1 ( Mo ) , 铝 （ A1 )及铜 （Cu ) 金属形成， 所述栅极绝缘层 54 通过等离子体增强化学气相沉积法由硅 ( Si )沉积而成， 所述半导体层 56由氢化非晶硅（a Si:H )沉积而形成。
所述柵极线由第一金属层的其它非薄膜晶体管阵列部分形成， 所述数 据线 34由第二金属层的其它非薄膜晶体管阵列部分形成。
所述像素电极 36 与公共电极 44 分别为一透明导电层， 在本实施例 中， 所述像素电极 36与公共电极 44均由氧化铟锡或氧化铟锌制成。 所述 第一基板 32为玻璃基^!或塑料基板， 本实施例中， 优选为玻璃基板。
在本实施例中， 其它各膜层的厚度具体如下： 所述第一钝化层 38 的 厚度为 2000〜5000A， 所述半导体层 56的厚度为 100〜6000A， 所述源 /漏极 58的厚度为 1000〜.6000A, 所述像素电极 36的厚度为 100〜 ΟΟθΑ, 所述公 共电极 44的厚度为 iOC 'iOOOA, 所述黑色矩阵 42的厚度为 0。2〜i,0um。 请参阅图 4至图 11， 本发明还提供一种阵列基板的制作方法， 包括以 下步骤：
步骤 1、 提供一第-—基板 32。
所述第一基板 42 为玻璃基板或塑料基板， 本实施例中， 优选为玻璃 基板。
步骤 2、 在所述第一基板 42上形成栅极线（未图示） 、 数据线 34及 薄膜晶体管阵列 （未标示） 。
该步骤可以细分为以下步骤：
步骤 2】、 在所述第一基板 42 上形成第一金属层， 并对该第一金属层 按预定图案进行第一光刻制程， 以形成栅极 52与棚 ·极线。
具体的， 第一光刻制程包括： 涂布、 曝光、 显影、 蝕刻、 剥离等制 程， 其中蚀刻是采用掩膜板的湿法蚀刻。
所述櫪极. 52的厚度为 2000〜5000A„
步骤 22、 通过等离子增强化学气相沉积法 （PECVD )在所述第一基 板 32及楣极 52与栅极线上沉积硅以形成柵极绝缘层 54。
所述櫥极绝缘层的厚度为 2000〜4000A
步骤 23、 通过等离子增强化学气相沉积法在所述栅极绝缘层 54 上沉 积氢化非晶硅以形成半导体层 56, 并按预定图案对该半导体层 56进行第 二光刻制程。
第二光刻制程包括： 涂布、 曝光、 显影、 蚀刻、 剥离等制程， 其中蚀 刻为千法独刻。
所述半导体层 56的厚度为 ί00〜6000Α。
步骤 24、 在所述半导体层 56与栅极绝缘层 54上形成第二金属层， 并 按预定图案对该第二金属层进行第三光刻制程， 以形成源 Ζ漏极 58 与数据 线 34, 进而形成薄膜晶体管阵列。
第三光刻制程包括： 涂布、 曝光、 显影、 蚀刻、 剥离等制程， 其中蚀 刻为湿法独刻。
所述源 /漏极 58的厚度为 1000〜6000Α。
步骤 3、 在所述薄膜晶体管阵列上形成像素电极 36。
在所述薄膜晶体管阵列 （源 /漏极 58与柵极绝缘层 54 )上形成一透明 导电层， 并按预定图案对该透明导电层进行第四光刻制程， 以形成像素电 极 36。 其中， 第四光刻制程包括： 涂布、 曝光、 显影、 蚀刻、 剥离等制 程， 其中蚀刻为采用掩莫板的湿法蚀刻。 所述.像素电极 36的厚度为 100〜1000Α。
步骤 4、 在所述像素电极 36、 数据线 34 与薄膜晶体管阵列上沉积形 成第一钝化层 38。
通过等离子增强化学气相沉积法在所述像素电极 36、 数据线 34与薄 膜晶体管阵列上沉积形成一保护膜， 并按预定图案对该保护膜进行第五光 刻制程， 以形成第一钝化层 38。 其中， 第五光刻制程包括： 涂布、 曝光、 显影、 蚀刻、 剥离等制程， 其中蚀刻为千法蚀刻或湿法蚀刻。
所述第一钝化层 38的厚度为 2000〜5000A。
步骤 5、 在所述第一钝化层 38形成黑色矩阵 42。
通过涂覆制程在所述第一钝化层 38形成一定厚度的黑色矩阵 42， 并 对该黑色矩阵 42 进行第六光刻制程。 其中， 所述黑色矩阵 42 的厚度为 0.2〜'i .0um。
步骤 6、 在所述黑色矩阵 42与第一钝化层 38上形成公共电极 44„ 在所述黑色矩阵 42与第一钝化层 38上形成一透明导电层， 并按预定 图案对该透明导电层进行第七光刻制程， 以形成公共电极 44。 其中， 所述 公共电极 44的厚度为 100〜100θΑ。
请参阅图 12 , 本发明还提供一种液晶显示面板， 该液晶显示面板为边 缘切换型显示面板， 具体包括： 一阵列基板 30、 一彩色滤光片基板 50、 以及密封于阵列基板 30与彩色滤光片基板 50之间的液晶材料 60; 所述阵 列基板 30包括: 一第一基板 32、 形成于所述第一基板 32上的栅极线（未 图示） 、 形成于所述第一基板 32上的数据线 34、 形成于所述第一基板 32 上的薄膜晶体管阵列 （未标示） 、 形成于所述薄膜晶体管阵列上的像素电 极 36、 形成于所述像素电极 36、 数据线 34与薄膜晶体管阵列上的第一钝 化层 38、 形成于所述第一钝化层 38上的黑色矩阵 42、 以及形成于所述黑 色矩阵 42与第一钝化层 38上的公共电极 44。 所述彩色滤光片基板 50包 括： 第二基板 61、 形成于所述第二基板 61 上的彩色滤光片 62、 形成于所 述彩色滤光片 62与第二基板 61上的第二钝化层 67、 以及形成于第二钝化 层 67上的间隔层 68。 所述公共电极 44位于所述.数据线 34、 柵极线的上 面， 且在公共电极 44与数据线 34、 柵极线之间加入了黑色矩阵 42， 有利 于增大它们之间的距离， 进而减小了公共电极 44与櫥极线、 数据线 34之 间的寄生电容， 有利于提高公共电极 44上电压的均匀性。
具体的， 所述薄膜晶体管阵列包括： 形成于所述第一基板 32 上的栅 极 52、 形成于所述第一基板 32与楣-极 52上的柵极绝缘层 54、 形成于所 述棚 _极绝缘层 54上的半导体层 56、 形成于所述半导体层 56上的源 /漏极 58 tl 所述栅极 52 的厚度为 2000〜5000Α， 所述柵极绝缘层 54 的厚度为 2000-5000Α, 所述櫪极 52由鉻、 #1、 铝及铜形成， 所述櫥极绝缘层 54通 过等离子体增强化学气相沉积法由硅沉积而成, 所述半导体层 56 由氢化 非晶硅沉积而形成。
所述柵极线由第一金属层的其它非薄膜晶体管阵列部分形成， 所述数 据线 34由第二金属层的其它非薄膜晶体管阵列部分形成。
所述像素电极 36 与公共电极 44 分别为一透明导电层， 在本实施例 中， 所述像素电极 36与公共电极 44均由氧化铟锡或氧化铟锌制成。 所述 第一基板 32为玻璃基板或塑料基板， 本实施例中， 优选为玻璃基板。
在本实施例中， 其它各膜层的厚度具体如下： 所述第一钝化层 38 的 厚度为 2000-5000 A , 所述半导体层 56的厚度为 100-6000 A , 所述源 /漏极 58的厚度为 1000~6000A, 所述像素电极 36的厚度为 Ι 00~1000Α, 所述公 共电极 44的厚度为 iOO〜iOOOA, 所述黑色矩阵 42的厚度为 0。2〜i,0um。
所述第二基板 61为玻璃基板或塑料基板， 所述彩色滤光片 62包括： 红色滤光片 63、 蓝色滤光片 64及绿色滤光片 66。
综上所述， 本发明的阵列基板及其制作方法及应用该阵列基板的液晶 显示面板， 将黑色矩阵形成于阵列基板上， 增大了公共电极与数据线及柵 极线之间的距离， 进而减小了公共电极与槲极线、 数据线之间的寄生电 容， 有利于提高公共电极上电压的均勾性， 及改善了屏幕画面的绿斑及闪
: 以上所述， 对 ^本领域的普通技术 员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求 一种阵列基板， 包括： 一第一基板、 形成于所述第一基板上的楣- 极线、 形成于所述第一基板上的数据线、 形成于所述第一基板上的薄膜晶 体管阵列、 形成于所述薄膜晶体管阵列上的像素电极、 形成于所述像素电 极、 数据线与薄膜晶体管阵列上的第一钝化层、 形成于所述第一钝化层上 的黑色矩阵， 以及形成于所述黑色矩阵与第一钝化层上的公共电极。
2、 如权利要求 1 所述的阵列基板， 其中， 所述薄膜晶体管阵列包 括： 形成于所述第一基板上的栅极、 形成于所述第一基板与栅极上的楣-极 绝缘层、 形成于所述栅极绝缘层上的半导体层、 形成于所述半导体层上的 源 /漏极， 所述柵极由铬、 钼、 铝及铜形成， 所述柵极绝缘层通过等离子体 增强化学气相沉积法由硅沉积而成， 所述半导体层由氢化非晶硅沉积而形 成。
3、 如权利要求 1 所述的阵列基板， 其中， 所述像素电极与公共电极 分别为一透明导电层， 所述像素电极与公共电极均由氧化铟锡或氧化铟锌 制成， 所述第一基板为玻璃基板或塑料基板。
4、 如权利要求 2 所述的阵列基板， 其中， 所述櫥极绝缘层的厚度为 200C 5000A , 所述极极的厚度为 2000〜5000A , 所述半导体层的厚度为 2000- 000A, 所述第 钝化层的厚度为 100〜6000A， 所述源 /漏极的厚度 为 1000 6000A , 所述像素电极的厚度为 100〜100θΑ , 所述公共电极的厚 度为 100〜I ()00A, 所述黑色矩阵的厚度为 0.2〜： L0um。
5、 一种阵列基板的制作方法， 包括以下步骤：
步骤 1、 提供一第一基板；
步骤 2、 在所述第一基板上形成栅极线、 数据线及薄膜晶体管阵列； 步骤 3、 在所述薄膜晶体管阵列上形成像素电极；
步骤 4、 在所述像素电极、 数据线与薄膜晶体管阵列上沉积形成第一 钝化层；
步骤 5、 在所述第一钝化层上形成黑色矩阵；
步骤 6、 在所述黑色矩阵与第一钝化层上形成公共电极。
6、 如权利要求 5 所述的阵列基 的制作方法， 其中， 所述步骤 2 包 括'以下步骤：
步骤 2】、 在所述第一基板上形成第一金属层， 并对该第一金属层按預 定图案进行第一光刻制程， 以形成櫥极与櫥极线； 步骤 22、 通过等离子增强化学气相沉积法在所述第一基板及栅极与栅 极线上沉积硅以形成栅极绝缘层；
步骤 23。 通过等离子增强化学气相沉积法在所述极极绝缘层上沉积氢 化非晶硅以形成半导体层， 并按预定图案对该半导体层进行第二光刻制 程；
步骤 24、 在所述半导体层与柵极绝缘层上形成第二金属层， 并按预定 图案对该第二金属层进行第三光刻制程， 以形成源 /漏极与数据线， 进而形 成薄膜晶体管阵列。
7、 如权利要求 5 所述的阵列基 的制作方法， 其中， 所述步骤 3 中 在所述薄膜晶体管阵列上形成一透明导电层， 并按預定图案对该透明导电 层进行第四光刻制程， 以形成像素电极；
所述步骤 4 中通过等离子增强化学气相沉积法在所述像素电极、 数据 线与薄膜晶体管阵列上沉积形成一保护膜， 并按预定图案对该保护膜进行 第五光刻制程， 以形成第一钝化层；
所述步骤 5 中通过涂覆制程在所述第一钝化层上形成黑色矩阵， 并对 该黑色矩阵进行第六光刻制程；
所述步骤 6 中在所述黑色矩阵与第一钝化层上形成一透明导电层， 并 按预定图案对该透明导电层进行第七光刻制程， 以形成公共电极。
8、 如权利要求 6 所述的阵列基板的制作方法， 其中， 所述第一基-板 为玻璃基板或塑料基板， 所述栅极绝缘层的厚度为 2000〜5000_A.， 所述栅 极的厚度为 2000 5000A, 所述半导体层的厚度为 2000 -4000A, 所述第一 钝化层的厚度为 i00〜6000A， 所述源 /漏极的厚度为 1000~6000A, 所述像 素电极的厚度为 誦〜 1000A， 所述公共电极的厚度为 100-lOOOA, 所述黑 色矩阵的厚度为 0,2〜i。0um。
9、 一种液晶显示面板， 包括： 一阵列基板、 一彩色滤光片基板。 以 及密封于阵列基板与彩色滤光片基板之间的液晶材料； 所述阵列基板包 括： 一第一基板、 形成于所述第一基板上的棚 ·极线、 形成于所述第一基板 上的数据线、 形成于所述第一基板上的薄膜晶体管阵列、 形成于所述薄膜 晶体管阵列上的像素电极、 形成于所述像素电极 数据线与薄膜晶体管阵 列上的第一钝化层、 形成于所述第一钝化层上的黑色矩阵， 以及形成于所 述黑色矩阵与第一钝化层上的公共电极； 所述彩色滤光片基板包括： 第二 基板、 形成于所述第二基板上的彩色滤光片、 形成于所述彩色滤光片与第 二基板上的第二钝化层、 以及形成于第二钝化层上的间隔层。
10, 如权利要求 9所述的液晶显示面板， 其中， 所述薄膜晶体管阵列 包括： 形成于所述第一基板上的柵极、 形成于所述第一基板与柵极上的櫥 极绝缘层、 形成于所述槲极绝缘层上的半导体层， 形成于所述半导体层上 的源 /漏极， 所述柵极由铬、 钼、 铝及铜形成， 所述栅极绝缘层通过等离子 体增强化学气相沉积法由硅沉积 成， 所述半导体层由氢化非晶硅沉积而 形成；
所述像素电极与公共电极分别为一透明导电层， 所述像素电极与公共 电极均由氧化铟锡或氧化铟锌制成， 所述第一基板为玻璃基板或塑料基 板；
所述柵极绝缘层的厚度为 2000〜5000A， 所述栅极的厚度为 2000〜5000A， 所述半导体层的厚度为 2000〜4000A , 所述第 - 钝化层的厚 度为 100〜6000A， 所述源 /漏极的厚度为 000〜6000A， 所述像素电极的厚 度为 100〜100θΑ, 所述公共电极的厚度为 100〜100θΑ, 所述黑色矩阵的厚 度为 0,2〜l ,0um;
所述第二基板为玻璃基板或塑料基板， 所述彩色滤光片包括： 红色滤 光片、 蓝色滤光片及绿色滤光片。
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