CN110764329A - 阵列基板及其制备方法、液晶显示面板、显示装置 - Google Patents

阵列基板及其制备方法、液晶显示面板、显示装置 Download PDF

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Publication number
CN110764329A
CN110764329A CN201911053760.8A CN201911053760A CN110764329A CN 110764329 A CN110764329 A CN 110764329A CN 201911053760 A CN201911053760 A CN 201911053760A CN 110764329 A CN110764329 A CN 110764329A
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China
Prior art keywords
electrode
lines
thin film
film transistor
grid
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Pending
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CN201911053760.8A
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English (en)
Inventor
陈鹏
赵剑
毛大龙
刘子正
王志贤
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BOE Technology Group Co Ltd
Wuhan BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Wuhan BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Wuhan BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201911053760.8A priority Critical patent/CN110764329A/zh
Publication of CN110764329A publication Critical patent/CN110764329A/zh
Priority to US16/847,025 priority patent/US20210132455A1/en
Pending legal-status Critical Current

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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种阵列基板及其制备方法、液晶显示面板、显示装置,能够避免在栅线和数据线交叠而产生较大的寄生电容的问题。阵列基板包括:衬底,设置于衬底上的多条栅线、多条数据线以及多条公共电极线;栅线和数据线平行,公共电极线与栅线交叉;多条公共电极线之间相互绝缘;多条栅线和/或多条数据线,与多条公共电极线限定出多个亚像素区域,亚像素区域设置有至少一个薄膜晶体管以及像素电极;像素电极与公共电极线同层同材料;薄膜晶体管包括栅极、半导体有源图案、源极和漏极;薄膜晶体管的源极与数据线电连接,漏极与像素电极电连接,栅极与栅线电连接。

Description

阵列基板及其制备方法、液晶显示面板、显示装置
技术领域
本发明涉及显示技术领域,尤其涉及一种阵列基板及其制备方法、液晶显示面板、显示装置。
背景技术
薄膜晶体管液晶显示装置(Thin Film Transistor Liquid Crystal Display,TFT-LCD)具有重量轻,厚度薄,功耗低,性能稳定,价格相对较低等特点,在当前平板显示领域占据主导市场。目前液晶显示器尺寸不断向大尺寸方向发展,随着面板尺寸的增大,对显示面板良率的要求越来越高。
目前,在薄膜晶体管液晶显示装置中,通常采用栅线和数据线交叉设置限定出多个亚像素区域。但是这种栅线和数据线的设置方式,沿显示装置厚度的方向,两者会产生交叠,在该交叠的区域,容易产生较大的寄生电容,增加显示装置发生闪烁等显示不良情况的几率,影响显示效果。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、液晶显示面板、显示装置,能够避免在栅线和数据线交叠而产生较大的寄生电容的问题。
为达到上述目的,本发明的实施例采用如下技术方案:
一方面,本发明提供一种阵列基板,包括:衬底,设置于所述衬底上的多条栅线、多条数据线以及多条公共电极线;所述栅线和所述数据线平行,所述公共电极线与所述栅线交叉;多条所述公共电极线之间相互绝缘。
多条所述栅线和/或多条所述数据线,与多条所述公共电极线限定出多个亚像素区域,所述亚像素区域设置有至少一个薄膜晶体管以及像素电极;所述像素电极与所述公共电极线同层同材料。
所述薄膜晶体管包括栅极、半导体有源图案、源极和漏极;所述薄膜晶体管的源极与所述数据线电连接,漏极与所述像素电极电连接,栅极与所述栅线电连接。
可选的,所述栅极设置于所述半导体有源图案靠近所述衬底一侧,作为底栅极。
所述薄膜晶体管还包括设置于所述源极和所述漏极远离所述衬底的一侧的顶栅极;所述顶栅极与所述底栅极电连接。
可选的,所述栅线充当所述薄膜晶体管的所述顶栅极。
可选的,沿所述衬底的厚度方向,所述薄膜晶体管中,所述底栅极在所述衬底上的正投影覆盖所述半导体有源图案在所述衬底上的正投影。
所述栅线在所述衬底上的正投影,覆盖与该栅线连接的所述薄膜晶体管中所述半导体有源图案在所述衬底上的正投影。
可选的,所述薄膜晶体管的沟道呈U形。
可选的,所述亚像素区域还设置有公共电极。
每根所述公共电极线与沿其延伸方向排布的一排所述亚像素区域中所述公共电极电连接。
在本发明实施例提供的阵列基板中,由于栅线和数据线平行设置,因而栅线和数据线不存在交叠区域,从而避免了栅线和数据线交叠而产生较大的寄生电容的问题。在此基础上,由多条栅线和/或多条数据线与多条公共电极线限定出多个亚像素区域P,由于公共电极线的线宽比栅线的线宽小,因此公共电极线与栅线的交叠区域较小,相应产生的寄生电容也小,而且,由于公共电极线与像素电极的材料相同,使得金属的栅线与透明导电材料的公共电极线的交叠区域产生的寄生电容更小,从而可减小显示装置发生闪烁等显示不良的情况的几率,提高显示效果。此外,当栅线和数据线平行设置时,栅线的线宽可以做的更小,从而能增大像素的开口率。
另一方面,本发明实施例还提供一种液晶显示面板,包括所述阵列基板。
再一方面,本发明实施例还提供一种显示装置,包括,所述液晶显示面板、栅极驱动电路、源极驱动电路以及公共电极驱动电路。
所述栅极驱动电路与多条栅线连接。
所述源极驱动电路与多条数据线连接。
所述公共电极驱动电路与多条公共电极线连接;所述公共电极驱动电路用于分别向每条所述公共电极线输出公共电压。
又一方面,本发明实施例还提供一种阵列基板的制备方法,包括:
在衬底上形成多条栅线、多条数据线以及多条公共电极线;所述栅线和所述数据线平行,所述公共电极线与所述栅线交叉;多条所述公共电极线之间相互绝缘;多条所述栅线与多条所述公共电极线限定出多个亚像素区域。
所述阵列基板的制备方法,还包括:在所述亚像素区域形成至少一个薄膜晶体管以及与所述薄膜晶体管连接的像素电极。
所述薄膜晶体管包括栅极、半导体有源图案、源极和漏极;所述薄膜晶体管的源极与所述数据线电连接,漏极与所述像素电极电连接,栅极与所述栅线电连接。
其中,所述像素电极与所述公共电极线通过同一次构图工艺形成,所述源极和所述漏极与所述数据线通过同一次构图工艺形成。
可选的,所述栅极作为底栅极,所述栅线还充当所述薄膜晶体管的顶栅极。
形成所述薄膜晶体管以及与所述薄膜晶体管连接的像素电极,包括。
在所述衬底上通过一次构图工艺形成栅极,并形成栅绝缘层。
在所述栅绝缘层上,通过一次构图工艺形成所述半导体有源图案。
通过一次构图工艺形成与所述半导体有源图案直接接触的所述源极和所述漏极。
通过一次构图工艺形成第一绝缘层,所述第一绝缘层包括多个第一过孔。
通过一次构图工艺形成像素电极,针对所述亚像素区域中的每个所述薄膜晶体管,所述像素电极均通过一个所述第一过孔与该薄膜晶体管的漏极电连接。
形成第二绝缘层,并通过一次构图工艺形成贯穿所述第二绝缘层、所述第一绝缘层和所述栅绝缘层的多个第二过孔。
通过一次构图工艺形成所述栅线,所述栅线通过所述第二过孔与所述栅极电连接。
可选的,沿所述衬底的厚度方向,所述薄膜晶体管中,所述底栅极在所述衬底上的正投影覆盖所述半导体有源图案在所述衬底上的正投影。
所述栅线在所述衬底上的正投影,覆盖与该栅线连接的所述薄膜晶体管中所述半导体有源图案在所述衬底上的正投影。
再一方面,本发明实施例提供一种所述显示装置的驱动方法,包括:
在一图像帧,栅极驱动电路依次向多条栅线输出扫描信号。
所述源极驱动电路向多条数据线输出数据信号。
所述公共电极驱动电路分别向多条公共电极线中的每条输出公共电压。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种显示装置的框架示意图;
图2a为本发明实施例提供的一种背光模组的结构示意图;
图2b为本发明实施例提供的另一种背光模组的结构示意图;
图3a为本发明实施例提供的一种液晶显示面板的结构示意图;
图3b为本发明实施例提供的另一种液晶显示面板的结构示意图;
图4为本发明实施例提供的一种阵列基板的结构示意图;
图5为本发明实施例提供的另一种阵列基板的结构示意图;
图6a为本发明实施例提供的图4中R区域的结构示意图;
图6b为本发明实施例提供的图6a中AA’的剖面示意图;
图6c为本发明实施例提供的图6a中GG’的剖面示意图;
图7为本发明实施例提供的再一种阵列基板的结构示意图;
图8为本发明实施例提供的又一种阵列基板的结构示意图;
图9a为本发明实施例提供的图8中Q区域的结构示意图;
图9b为本发明实施例提供的图9a中BB’的剖面示意图;
图9c为本发明实施例提供的图9a中CC’的剖面示意图;
图10a为本发明实施例提供的又一种阵列基板的结构示意图;
图10b为本发明实施例提供的再一种阵列基板的结构示意图;
图11为本发明实施例提供的一种显示装置的结构示意图;
图12为本发明实施例提供的阵列基板的制备方法中形成薄膜晶体管以及与薄膜晶体管连接的像素电极的流程示意图;
图13a为本发明实施例提供的阵列基板的制备方法中形成栅极以及栅绝缘层后阵列基板的结构示意图;
图13b为本发明实施例提供的图13a中DD’的剖面示意图;
图14为本发明实施例提供的阵列基板的制备方法中形成半导体有源图案后阵列基板的结构示意图;
图15为本发明实施例提供的阵列基板的制备方法中形成源极和漏极后阵列基板的结构示意图;
图16a为本发明实施例提供的阵列基板的制备方法中形成第一绝缘层以及第一过孔后阵列基板的结构示意图;
图16b为本发明实施例提供的图16a中EE’的剖面示意图;
图17为本发明实施例提供的阵列基板的制备方法中形成像素电极后的阵列基板的结构示意图;
图18a为本发明实施例提供的阵列基板的制备方法中形成第二绝缘层以及第二过孔后的阵列基板的结构示意图;
图18b为本发明实施例提供的图18a中FF’的剖面示意图;
图19为本发明实施例提供的一种显示面板的驱动方法的流程示意图。
附图标记
1-框架;2-玻璃盖板;3-液晶显示面板;4-背光模组;5-电路板;6-栅极驱动电路;7-源极驱动电路;8-公共电极驱动电路;41-背光源、42-导光板;43光学膜片;30-阵列基板;310衬底;311-栅线;312-数据线;313-公共电极线;314-薄膜晶体管;315-像素电极;316-公共电极;3141-栅极;3142-半导体有源图案;3143-源极;3144-漏极;3145-栅绝缘层;3147-第一绝缘层;3148-第二绝缘层;3141a-底栅极;3141b-顶栅极;3147a-第一过孔;2148a-第二过孔。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
如图1所示,本发明实施例提供的液晶显示装置的主要结构包括框架1、盖板玻璃2、液晶显示面板3、背光模组4、电路板5以及包括其他电子配件。本发明实施例提供的液晶显示面板3包括阵列基板30、对盒基板40以及设置于阵列基板30和对盒基板40之间的液晶层50,阵列基板30和对盒基板40通过封框胶对合在一起,从而将液晶层50限定在封框胶围成的区域内。
其中,框架1的纵截面例如呈U型,液晶显示面板3、背光模组4、电路板5以及其他电子配件设置于框架1内,背光模组4设置于液晶显示面板3的下方,电路板5设置于背光模组4下方,盖板玻璃2位于液晶显示面板3远离背光模组4的一侧。
如图2a和图2b所示,背光模组4包括背光源41、导光板42以及设置于导光板42出光侧的光学膜片43等。光学膜片43例如可以包括扩散片和/或增光膜等。导光板42的形状有楔形和平板型两种,图2a中以导光板42为楔形板进行示意,图2b以导光板42为平板型进行示意。增光膜例如可以包括棱镜膜(Brightness Enhancement Film,BEF)和反射型偏光增亮膜(Dual Brightness Enhancement Film,DBEF),两者可以结合使用。
其中,如图2a所示,背光源41可以设置于导光板42的侧面,在此情况下,该背光模组4为侧入式背光模组。如图2b所示,背光源41也可以设置于导光板42的远离出光侧的一侧,在此情况下,该背光模组4为直下式背光模组。背光源41例如可以是发光二极管(Light-Emitting Diode,LED)。图2a和图2b中的背光模组4的结构仅为示意,不做任何限定。此外,如图2a和图2b所示,背光模组4还可以包括反射片44,对于侧入式背光模组,反射片44设置于导光板42的远离出光侧的一侧;对于直下式背光模组,反射片44设置于背光源41远离导光板42的一侧。
如图3a和图3b所示,液晶显示面板3具有显示区A和周边区S,周边区S例如围绕显示区A一周设置。上述显示区A中包括多种颜色的亚像素(sub pixel)P;该多种颜色的亚像素P至少包括第一颜色亚像素、第二颜色亚像素和第三颜色亚像素,第一颜色、第二颜色和第三颜色为三基色(例如红色、绿色和蓝色)。
图3a和图3b中以上述多个亚像素P呈阵列形式排列为例进行的说明。在此情况下,沿水平方向排列成一排的亚像素P称为同一行亚像素P,沿竖直方向排列成一排的亚像素P称为同一列亚像素P。
如图4和图5所示,本发明实施例提供一种阵列基板30,包括:衬底310,设置于衬底310上的多条栅线311、多条数据线312以及多条公共电极线313;栅线311和数据线312平行,公共电极线313与栅线311交叉;多条公共电极线313之间相互绝缘。可以理解的是,栅线311、数据线312、公共电极线313之间互相绝缘,当然,多条栅线311之间,多条数据线312之间也相互绝缘。其中,公共电极线313用于向公共电极提供电压。
多条栅线311和/或多条数据线312,与多条公共电极线313限定出多个亚像素区域P′。亚像素区域P′中设置有至少一个薄膜晶体管314以及与薄膜晶体管314连接的像素电极315;像素电极315与公共电极线313同层同材料。可以理解的是,每个亚像素P所在的区域即为此处的亚像素区域P′。
如图6a、图6b和图6c所示,薄膜晶体管314包括栅极3141、半导体有源图案3142、源极3143和漏极3144;薄膜晶体管314的源极3143与数据线312电连接,漏极3144与像素电极315电连接,栅极3141与栅线311电连接。其中,薄膜晶体管314还包括设置在栅极3141与半导体有源图案3142之间的栅绝缘层3145。图6a、图6b和图6c以薄膜晶体管314为顶栅型薄膜晶体管为例进行示意,本发明实施例并不限于此。
其中,在包括该阵列基板30的上述液晶显示面板3中,如图4和图5所示,沿栅线311的延伸方向,同一排的亚像素P中的各薄膜晶体管314均连接同一条栅线311以及同一条数据线312。沿公共电极线313的延伸方向,同一排的亚像素P中的公共电极连接一条公共电极线313。
以栅线311的延伸方向为竖直方向,公共电极线313的延伸方向为水平方向为例,位于每列亚像素P中各薄膜晶体管314与一根栅线311连接,并与一根数据线312连接,位于同一行亚像素P中的公共电极316与一根公共电极线313连接。
以栅线311的延伸方向为竖直方向,公共电极线313的延伸方向为水平方向为例,包括该阵列基板30的上述液晶显示面板3的工作原理为:
在一图像帧,多条栅线311依次输入扫描信号,当任一条栅线311输入扫描信号时,使得与该栅线311连接的一列亚像素P中的薄膜晶体管314开启。当这一列亚像素P中的薄膜晶体管314开启后,与该列亚像素P中的薄膜晶体管314连接的数据线312输入数据电压,以向像素电极315提供该数据电压。与此同时,每条公共电极线313各自独立输出公共电压,对于每个亚像素P而言,可通过像素电极315与公共电极316上的电压,来控制该亚像素P所在区域的液晶的偏转角度,使该亚像素P能够进行不同的灰阶显示。
也就是说,对于同一列亚像素P而言,该列亚像素P中像素电极315上的电压是相同的。但是该列亚像素P中,公共电极上的电压是独立输出的,可能相同,也可能不完全相同,或者可能完全不相同。
需要说明的是,公共电极可以设置在阵列基板30上,也可以设置在对盒基板40上,本发明对此不作限定。但是基于上述的说明可知,在显示区A,公共电极不是整层设置的,以公共电极线313的延伸方向为水平方向为例,不同行亚像素P中的公共电极是相互间隔的。
对于栅线311和数据线312的设置方式,示例的,如图4所示,栅线311和数据线312依次排布,且栅线311和数据线312两两为一组,位于相邻两组中且靠近的栅线311和数据线312、以及公共电极线313限定亚像素区域P′。基于此,每组栅线311和数据线312与位于一列亚像素区域P′中的薄膜晶体管314连接,栅线311、数据线312以及亚像素区域P′的列数一一对应。
又示例的,如图5所示,栅线311两两为一组,且每组栅线311之间设置一根数据线312,位于不同组栅线311中,且靠近的两根栅线311、以及公共电极线313限定亚像素区域P′。基于此,每组栅线311分别与其两侧的两列亚像素区域P′中的薄膜晶体管314连接,位于该组栅线311之间的数据线312与该两列亚像素区域P′中的薄膜晶体管314均连接,栅线311与亚像素区域P′的列数一一对应,数据线312的个数少于栅线311的个数。
在本发明实施例提供的阵列基板30中,通过使栅线311和数据线312平行设置,公共电极线313与栅线311交叉设置,公共电极线313相互绝缘,并使位于亚像素区域P′中的薄膜晶体管314的源极3143与数据线312电连接,漏极3144与像素电极315电连接,栅极3141与栅线311电连接,可在公共电极线313与沿其延伸方向排布的亚像素中的公共电极电连接时,保证包括该阵列基板30的液晶显示面板3的正常工作。由于栅线311和数据线312平行设置,因而栅线311和数据线312不存在交叠区域,从而避免了栅线311和数据线312交叠而产生较大的寄生电容的问题。在此基础上,由多条栅线311和/或多条数据线312与多条公共电极线313限定出多个亚像素区域P,由于公共电极线313的线宽比栅线311的线宽小,因此公共电极线313与栅线311的交叠区域较小,相应产生的寄生电容也小,而且,由于公共电极线313与像素电极315的材料相同,使得金属的栅线311与透明导电材料的公共电极线313的交叠区域产生的寄生电容更小,从而可减小显示装置发生闪烁等显示不良的情况的几率,提高显示效果。此外,当栅线311和数据线312平行设置时,液晶层中的隔离柱可以卡在栅线311和数据线312之间,从而防止隔离柱向亚像素区域P滑动,栅线311无需支撑隔离柱,因此,栅线311的线宽可以做的更小,从而能增大像素的开口率。
可选的,如图4-图5以及图6a所示,薄膜晶体管314的沟道呈U形。
当然薄膜晶体管314的沟道也可以呈1字形,即,如图7所示,源极3143和漏极3144分为位于栅极3141相对的两侧。
U形沟道的薄膜晶体管314具有较高的宽长比,且该结构的薄膜晶体管314还可以应用在栅极驱动电路中。
可选的,如图8、图9a-图9c所示,栅极3141设置于半导体有源图案3142靠近衬底310一侧,作为底栅极3141a。
薄膜晶体管314还包括设置于源极3143和漏极3144远离衬底310的一侧的顶栅极3141b;顶栅极3141b与底栅极3141a电连接。
其中,顶栅极3141b与半导体有源图案3142之间还可以设置有第二绝缘层3148。
通过将薄膜晶体管314设置为双栅极薄膜晶体管,可以减小开启与关闭薄膜晶体管314所需的时间,提高薄膜晶体管314的响应速度。可选的,如图8和图9a-图9c所示,栅线311充当薄膜晶体管314的顶栅极3141b。
这样一来,无须单独制作栅线311,简化了制作工艺。
在此基础上,可选的,如图9a-图9c所示,沿衬底310的厚度方向,薄膜晶体管314中,底栅极3141a在衬底310上的正投影覆盖半导体有源图案3142在衬底310上的正投影。
栅线311在衬底310上的正投影,覆盖与该栅线10连接的薄膜晶体管314中半导体有源图案3142在衬底310上的正投影。
基于此,底栅极3141a可以遮挡从背光源4入射至半导体有源图案3142的光线,栅线311可以遮挡从外界入射至半导体有源图案3142的光线,可降低光线对薄膜晶体管314中沟道漏电流的影响,提高薄膜晶体管314稳定性。同时,栅线311可替代彩色滤光片中的黑矩阵,起到遮挡漏光区功能,因而整体工艺制程无需额外增加掩膜版,从而节约成本。
可选的,如图8和图9a所示,每个亚像素区域P′中均设置有两个薄膜晶体管314。
其中,每个薄膜晶体管314的栅极3144分别与同一栅线311电连接,源极3143分别与同一数据线312电连接,漏极3144分别与同一像素电极315电连接。
即,同一个像素电极315由两个薄膜晶体管314驱动,当其中一个薄膜晶体管314出现单个过孔不良而失效时,另外一个薄膜晶体管314可以驱动像素电极315正常工作,提高了包括该阵列基板30的液晶显示面板3的良率。
可选的,如图10a和图10b所示,亚像素区域P′还设置有公共电极316。
每根公共电极线313与沿其延伸方向排布的一排亚像素区域P′中公共电极316电连接。
基于上述的描述,如图11所示,本发明实施例提供的显示装置中,还设置有栅极驱动电路6、源极驱动电路7以及公共电极驱动电路8。
栅极驱动电路6与多条栅线311连接。其中,栅极驱动电路6可以利用阵列基板行驱动(Gate Driver on Array,GOA)技术直接设置在阵列基板30上,也可以为集成电路(Integrated Circuit,IC),绑定在阵列基板30上或者与阵列基板30连接的柔性线路板上。
源极驱动电路7与多条数据线312连接。其中,源极驱动电路7可以为IC,绑定在阵列基板30上或者与阵列基板30连接的柔性线路板上。
公共电极驱动电路8与多条公共电极线313连接;公共电极驱动电路8用于分别向每条公共电极线313输出公共电压。其中,公共电极驱动电路8可以为IC,绑定在阵列基板30连接的柔性线路板上。
本发明实施例提供一种阵列基板300的制备方法包括:
如图4和图5所示,在衬底310上形成多条栅线311、多条数据线312以及多条公共电极线313;栅线311和数据线312平行,公共电极线313与栅线311交叉;多条公共电极线313之间相互绝缘;多条栅线311和/或多条数据线312,与多条公共电极线313限定出多个亚像素区域P′。
其中,栅线311与公共电极线313交叉,例如可以为栅线311沿第一方向延伸,公共电极线313沿第二方向延伸,第一方向与第二方向互相垂直,多条栅线311和/或多条数据线312,与多条公共电极线313限定出多个亚像素区域P′。这样一来,沿第一方向的同一排所有亚像素区域P′中的薄膜晶体管314连接至同一条栅线311和同一条数据线312,沿第二方向的同一排所有亚像素区域P′中的薄膜晶体管314连接至同一公共电极线313。
在此基础上,阵列基板300的制备方法还包括:
如图6a-6b所示,在亚像素区域P′形成至少一个薄膜晶体管314以及与薄膜晶体管314连接的像素电极315。
薄膜晶体管314包括栅极3141、半导体有源图案3142、源极3143和漏极3144;薄膜晶体管314的源极3143与数据线312电连接,漏极3144与像素电极315电连接,栅极3141与栅线311电连接。
其中,像素电极315与公共电极线313通过同一次构图工艺形成,源极3143和漏极3144与数据线312通过同一次构图工艺形成。构图工艺包括涂覆光刻胶、掩膜曝光、显影以及刻蚀工艺。
在本发明实施例提供的阵列基板的制备方法中,通过使栅线311和数据线312平行,公共电极线313与栅线311交叉,公共电极线313相互绝缘,并使位于亚像素区域P′中的薄膜晶体管314的源极3143与数据线312电连接,漏极3144与像素电极315电连接,栅极3141与栅线311电连接,可在公共电极线313与沿其延伸方向排布的亚像素中的公共电极电连接时,保证包括该阵列基板30的液晶显示面板3的正常工作。由于栅线311和数据线312平行,因而栅线311和数据线312不存在交叠区域,从而避免了在栅线311和数据线312交叠而产生较大的寄生电容的问题。在此基础上,由多条栅线311和/或多条数据线312与多条公共电极线313限定出多个亚像素区域P,由于公共电极线313的线宽比栅线311的线宽小,因此公共电极线313与栅线311的交叠区域较小,相应产生的寄生电容也小,而且,由于公共电极线313与像素电极315的材料相同,使得金属的栅线311与透明导电材料的公共电极线313的交叠区域产生的寄生电容更小,从而可减小显示装置发生闪烁等显示不良的情况的几率,提高显示效果。此外,通过同一次构图工艺形成像素电极315与公共电极线313和通过同一次构图工艺形成源极3143和漏极3144与数据线312,可以简化制作工艺。
可选的,如图8-图9所示,栅极3141作为底栅极3141a,栅线311还充当薄膜晶体管314的顶栅极3141b。
通过将薄膜晶体管314设置为双栅极薄膜晶体管,可以减小开启与关闭薄膜晶体管314所需的时间,提高薄膜晶体管314的响应速度,并且无须单独制作顶栅极3141b,简化了制作工艺。同时,栅线311可以遮挡从外界入射至半导体有源图案3142的光线,可降低光线对薄膜晶体管314中沟道漏电流的影响,提高薄膜晶体管314稳定性。此外,栅线311可替代彩色滤光片中的黑矩阵,起到遮挡漏光区功能,因而整体工艺制程无需额外增加用于制作黑矩阵的掩膜版,从而节约成本。
如图12所示,形成薄膜晶体管314以及与薄膜晶体管314连接的像素电极315,包括:
S10、如图13a和图13b所示,在衬底310上通过一次构图工艺形成栅极3141,并形成栅绝缘层3145。
S11、如图14所示,在栅绝缘层3145上,通过一次构图工艺形成半导体有源图案3142。
S12、如图15所示,通过一次构图工艺形成与半导体有源图案3142直接接触的源极3143和漏极3144;
S13、如图16a和图16b所示,通过一次构图工艺形成第一绝缘层3147,所述第一绝缘层3147包括多个第一过孔3147a。
S14、如图17所示,通过一次构图工艺形成像素电极315,针对亚像素区域P′中的每个薄膜晶体管314,像素电极315均通过一个第一过孔3147a与该薄膜晶体管314的漏极3144电连接。
S15、如图18a和图18b所示,形成第二绝缘层3148,并通过一次构图工艺形成贯穿第二绝缘层3148、第一绝缘层3147和所述栅绝缘层3145的多个第二过孔3148a。
S16、如图9a-图9c所示,通过一次构图工艺形成栅线311,栅线311通过第二过孔3148a与栅极311电连接。
可选的,沿衬底310的厚度方向,薄膜晶体管314中,底栅极3141a在衬底310上的正投影覆盖半导体有源图案3142在衬底310上的正投影。
栅线311在衬底310上的正投影,覆盖与该栅线311连接的薄膜晶体管314中半导体有源图案3142在衬底310上的正投影。
在此基础上,底栅极3141a可以遮挡从背光源4入射至半导体有源图案3142的光线,栅线311可以遮挡从外界入射至半导体有源图案3142的光线,从而能够降低入射至阵列基板30的光线对薄膜晶体管314中沟道漏电流的影响,提高薄膜晶体管314稳定性。
本发明实施例提供一种显示装置的驱动方法,如图19所示,包括:
S20、在一图像帧,栅极驱动电路6依次向多条栅线311输出扫描信号。
S21、源极驱动电路7向多条数据线312输出数据信号。
S22、公共电极驱动电路8分别向多条公共电极线313中的每条输出公共电压。
需要说明的是,公共电极驱动电路8由独立的IC芯片控制,公共电极线313互相之间绝缘,因此各公共电极线313之间的公共电压可以不同。
以栅线311的延伸方向为竖直方向,公共电极线313的延伸方向为水平方向为例,包括该阵列基板30的上述液晶显示面板3的工作原理为:
在一图像帧,当栅极驱动电路6向任一条栅线311输出扫描信号时,使得与该栅线311的连接的一列亚像素P中的薄膜晶体管314开启。当这一列亚像素P中的薄膜晶体管314开启后,源极驱动电路7为与该列亚像素P中的薄膜晶体管314的源极连接的数据线输出数据信号,以向像素电极315提供该数据信号对应的数据电压。与此同时,公共电极驱动电路8分别向多条公共电极线313中的每条输出公共电压。对于每个亚像素P而言,可通过像素电极315与公共电极316上的电压,来控制该亚像素P所指区域的液晶的偏转角度,使该亚像素P能够进行不同的灰阶显示。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。

Claims (13)

1.一种阵列基板,其特征在于,包括:衬底,设置于所述衬底上的多条栅线、多条数据线以及多条公共电极线;所述栅线和所述数据线平行,所述公共电极线与所述栅线交叉;多条所述公共电极线之间相互绝缘;
多条所述栅线和/或多条所述数据线,与多条所述公共电极线限定出多个亚像素区域,所述亚像素区域设置有至少一个薄膜晶体管以及像素电极;所述像素电极与所述公共电极线同层同材料;
所述薄膜晶体管包括栅极、半导体有源图案、源极和漏极;所述薄膜晶体管的源极与所述数据线电连接,漏极与所述像素电极电连接,栅极与所述栅线电连接。
2.根据权利要求1所述的阵列基板,其特征在于,所述栅极设置于所述半导体有源图案靠近所述衬底一侧,作为底栅极;
所述薄膜晶体管还包括设置于所述源极和所述漏极远离所述衬底的一侧的顶栅极;所述顶栅极与所述底栅极电连接。
3.根据权利要求2所述的阵列基板,其特征在于,所述栅线充当所述薄膜晶体管的所述顶栅极。
4.根据权利要求2所述的阵列基板,其特征在于,沿所述衬底的厚度方向,所述薄膜晶体管中,所述底栅极在所述衬底上的正投影覆盖所述半导体有源图案在所述衬底上的正投影;
所述栅线在所述衬底上的正投影,覆盖与该栅线连接的所述薄膜晶体管中所述半导体有源图案在所述衬底上的正投影。
5.根据权利要求1所述的阵列基板,其特征在于,所述薄膜晶体管的沟道呈U形。
6.根据权利要求1-5任一项所述的阵列基板,其特征在于,每个所述亚像素区域中均设置有两个所述薄膜晶体管。
7.根据权利要求1-5任一项所述的阵列基板,其特征在于,所述亚像素区域还设置有公共电极;
每根所述公共电极线与沿其延伸方向排布的一排所述亚像素区域中所述公共电极电连接。
8.一种液晶显示面板,其特征在于,包括权利要求1-7任一项所述的阵列基板。
9.一种显示装置,其特征在于,包括权利要求8所述的液晶显示面板、栅极驱动电路、源极驱动电路以及公共电极驱动电路;
所述栅极驱动电路与多条栅线连接;
所述源极驱动电路与多条数据线连接;
所述公共电极驱动电路与多条公共电极线连接;所述公共电极驱动电路用于分别向每条所述公共电极线输出公共电压。
10.一种阵列基板的制备方法,其特征在于,包括:在衬底上形成多条栅线、多条数据线以及多条公共电极线;所述栅线和所述数据线平行,所述公共电极线与所述栅线交叉;多条所述公共电极线之间相互绝缘;多条所述栅线与多条所述公共电极线限定出多个亚像素区域;
所述阵列基板的制备方法,还包括:在所述亚像素区域形成至少一个薄膜晶体管以及与所述薄膜晶体管连接的像素电极;
所述薄膜晶体管包括栅极、半导体有源图案、源极和漏极;所述薄膜晶体管的源极与所述数据线电连接,漏极与所述像素电极电连接,栅极与所述栅线电连接;
其中,所述像素电极与所述公共电极线通过同一次构图工艺形成,所述源极和所述漏极与所述数据线通过同一次构图工艺形成。
11.根据权利要求10所述的阵列基板的制备方法,其特征在于,所述栅极作为底栅极,所述栅线还充当所述薄膜晶体管的顶栅极;
形成所述薄膜晶体管以及与所述薄膜晶体管连接的像素电极,包括:
在所述衬底上通过一次构图工艺形成栅极,并形成栅绝缘层;
在所述栅绝缘层上,通过一次构图工艺形成所述半导体有源图案;
通过一次构图工艺形成与所述半导体有源图案直接接触的所述源极和所述漏极;
通过一次构图工艺形成第一绝缘层,所述第一绝缘层包括多个第一过孔;
通过一次构图工艺形成像素电极,针对所述亚像素区域中的每个所述薄膜晶体管,所述像素电极均通过一个所述第一过孔与该薄膜晶体管的漏极电连接;
形成第二绝缘层,并通过一次构图工艺形成贯穿所述第二绝缘层、所述第一绝缘层和所述栅绝缘层的多个第二过孔;
通过一次构图工艺形成所述栅线,所述栅线通过所述第二过孔与所述栅极电连接。
12.根据权利要求11所述的阵列基板的制备方法,其特征在于,沿所述衬底的厚度方向,所述薄膜晶体管中,所述底栅极在所述衬底上的正投影覆盖所述半导体有源图案在所述衬底上的正投影;
所述栅线在所述衬底上的正投影,覆盖与该栅线连接的所述薄膜晶体管中所述半导体有源图案在所述衬底上的正投影。
13.一种如权利要求9所述的显示装置的驱动方法,其特征在于,包括:
在一图像帧,栅极驱动电路依次向多条栅线输出扫描信号;
所述源极驱动电路向多条数据线输出数据信号;
所述公共电极驱动电路分别向多条公共电极线中的每条输出公共电压。
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CN114236928B (zh) * 2021-12-22 2023-09-29 京东方科技集团股份有限公司 显示面板及显示装置
CN114236928A (zh) * 2021-12-22 2022-03-25 京东方科技集团股份有限公司 显示面板及显示装置
CN114994992A (zh) * 2022-05-11 2022-09-02 京东方科技集团股份有限公司 显示面板及显示装置
CN114994992B (zh) * 2022-05-11 2023-10-20 京东方科技集团股份有限公司 显示面板及显示装置

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