WO2022088102A1 - 电极结构、显示面板及显示装置 - Google Patents

电极结构、显示面板及显示装置 Download PDF

Info

Publication number
WO2022088102A1
WO2022088102A1 PCT/CN2020/125534 CN2020125534W WO2022088102A1 WO 2022088102 A1 WO2022088102 A1 WO 2022088102A1 CN 2020125534 W CN2020125534 W CN 2020125534W WO 2022088102 A1 WO2022088102 A1 WO 2022088102A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
substrate
strip
width
orthographic projection
Prior art date
Application number
PCT/CN2020/125534
Other languages
English (en)
French (fr)
Inventor
陈轶夫
曲莹莹
董霆
黄建华
薄灵丹
曲峰
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002577.XA priority Critical patent/CN114981719B/zh
Priority to US17/425,397 priority patent/US11921378B2/en
Priority to PCT/CN2020/125534 priority patent/WO2022088102A1/zh
Publication of WO2022088102A1 publication Critical patent/WO2022088102A1/zh
Priority to US18/396,474 priority patent/US20240126122A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an electrode structure, a display panel and a display device.
  • the ITO (indium tin oxide) electrode structure on the array substrate is made smaller and smaller.
  • the purpose of the present disclosure is to provide an electrode structure, a display panel and a display device, which can improve the light efficiency and transmittance of a pixel, and at the same time, can reduce the defective wire breakage in the manufacturing process and improve the production yield.
  • a first aspect of the present disclosure provides an electrode structure comprising:
  • the first electrode part includes a first connection strip extending in a first direction and a plurality of first electrode strips arranged at intervals in the first direction, the first connection strips having opposite sides in the second direction On the first side and the second side, the plurality of first electrode strips are located on the first side of the first connection strip and are connected to the first connection strip, and adjacent to the first electrode strips are far away from the The ends of the first connecting strip are in an opening shape;
  • the second electrode portion is spaced from the first electrode portion in the first direction, and the second electrode portion includes a second connection bar extending in the first direction and a second connection bar extending in the first direction.
  • a plurality of second electrode strips are arranged at intervals upward, the second connection strips are located at a position away from the second side from the first side, and the second connection strips have a second electrode strip opposite in the second direction.
  • Three sides and a fourth side the third side is located at the position of the fourth side close to the first side; the plurality of second electrode strips are located on the third side of the second connection strip and are connected with the The second connection bars are connected, and the ends of the adjacent second electrode bars away from the second connection bars are in an opening shape;
  • connection part located between the first electrode part and the second electrode part, two ends of the conductive connection part are respectively connected with the first connection bar and the second connection bar; and the conductive connection
  • the area of the connection part is larger than the area of the first electrode strip and the area of the second electrode strip;
  • first direction and the second direction are perpendicular to each other.
  • the orthographic projections of the first electrode portion, the second electrode portion, and the conductive connection portion on a reference plane coincide with each other; wherein the reference plane is the same as the reference plane.
  • the extension directions of the first electrode strips, the second electrode strips, and the conductive connection parts are all parallel to the third direction, and the first electrode strips a width equal to the first width of the second electrode strip, and the first width of the first electrode strip is smaller than the first width of the conductive connecting portion;
  • the first width is a dimension in a fourth direction
  • the third direction is perpendicular to the fourth direction
  • the third direction intersects both the first direction and the second direction .
  • the conductive connection portion includes a first conductive connection bar and a second conductive connection bar that are spaced apart in the second direction and both extend in the first direction , and at least two third conductive connection strips located between the first conductive connection strip and the second conductive connection strip and arranged at intervals in the first direction, each of the third conductive connection strips has The two ends are respectively connected with the first conductive connection bar and the second conductive connection bar, and the extension direction of the third conductive connection bar is parallel to the third direction;
  • first conductive connection bar is connected to the first connection bar
  • second conductive connection bar is connected to the second connection bar
  • a first width of the third conductive connection strip is equal to a first width of the first electrode strip, and a second width of the first conductive connection strip is equal to the first width of the first conductive connection strip.
  • the second width of the first connection strip is equal, and the second width of the second conductive connection strip is equal to the second width of the second connection strip; wherein, the second width is in the second direction. size.
  • the gap between the adjacent first electrode strips is a first gap
  • the gap between the adjacent second electrode strips is a second gap
  • the adjacent The gap between the third conductive connecting strips is a third gap
  • the gap between the third conductive connecting strip and the first electrode strip is a fourth gap
  • the gap between the strips is a fifth gap, wherein the first width of the first gap, the first width of the second gap, the first width of the third gap, the first width of the fourth gap The width is equal to the first width of the fifth slit.
  • a ratio of the first width of the first slit to the first width of the first electrode strip is 1 to 4.
  • the length of the first conductive connection bar and the length of the second conductive connection bar are both smaller than the length of the first connection bar and the length of the second connection bar a length, the length being a dimension in the first direction.
  • the conductive connection part is a conductive connection bar
  • the conductive connection bar extends in the third direction
  • the first width of the conductive connection bar is the same as the first width of the first conductive connection bar.
  • the ratio of the first widths of the electrode strips is 1.5 to 5.5.
  • the first electrode part further includes a signal connection bar located on a first side of the first connection bar and connected to the first connection bar, and located on the plurality of first connection bars.
  • An electrode strip is away from the side of the conductive connection part.
  • a second aspect of the present disclosure provides a display panel including an array substrate, wherein the array substrate includes:
  • the first substrate has a plurality of sub-pixel regions arranged in an array along the row and column directions, a first wiring region located between the sub-pixel regions in two adjacent rows, and a second wiring region located between two adjacent columns a wiring area, there is overlap between the first wiring area and the second wiring area;
  • each of the sub-pixel units including a pixel electrode at least partially located in the sub-pixel area, a common electrode and a transistor at least partially located in the first wiring area ;
  • the transistor includes a gate, a first electrode and a second electrode;
  • the pixel electrode is connected to the first electrode;
  • the orthographic projection of the common electrode on the first substrate is the same as the pixel electrode at the The orthographic projections on the first substrate overlap; and at least one of the pixel electrode and the common electrode is the electrode structure described in any one of the above, and the row direction is the second direction, the column direction is the first direction;
  • a plurality of rows of scan lines are formed on the first substrate, at least one row of the scan lines is located in one of the first wiring regions, the scan lines are connected to the gate, and are configured to connect to the sub-pixels unit provides scan signal,
  • a plurality of rows of common lines are formed on the first substrate, at least one row of the common lines is located in one of the first wiring regions, the common lines are connected to the common electrodes, and are configured to connect to the sub-pixels
  • the unit provides a common signal
  • a plurality of columns of data lines are formed on the first substrate, at least one column of the data lines is located in one of the second wiring regions, the data lines are connected to the second pole, and are configured to be connected to the sub-substrate
  • the pixel unit provides data signals
  • the orthographic projection of the scan line on the first substrate and the orthographic projection of the common line on the first substrate do not overlap; the data line on the first substrate The orthographic projection overlaps the orthographic projection of the scan line and the common line on the first substrate.
  • the common electrode is located on a side of the pixel electrode away from the first substrate, and the common electrode is the electrode structure.
  • the display panel further includes:
  • a plurality of spacers are located on a side of the data line away from the first substrate, and an orthographic projection of each of the spacers on the first substrate is located at one of the alignment parts on the in the orthographic projection on the first substrate.
  • each of the first wiring regions is provided with a row of the scan lines and a row of the common lines, and the alignment portion is on the positive side of the first substrate.
  • the projection is between the scan line and the orthographic projection of the common line on the first substrate.
  • the data line further has a first overlapping portion overlapping with an orthographic projection of the scan line on the first substrate, and a first overlapping portion overlapping with the common line
  • the orthographic projection on the first substrate has an overlapping second overlapping portion; wherein, the distance between the first overlapping portion and the alignment portion in the column direction is a first distance, and the The spacing between the second overlapping portion and the alignment portion in the column direction is a second spacing, and the ratio of the first spacing and the second spacing to the first width of the first electrode strip is 1.5 to 17.
  • the signal connection bar of the common electrode is located in the first wiring area
  • the common electrode is located on a side of the common line away from the first substrate, and the signal connection bar is connected to the common line through a first via structure;
  • the common line has a first segment outside the second wiring area and inside the first wiring area, and the first segment has a first portion, a second portion arranged in sequence in the row direction part and a third part, the side of the third part away from the scan line is farther from the scan line than the side of the first part away from the scan line, the second part away from the scan line
  • the side of the first part is closer to the scan line than the side of the first part farther away from the scan line, and the side of the second part farther away from the scan line and the first part and the third part a gap is formed between;
  • the part of the orthographic projection of the first via structure on the first substrate overlaps with the orthographic projection of the second part and the third part on the first substrate, and another A part overlaps with the orthographic projection of the notch on the first substrate; and the distance between the boundary line of the first via structure and the boundary line of the third part in the column direction is the first Three pitches, the pitch between the boundary line of the first via structure and the boundary line of the third portion away from the second portion in the row direction is a fourth pitch, and the boundary of the first via structure The distance between the line and the boundary line of the second part far from the third part in the row direction is a fifth distance, and the third distance, the fourth distance and the fifth distance are different from the first distance.
  • the ratio of the first widths of an electrode strip is 1-6.
  • each column of data lines is connected to a first electrode of a transistor of each of the sub-pixel units in a column of sub-pixel units.
  • two adjacent first poles located on opposite sides of the data line in the row direction and adjacent to each other have an equal interval with the data line in the row direction.
  • the first electrodes of the transistors in each of the sub-pixel units and the data lines connected thereto are equally spaced in the row direction.
  • two adjacent pixel electrodes located on opposite sides of the data line in the row direction and adjacent to the data line are symmetrically disposed with respect to the data line.
  • the two adjacent common electrodes on opposite sides in the row direction are symmetrically arranged with respect to the data line.
  • it further includes: an opposite substrate arranged in a cell-to-cell manner with the array substrate, and liquid crystal molecules located between the opposite substrate and the array substrate;
  • the opposite substrate includes a second substrate on the side of the spacer away from the array substrate and a shielding layer on the side of the second substrate close to the array substrate, the shielding layer having cross shielding part, first shielding parts located on opposite sides of the cross shielding part in the row direction, and second shielding parts located on opposite sides of the cross shielding part in the column direction;
  • the orthographic projection of the cross shielding portion on the first substrate at least covers the intersection region of the first wiring region and the second wiring region, and the first shielding portion on the first substrate
  • the orthographic projection covers at least the first wiring area and is located outside the second wiring area
  • the orthographic projection of the second shielding portion on the first substrate covers at least the second wiring area and is located at the outside the first wiring area
  • the maximum dimension of the cross shielding part corresponding to the spacer in the column direction is larger than the maximum dimension of the first shielding part in the column direction
  • the maximum dimension of the cross shielding part in the row direction is larger than the maximum dimension of the first shielding part in the row direction.
  • the maximum size of the second shielding portion in the row direction is larger than the maximum dimension of the second shielding portion in the row direction.
  • the orthographic projection of the spacer on the second substrate is located in a central area of the orthographic projection of the cross shielding portion on the second substrate
  • the distance between the edge of the orthographic projection of the spacer on the second substrate and the edge of the orthographic projection of the cross shielding portion on the second substrate is a sixth distance, and the sixth distance
  • the ratio of the pitch to the first width of the first electrode strips is 11 to 33.
  • the orthographic projection of the transistor on the first substrate is located within the orthographic projection of the first shielding portion on the first substrate, and the pixel electrode having a first failure region, the first failure region is connected with the second pole through a second via structure; wherein, the orthographic projection of the first failure region on the first substrate is located on the first In the orthographic projection of the shielding portion on the first substrate, the ratio of the size of the first failure region in the column direction to the first width of the first electrode strip is 1.5 to 5.5.
  • the pixel electrode further has a second invalid area, and an orthographic projection of the second invalid area on the first substrate is located on the second shielding portion on the within the orthographic projection on the first substrate, where,
  • the liquid crystal molecules are negative liquid crystal molecules, and the ratio of the size of the second dead region in the row direction to the first width of the first electrode strip is 0.3 to 0.5; or
  • the liquid crystal molecules are positive liquid crystal molecules, and the ratio of the size of the second dead region in the row direction to the first width of the first electrode strip is 2 to 5.5.
  • a third aspect of the present disclosure provides a display device including the display panel described in any one of the above.
  • FIG. 1 shows a schematic structural diagram of an electrode structure in the related art
  • FIG. 2 shows a schematic structural diagram of an electrode structure according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic structural diagram of an electrode structure according to another embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a partial structure of a display panel according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of an array substrate in a display panel according to an embodiment of the present disclosure
  • FIG. 6 shows an enlarged schematic view of the transistor shown in FIG. 5;
  • Fig. 7 shows the enlarged schematic diagram of part A in Fig. 5;
  • Fig. 8 shows the enlarged structural schematic diagram of part B in Fig. 5;
  • FIG. 9 is a schematic diagram showing the positional relationship between the spacer and the array substrate described in the embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of the positional relationship between the array substrate, the blocking layer and the black matrix shown in FIG. 5;
  • FIG. 11 shows a schematic structural diagram of the shielding layer shown in FIG. 10 .
  • Electrode structure 11. Slit;
  • the pattern of the electrode structure 10 in the liquid crystal display panel is designed to have a slit 11 inside, and the slit 11 is closed around it, as shown in FIG. Poor display.
  • the present disclosure provides an electrode structure, which can be used in a liquid crystal display panel and can be used as a pixel electrode or a common electrode of the liquid crystal display panel; for example, the electrode structure can be an ITO electrode.
  • the electrode structure may include a first electrode part 20 , a conductive connection part 22 and a second electrode part 21 arranged in sequence in the first direction Y; wherein:
  • the first electrode part 20 may include a first connection bar 201 extending in the first direction Y and a plurality of first electrode bars 202 arranged at intervals in the first direction Y, and the first connection bar 201 has a direction in the second direction X
  • a plurality of first electrode strips 202 are located on the first side of the first connection strips 201 and connected to the first connection strips 201 , and the adjacent first electrode strips 202 are away from the first connection
  • the ends of the strips 201 are in an opening shape, that is, there is no connection between the ends of the adjacent first electrode strips 202 that are far away from the first connection strips 201 .
  • first electrode strips 202 are arranged at intervals in the first direction Y, which means that there is a first gap S1 between adjacent first electrode strips 202, and the first gap S1 is in the form of a first gap S1. semi-open.
  • the second electrode part 21 includes a second connection bar 211 extending in the first direction Y and a plurality of second electrode bars 212 arranged at intervals in the first direction Y, and the second connection bars 211 are located on the first side away from the second
  • the second connecting bar 211 has a third side and a fourth side opposite in the second direction X, and the third side is located at the position where the fourth side is close to the first side.
  • the second direction X and the The first direction Y is perpendicular to each other; the plurality of second electrode bars 212 are located on the third side of the second connection bars 211 and connected to the second connection bars 211 , and the ends of the adjacent second electrode bars 212 that are far away from the second connection bars 211 There is an opening shape between the parts, that is, there is no connection between the end parts of the adjacent second electrode strips 212 that are far away from the second connection strips 211 .
  • the aforementioned plurality of second electrode strips 212 are arranged at intervals in the first direction Y, which means that there is a second gap S2 between adjacent second electrode strips 212, and the second gap S2 is in the shape of a second gap S2. semi-open.
  • the conductive connection portion 22 is located between the first electrode portion 20 and the second electrode portion 21 , and two ends of the conductive connection portion 22 are respectively connected to the first connection bar 201 and the second connection bar 211 .
  • the first electrode part 20 and the second electrode part 21 of the electrode structure with the semi-open first slit S1 and the second slit S2, respectively, the first slit S1 and the second slit S2 Liquid crystal molecules can also be deflected at the opening of the slit S2; therefore, compared with the electrode structure that is closed around the slit shown in FIG. 1 , the light efficiency around the electrode structure can be improved.
  • the light efficiency around the electrode structure can be improved.
  • the opening direction of one of the first slit S1 of the first electrode part 20 and the second slit S2 of the second electrode part 21 is oriented to the right, and the opening direction of the other is oriented to the left; that is, the first electrode
  • the openings of the first slit S1 of the electrode part 20 and the second slit S2 of the second electrode part 21 are opposite to each other, so that the light effect of the electrode structure on both sides of the second direction X (ie: the left and right sides in FIG. 2 ) can be balanced. , so that the peripheral light effect of the electrode structure is more balanced, so as to improve the display effect.
  • the orthographic projections of the first electrode portion 20 , the second electrode portion 21 and the conductive connection portion 22 on the reference plane overlap each other, and the overlap mentioned here refers to the complete overlap within the allowable range of errors.
  • the design difficulty of the electrode structure can be reduced, thereby facilitating the arrangement of a plurality of electrode structures in the array substrate, but it is not limited to this. Coincidence, on a case-by-case basis.
  • the reference plane mentioned in the present disclosure is a plane perpendicular to the first direction Y.
  • the first electrode strips 202 and the second electrode strips 212 mentioned above may be parallel to each other, that is, the extension directions of the first electrode strips 202 and the second electrode strips 212 are parallel to each other, so as to balance the first electrode portion 20 and the second electrode strip 212.
  • Light effect at the electrode portion 21 Specifically, the extending directions of the first electrode strips 202 and the second electrode strips 212 may be parallel to each other with the third direction Q, which intersects the first direction Y and the second direction X, that is, the third direction Q is not parallel or collinear with the first direction Y and the second direction X, so the design can reduce the color shift and improve the display effect.
  • the acute angle between the third direction Q and the second direction X may be 5° to 15°, such as 5°, 7°, 9°, 11°, 13°, 15° and so on.
  • the first width of the first electrode strip 202 may be equal to the first width of the second electrode strip 212; in addition, the first width of the first slit S1 may be equal to the first width of the second slit S2, so that the The light effects at the first electrode part 20 and the second electrode part 21 are further balanced to improve the display effect of the product.
  • the first width mentioned in the present disclosure refers to the dimension in the fourth direction P, and the fourth direction P and the third direction Q are perpendicular to each other.
  • the first width of the first electrode strip 202 in order to ensure that the liquid crystal molecules at the first electrode part 20 and the second electrode part 21 are well deflected, so as to improve the light efficiency at the first electrode part 20 and the second electrode part 21; the first width of the first electrode strip 202, The first width of the first slit S1, the first width of the second electrode strip 212 and the first width of the second slit S2 must meet certain requirements; that is, the first width of the first slit S1 and the first width of the first electrode strip 202
  • the ratio of the first widths may be 1 to 4, such as: 1, 1.5, 2, 2.5, 3, 3.5, 4, and so on.
  • the first widths of the first electrode strips 202 and the second electrode strips 212 in the embodiment of the present disclosure may be 1.8 ⁇ m to 3 ⁇ m, for example: 1.8 ⁇ m, 2 ⁇ m, 2.2 ⁇ m, 2.4 ⁇ m, 2.6 ⁇ m, 2.8 ⁇ m, 3 ⁇ m and so on;
  • the first width of the first slit S1 and the second slit S2 may be 3 ⁇ m to 7 ⁇ m, such as: 3 ⁇ m, 3.5 ⁇ m, 4 ⁇ m, 4.5 ⁇ m, 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m, 6.5 ⁇ m, 7 ⁇ m and so on.
  • the second width of the first connection bar 201 and the second width of the second connection bar 211 can be equal.
  • the second widths of the first connection bars 201 and the second connection bars 211 may be equal to the first widths of the first electrode bars 202 and the second electrode bars 212 , but are not limited thereto, and may also be slightly larger than the first electrode bars 202 and the first width of the second electrode strip 212, so as to improve the light efficiency, and also improve the situation that the first connection strip 201 and the second connection strip 211 are easily disconnected due to the too small first width of the first connection strip 201 and the second connection strip 211. product yield.
  • the second width mentioned in the embodiments of the present disclosure is the dimension in the second direction X.
  • the first electrode part 20 and the second electrode part 21 of the aforementioned electrode structure are connected by the conductive connection part 22.
  • the area of the conductive connecting portion 22 is designed to be larger, so as to avoid the situation that it is easily broken and lead to pixel failure.
  • the area of the conductive connecting portion 22 in the embodiment of the present disclosure is larger than that of the first electrode.
  • the area of the strip 202 and the area of the second electrode strip 212 is larger than that of the first electrode.
  • the overall extending direction of the conductive connection portion 22 may also be parallel to the third direction, so as to reduce the difficulty of processing and design.
  • the orthographic projection of the conductive connection portion 22 on the reference plane coincides with the orthographic projection of the first electrode portion 20 and the second electrode portion 21 on the reference plane, in order to make the area of the conductive connection portion 22 larger than that of the first electrode
  • the areas of the strips 202 and the second electrode strips 212 in this embodiment can make the first width of the first electrode strips 202 and the first width of the second electrode strips 212 smaller than the first width of the entire conductive connection portion 22 .
  • the conductive connection portion 22 may include a first conductive connection bar 221 , a second conductive connection bar 222 and at least two third conductive connection bars 223 ; Both the connection bars 221 and the second conductive connection bars 222 extend in the first direction Y, and the first conductive connection bars 221 and the second conductive connection bars 222 are arranged at intervals in the second direction X, and the first conductive connection bars 221 and The first connection bar 201 is connected, the second conductive connection bar 222 is connected to the second connection bar 211; at least two third conductive connection bars 223 are arranged at intervals in the first direction Y, and are located between the first conductive connection bar 221 and the second connection bar 223.
  • each third conductive connecting bar 223 (ie, the two ends in the extending direction) are respectively connected with the first conductive connecting bar 221 and the second conductive connecting bar 222, that is, In other words, there is a third gap S3 between the adjacent third conductive connecting strips 223, and the third gap S3 is closed around.
  • the loss of light efficiency above the conductive connection portion 22 can be reduced, thereby improving the overall light efficiency of the electrode structure.
  • the first electrode part 20 and the second electrode part 21 can be connected and conducted through at least two wires (ie, the third conductive connecting bar 223 ), so that even if Partical causes one of the wires to be disconnected, there are still other wires.
  • the first electrode part 20 and the second electrode part 21 are connected and turned on, so that the occurrence rate of pixel failure can be greatly reduced, that is, the product yield can be improved.
  • two third conductive connecting strips 223 are provided, which can appropriately reduce the proportion of the conductive connecting parts 22 in the electrode structure while ensuring stable connection between the first electrode part 20 and the second electrode part 21 . That is: to provide more design space for the first electrode part 20 and the second electrode part 21, in other words, the area of the first electrode part 20 and the second electrode part 21 can be larger than the area of the conductive connection part 22, because the first electrode part 20 and the second electrode part 21 can be The gap between the first electrode part 20 and the second electrode part 21 is of a semi-open design, while the gap of the conductive connection part 22 is of a closed design.
  • the light efficiency of the first electrode part 20 and the second electrode part 21 is better than that of the conductive connection part 22 In this way, by making the area of the first electrode part 20 and the second electrode part 21 larger than that of the conductive connection part 22, the overall light efficiency of the electrode structure can be improved, and the product quality can be improved.
  • the opening of the third slit S3 it can also alleviate the situation that the Partical falls on the conductive connection part 22 during the manufacturing process, so as to alleviate the situation that the resistance value of the conductive connection part 22 increases due to the Partical, thereby reducing the driving of the pixel. Impact.
  • the number of the third conductive connecting strips 223 is not limited to two, but may also be set to three, four, etc., depending on the specific situation.
  • the length of the first conductive connection bar 221 and the length of the second conductive connection bar 222 are both smaller than the length of the first connection bar 201 and the length of the second connection bar. 211 in length. It should be understood that the length mentioned here is the dimension in the first direction Y. FIG.
  • the second width of the first conductive connection bar 221 may be equal to the second width of the first connection bar 201
  • the second width of the second conductive connection bar 222 may be equal to the second width of the second connection bar 211 .
  • the extending direction of the third conductive connection bar 223 and the third direction Q are parallel to each other.
  • the first width of the third conductive connecting strips 223 may be equal to the first width of the first electrode strips 202 ; in addition, the third gap S3 between the adjacent third conductive connecting strips 223 may be the same as that of the adjacent first electrodes.
  • the first gap S1 between the strips 202 and the second gap S2 between the adjacent second electrode strips 212 are equal, so that the light effects at the conductive connection portion 22 and the first electrode portion 20 and the second electrode portion 21 can be balanced. , in order to improve the product display effect.
  • the fourth gap S4 between the third conductive connection bar 223 and the first electrode bar 202 , the fifth gap S5 between the third conductive connection bar 223 and the second electrode bar 212 and the aforementioned first gap S1 , the second slit S2 , and the third slit S3 are all equal to balance the light effects at the conductive connection portion 22 , the first electrode portion 20 , the second electrode portion 21 and between the three, thereby improving the display effect of the product.
  • the conductive connection portion 22 may be a conductive connection bar extending in the third direction Q, wherein the first width of the conductive connection bar is the same as the first width of the conductive connection bar.
  • the ratio of the first width of an electrode strip 202 may be 1.5 to 5.5, that is to say, the conductive connection portion 22 is wider than the first electrode strip 202 to improve the situation that the conductive connection portion 22 is easily broken. Guarantee product quality.
  • the first width of the conductive connection bar may be 5 ⁇ m to 10 ⁇ m, such as 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m and so on.
  • the first electrode part 20 further includes a signal connection bar 203 located on the first side of the first connection bar 201 and connected to the first connection bar 201 , and It is located on the side of the plurality of first electrode strips 202 away from the conductive connection portion 22 .
  • the signal connection bar 203 can be connected to a common line in the array substrate, that is, the signal connection bar 203 can be used to receive a common signal; but not limited to this
  • the signal connection bar 203 can also be connected to the source and drain electrodes of the transistors in the array substrate for receiving signals transmitted from the source and drain electrodes, such as data signals.
  • FIG. 2 and FIG. 3 have no practical significance, and are only for the purpose of distinguishing the aforementioned structures, so as to facilitate the understanding of the positional relationship between the aforementioned structures. It should be understood that, The electrode structure mentioned in the embodiments of the present disclosure is an integral structure as a whole.
  • the present disclosure also provides a display panel, which may be a liquid crystal display panel; as shown in FIG. 4 , the display panel may include an array substrate 3 , an opposite substrate 4 arranged in a cell with the array substrate 3 , and an array substrate 4 located on the opposite substrate. 4.
  • the liquid crystal molecules 5 may be negative liquid crystal molecules, but not limited thereto, and may also be positive liquid crystal molecules.
  • the plurality of spacers 6 may include a main spacer and an auxiliary spacer. When the display panel does not receive external pressure, both ends of the main spacer can be in contact with the array substrate 3 and the opposite substrate 4 respectively. , mainly plays a supporting role; and when the auxiliary spacer does not receive external pressure on the display panel, if the auxiliary spacer is formed on the opposite substrate 4 , there is a certain distance between the auxiliary spacer and the array substrate 1 .
  • the thickness of the display panel can be fine-tuned by adjusting the level difference between the main spacer and the auxiliary spacer.
  • the height of the main spacer is greater than the height of the auxiliary spacer.
  • the two main spacers and auxiliary spacers may be arranged according to a certain period.
  • the size and height of different types of spacers need to be monitored during the manufacturing process. Because the size of the spacer is small, and there are generally fewer main spacers, it is difficult for the equipment to accurately identify the position of the main spacer depending on the size alone.
  • a space around the main spacer is designed to be vacant (ie: Do not set any spacers) to facilitate quicker and more accurate identification of the main spacer position and monitor it. For example, in the design, no spacer is set under the main spacer. When monitoring, you can first Quickly determine the position where no spacer is provided, and then the aforementioned design rules can make it clear that the spacer at the upper position without any spacer is the main spacer.
  • the array substrate 3 may include a first substrate 30 and a plurality of sub-pixel units, a plurality of rows of scan lines 31 , a plurality of rows of common lines 32 , and a plurality of columns of data lines 33 formed on the first substrate 30 . ,in:
  • the first substrate 30 may have a plurality of sub-pixel regions 301 arranged in an array along the row direction X and the column direction Y, a first wiring region 302 located between two adjacent rows of sub-pixel regions 301 , and For the second wiring area 303 located between two adjacent columns, there is overlap between the first wiring area 302 and the second wiring area 303 .
  • the first substrate 30 can be a single-layer structure, and the material of the first substrate 30 can be glass. But not limited to this, the first substrate 30 can also have a multi-layer structure; and the material of the first substrate 30 is not limited to glass, and can also be other materials, such as polyimide (PI) and other materials, depending on the specific situation Depends.
  • PI polyimide
  • each sub-pixel unit includes a pixel electrode 34 located at least partially in the sub-pixel region 301 , a common electrode 35 , and a transistor 36 located at least partially in the first wiring region 302 .
  • a capacitor (not shown in the figure) may also be included in the sub-pixel unit.
  • the transistor 36 may include an active layer 360 , a gate electrode 361 , and a first electrode 362 and a second electrode 363 disposed in the same layer; wherein, the gate electrode 361 and the active layer
  • An insulating layer 37 can also be arranged between the 360 to insulate the gate 361 and the active layer 360 from each other.
  • the insulating layer 37 can be made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials. It should be noted that the gate electrode 361 may be disposed in the same layer as the scan line 31 , and the gate electrode 361 may belong to a part of the aforementioned scan line 31 .
  • the transistor 36 may be a top-gate type or a bottom-gate type.
  • the transistor 36 is mainly of bottom gate type as an example for description.
  • the gate 361 is formed on the first substrate 30, and the gate 361 may include a metal material or an alloy material, such as molybdenum, aluminum, titanium, etc., to ensure its good electrical conductivity;
  • the insulating layer is formed on the first substrate 30 and covers the gate electrode 361, and the insulating layer can be made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials;
  • the active layer 360 is formed on the insulating layer away from the first On one side of the substrate 30, the first electrode 362 and the second electrode 363 are respectively connected to the two doped regions of the active layer 360.
  • the first electrode 362 and the second electrode 363 may include metal materials or alloy materials, such as molybdenum,
  • the number of transistors 36 in the sub-pixel unit can be set to be multiple, and the transistors 36 are further classified into N-type and P-type.
  • the pixel electrode 34 may be connected to the first electrode 362 ; wherein, when the transistor 36 connected to the pixel electrode 34 is an N-type, the first electrode 362 of the transistor 36 may be a drain electrode, and the second electrode may be a drain electrode. 363 can be a source electrode; when the transistor 36 connected to the pixel electrode 34 is a P-type, the first electrode 362 of the transistor 36 can be a source electrode, and the second electrode 363 can be a drain electrode.
  • the orthographic projection of the common electrode 35 on the first substrate 30 overlaps with the orthographic projection of the pixel electrode 34 on the first substrate 30 .
  • the pixel electrode 34 and the common electrode 35 is the electrode structure described in any of the foregoing embodiments, so that the light efficiency around the pixel can be improved and the product quality can be improved.
  • the row direction X mentioned in this embodiment may be parallel to the aforementioned second direction X
  • the column direction Y may be the aforementioned first direction Y.
  • the pixel electrode 34 may be located on the side of the common electrode 35 close to the first substrate 30, that is, the pixel electrode 34 may be fabricated on the first substrate 30 before the common electrode 35; for example, while In other words, the pixel electrode 34 can be a plate-shaped electrode; that is, the pixel electrode 34 is a whole piece without a slit; and the common electrode 35 can be the electrode structure described in any of the foregoing embodiments; The electric field generated between the electrodes 35 deflects all the liquid crystal molecules between the electrodes and directly above the electrodes, which can improve the working efficiency of the liquid crystal and increase the light transmission efficiency. But not limited to this, the pixel electrode 34 can also be located on the side of the common electrode 35 away from the first substrate 30, the pixel electrode 34 is the electrode structure described in any of the foregoing embodiments; the common electrode 35 is a plate electrode.
  • the pixel electrode 34 is mainly located on the side of the common electrode 35 close to the first substrate 30 , and the pixel electrode 34 can be a plate-shaped electrode; and the common electrode 35 can be any of the aforementioned embodiments.
  • the described electrode structure is illustrated as an example.
  • the pixel electrode 34 can be made of ITO material, but it is not limited to this, and can also be made of transparent materials such as indium zinc oxide (IZO), zinc oxide (ZnO), etc.; That is to say, since the material used for the pixel electrode 34 is different from that of the gate electrode 361 , the first electrode 362 and the second electrode 363 of the transistor 36 , the pixel electrode 34 is different from the gate electrode 361 , the first electrode 362 and the second electrode 363 of the transistor 36 .
  • the second pole 363 can be fabricated by using different patterning processes.
  • the pixel electrode 34 may be located on the side of the first electrode 362 and the second electrode 363 of the transistor 36 close to the first substrate 30. As shown in FIG. 5, the pixel electrode 34 may be connected to the transistor through the second via structure H2. The first pole 362 of 36 is connected. The pixel electrode 34 can be formed on the first substrate 30 before the gate electrode 361 of the transistor 36 is formed. That is, when fabricating the array substrate, a patterning process can be used to form the pixel electrode on the first substrate 30 first. 34 , and then another patterning process is used to form the gate 361 of the transistor 36 on the first substrate 30 .
  • the pixel electrode 34 and the gate electrode 361 are both formed on the first substrate 30, the pixel electrode 34 and the gate electrode 361 are disconnected from each other (ie, not connected). But not limited thereto, the pixel electrode 34 may also be formed on the first substrate 30 after the gate electrode 361 of the transistor 36 is formed, and the pixel electrode 34 may also be located on the side of the gate electrode 361 away from the first substrate 30 .
  • the common electrode 35 can also be made of transparent conductive materials such as ITO; the common electrode 35 can be formed on the first electrode 362 and the second electrode 363 of the transistor 36 away from the first lining On one side of the bottom 30 , it should be understood that there is an insulating layer between the common electrode 35 and the first electrode 362 and the second electrode 363 of the transistor 36 .
  • At least one row of scan lines 31 may be located in a first wiring area 302, in other words, at least one row of scan lines 31 may be disposed in each first wiring area 302; wherein, the scan lines 31 and the gates 361 of the transistors 36 in the sub-pixel unit
  • the aforementioned scan line 31 and the gate electrode 361 of the transistor 36 can be disposed in the same layer and have an integrated structure, and the scan line 31 is configured to provide scan signals to the sub-pixel units.
  • At least one row of common lines 32 may be located in a first wiring area 302, in other words, at least one row of common lines 32 may be provided in each first wiring area 302; wherein, the common lines 32 are connected to the common electrodes 35, which are configured to The sub-pixel unit provides a common signal; for example, the common line 32 can be arranged in the same layer as the scan line 31, that is, the common line 32 can be located on the side of the common electrode 35 close to the first substrate 30, as shown in FIG.
  • the common line 32 can be connected to the common electrode 35 through the first via structure H1; specifically, the common line 32 can be connected to the signal connection bar of the common electrode 35 through the first via structure H1; it should be understood that this signal
  • the connection bars may be located within the first wiring area 302 .
  • the common line 32 has a first segment 320 located outside the second wiring region 303 and within the first wiring region 302 , and the first segment 320 is in the row direction X They can be arranged at intervals and connected by a second segment 321 , a part of the second segment 321 is located in the second wiring area 303 , and the other part is located in the first wiring area 302 .
  • the first segment 320 of the common line 32 may have a first portion 3201 , a second portion 3202 and a third portion 3203 arranged in sequence in the row direction X, and the third portion 3203 is far away from the scanning
  • the side of the line 31 is farther from the scan line 31 than the side of the first part 3201 far from the scan line 31, and the side of the second part 3202 farther from the scan line 31 is closer to the scan line than the side of the first part 3201 far from the scan line 31 31, and a gap a is formed between the side of the second portion 3202 away from the scan line 31 and the first portion 3201 and the third portion 3203;
  • the size of the third part 3203 in the column direction Y is larger than the size of the first part 3201 in the column direction Y, that is, the third part 3203 is protruded from the first part 3201;
  • the dimension of the second part 3202 in the column direction Y is smaller than the dimension of
  • the orthographic projection of the first via structure H1 on the first substrate 30 overlaps with the orthographic projections of the second portion 3202 and the third portion 3203 on the first substrate 30 ,
  • the other part overlaps with the orthographic projection of the notch a on the first substrate 30.
  • This relationship can be understood as the first via structure H1 at the common line 32 is a half-via design, that is: the first via structure H1 A part is orthographically projected on the common line 32, and the other part is projected at the gap a.
  • This design can improve the diffusion uniformity of the alignment layer PI while ensuring that the first via structure H1 is located on the common line 32.
  • the distance between the boundary line of the first via structure H1 and the boundary line of the third part 3203 in the column direction Y is the third distance
  • the boundary line of the first via structure H1 and the boundary line of the third part 3203 are far away from the second distance
  • the distance between the boundary line of the part 3202 in the row direction X is the fourth distance
  • the distance between the boundary line of the first via structure H1 and the boundary line of the second part 3202 away from the third part 3203 in the row direction X is the fifth distance spacing, wherein, in order to ensure that the first via structure H1 can be formed on the common line 32, the ratio of the aforementioned third spacing, fourth spacing and fifth spacing to the first width of the first electrode strip 202 can be 1 to 6, such as: 1, 2, 3, 4, 5, 6, etc.
  • the third pitch, the fourth pitch and the fifth pitch may be 3 ⁇ m to 10 ⁇ m, such as: 3 ⁇ m, 5 ⁇ m, 7 ⁇ m, 10 ⁇ m, etc. Wait.
  • each first wiring area 302 may be provided with a row of scan lines 31 and a row of common lines 32. It should be understood that the scan lines 31 and the common lines 32 are disconnected from each other, That is, the orthographic projection of the scan line 31 on the first substrate 30 and the orthographic projection of the common line 32 on the first substrate 30 do not overlap. It should be noted that the first wiring area 302 is not limited to one row of scan lines 31 and one row of common lines 32, but also two rows of scan lines 31, or no common lines 32, etc., depending on the specific situation. The embodiments of the present disclosure are mainly described with one row of scan lines 31 and one row of common lines 32 disposed in each of the first wiring regions 302 .
  • At least one column of data lines 33 can be located in a second wiring region 303, in other words, at least one column of data lines 33 is disposed in each second wiring region 303, and this data line 33 can be connected to the second electrode 363 of the transistor 36 in the sub-pixel unit , which is configured to provide data signals to the sub-pixel units.
  • the orthographic projections of the data lines 33 on the first substrate 30 overlap with the orthographic projections of the scan lines 31 and the common lines 32 on the first substrate 30 .
  • the data line 33 in the embodiment of the present disclosure can be disposed in the same layer as the first electrode 362 and the second electrode 363 of the transistor 36 in the sub-pixel unit, that is, it can be fabricated by the same patterning process, so as to reduce the mask Cost; but not limited to this, it can also be made by different patterning processes, depending on the specific situation.
  • a column of data lines 33 can be arranged in each second wiring area 303, and the data lines 33 can be connected to the second poles 363 of the sub-pixel units in the same column, that is, the data Line 33 may provide data signals for the same column of sub-pixel cells.
  • each column of data lines 33 may be arranged symmetrically with respect to the central axis. It should be noted that the central axis mentioned here is a line passing through the center of the data lines 33 and extending in the column direction Y.
  • the distance between the two adjacent first poles 362 located on opposite sides of the data line 33 in the row direction X and the data line 33 in the row direction X may be equal to ensure that the data line 33 and the transistors 36 on both sides are equal.
  • the coupling capacitances are close to the same, thereby ensuring the uniformity of light effects on both sides of the data line 33 .
  • the pixel electrodes 34 located on opposite sides of the data line 33 in the row direction X and adjacent to each other can be symmetrically arranged with respect to the data line 33, and the two adjacent pixel electrodes 34 located on the opposite sides of the data line 33 in the row direction X and adjacent to each other
  • the electrodes 35 are symmetrically arranged with respect to the data lines 33 to ensure that the coupling capacitances between the data lines 33 and the pixel electrodes 34 and the common electrodes 35 on both sides are approximately the same, thereby ensuring uniformity of light efficiency on both sides of the data lines 33 .
  • the distance between the first pole 362 of each sub-pixel unit and the data line 33 connected to it in the row direction X is equal to ensure that the transistors 36 and data of each sub-pixel unit in each column are equal.
  • the coupling capacitances between the lines 33 are close to the same, so as to ensure the uniformity of light efficiency at each sub-pixel unit in each column. It should be noted that, when the distance between the first pole 362 of each sub-pixel unit in a column of sub-pixel units and the data line 33 connected thereto in the row direction X is equal, the first pole 362 of the column overlaps with the gate 361 The area needs to be consistent with the other columns.
  • the alignment portion 330 is located in the overlapping area of the first wiring area 302 and the second wiring area 303 , and The orthographic projection of the alignment portion 330 on the first substrate 30 does not coincide with the orthographic projection of the common line 32 and the scanning line 31 on the first substrate 30; wherein, as shown in FIG.
  • the orthographic projection of the first substrate 30 is located within the orthographic projection of the pair of position portions 330 on the first substrate 30, that is, the outer contour of the orthographic projection of the spacer 6 on the first substrate 30 is located in the opposite direction.
  • the inner side of the orthographically projected outer contour of the position portion 330 on the first substrate 30 ensures the flatness of the place where the spacer 6 is supported, so as to ensure that the spacer 6 is stably supported on the array substrate.
  • the scan lines 31 around the alignment portion 330 are of anisotropic design, and the pattern of the scan lines 31 is kept symmetrical with respect to the data lines 33 as much as possible to ensure the uniformity of light effects on both sides of the data lines 33 .
  • the maximum size of the alignment portion 330 in the data line 33 in the row direction X is larger than the maximum size of other parts in the row direction X; in the embodiment of the present disclosure, by placing the alignment portion 330 in the data line 33 in the row direction
  • the dimension in the direction X is designed to be larger to ensure the flatness of the place where the spacer 6 is supported.
  • the pixel aperture ratio can be increased.
  • the orthographic projection of the alignment portion 330 on the first substrate 30 is located on the first substrate 30 .
  • the scan lines 31 and the common lines 32 in the same first wiring area 302
  • metal blocks exist in the four directions of the upper, lower, left and right directions of the alignment portion 330 projected by the spacer 6, that is, there is an overlap of the scan line 31 and the data line 33 above. part, there is a part where the common line 32 and the data line 33 overlap, and a transistor 36 exists on the left and right, that is to say, the thickness of the area corresponding to the spacer 6 in the array substrate 3 is smaller than that on this area.
  • the effective area refers to an area that can emit light normally, and the effective area is located in the sub-pixel area 301 .
  • the overlapping portion of the orthographic projection of the data line 33 and the scan line 31 on the first substrate 30 can be defined as the first overlapping portion 331 , which is the same as the common line 32 in the
  • the overlapping portion of the orthographic projections on the first substrate 30 can be defined as the second overlapping portion 332;
  • the dark state is not uniform.
  • the orthographic projection shape of the alignment portion 330 on the first substrate 30 mentioned in the embodiment of the present disclosure may be similar to a rhombus, an ellipse, or a hexagon, etc., depending on the specific situation. It should be noted that the number and position of the alignment portions 330 in the array substrate may match the number and position of the spacers 6 , that is, the alignment portions 330 correspond to the spacers 6 one-to-one.
  • the opposite substrate may include a second substrate (not shown) on the side of the spacer 6 away from the array substrate 3 and a second substrate on the side of the second substrate close to the array substrate 3 .
  • the shielding layer 40 has a cross shielding portion 401, a first shielding portion 402 located on opposite sides of the cross shielding portion 401 in the row direction X, and a second shielding portion 401 located on opposite sides of the cross shielding portion 401 in the column direction Y
  • the shielding part 403 it should be noted that the orthographic projection of the cross shielding part 401 on the first substrate 30 covers at least the overlapping area of the first wiring area 302 and the second wiring area 303, and the first shielding part 402 is located in the first
  • the orthographic projection on the substrate 30 at least covers the first wiring area 302 and is located outside the second wiring area 303, and the orthographic projection of the second shielding portion 403 on the first substrate 30 at least covers the second wiring area 303 and is located in the second wiring area 303.
  • the first shielding portion 402 , the second shielding portion 403 and the cross shielding portion 401 in the shielding layer 40 may be arranged in an array, and the first shielding portion 402 , the second shielding portion 402 and the second shielding portion 402 arranged in the array may be arranged in an array.
  • the portion 403 and the cross-shielding portion 401 may enclose a light-transmitting hole 404, and the orthographic projection of the light-transmitting hole 404 on the first substrate 30 is located in the sub-pixel region 301, and the light-transmitting hole 404 is used to allow light to pass through.
  • the first shielding portion 402 , the second shielding portion 403 and the cross shielding portion 401 in the shielding layer 40 can be placed on the first substrate 30 .
  • the orthographic projection of may also cover part of the sub-pixel area 301 .
  • the spacer 6 when the display panel is subjected to a large external force, especially when the impact force such as a drop test is large, the spacer 6 mainly slides in the column direction Y, because the spacer 6 is used in the data line With this design on the alignment part 330 of 33, the spacer 6 always slides above the data line 33. Due to the support of the data line 33, the spacer 6 will not scratch the effective area.
  • the second shielding portion 403 and the cross shielding portion 401 are shielded. Even if the film layer above the data line 33 (ie, the alignment film layer) is scratched and causes light leakage, it will be shielded by the second shielding portion 403 and the cross shielding portion 401. , it will not form point-like or large-area dark-state light leakage defects, and then the display effect can be improved.
  • the spacer 6 even if the spacer 6 appears to slide in the row direction X when it is under pressure, since the first shielding portion 402 and the cross shielding portion 401 are shielded above the first wiring area 302, it will not form a dot shape or a large area. The dark-state light leakage is poor, which in turn can improve the display effect.
  • the maximum size of the cross shielding portion 401 in the column direction Y may be larger than the maximum size of the first shielding portion 402 in the column direction Y, and the cross shielding portion
  • the maximum size of 401 in the row direction X is larger than the maximum size of the second shielding part 403 in the row direction X, so the design can prevent the spacer 6 from sliding out of the blocking area during the pressure test, thereby improving the problem of poor light leakage in the dark state. question.
  • the maximum size of all the cross shielding parts 401 in the column direction Y is larger than the maximum size of the first shielding part 402 in the column direction Y
  • the maximum size in the row direction X is greater than the maximum size of the second shielding portion 403 in the row direction X; only the cross shielding portion 401 corresponding to the spacer 6 can be designed in this way, and the other ones not corresponding to the spacer 6
  • the size of the cross blocking part 401 in the column direction Y may be equal to the size of the first blocking part 402 in the column direction Y
  • the size in the row direction X may be equal to the size of the second blocking part 403 in the row direction X , which can improve the pixel aperture ratio.
  • the intersecting shielding portion 401 corresponding to the spacer 6 may be approximately hexagonal, and the intersecting shielding portion 401 , the first shielding portion 402 and the second shielding portion not corresponding to the spacer 6
  • the portion 403 may be approximately rectangular, but not limited thereto, and may also be other shapes, depending on the specific situation.
  • the orthographic projection of the spacer 6 on the second substrate may be located in the central area of the orthographic projection of the cross shielding portion 401 on the second substrate, and the orthographic projection of the spacer 6 on the second substrate
  • the distance between the edge and the edge of the orthographic projection of the cross shielding portion 401 on the second substrate is a sixth distance
  • the ratio of the sixth distance to the first width of the first electrode strip 202 is 11 to 33, for example: 11 , 17, 23, 28, 33, etc.
  • the sixth pitch can be 35 ⁇ m to 60 ⁇ m, such as: 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, 55 ⁇ m, 60 ⁇ m, etc.; this design can avoid the spacer 6 under pressure Slide out the occlusion area during the test, which can improve the problem of poor light leakage in the dark state.
  • the blocking layer 40 may also cover part of the pixel electrodes 34 .
  • the edge of the pixel electrode 34 is close to the scan line 31 and the data line 33 and there is a coupling electric field.
  • the liquid crystal arrangement will be disordered, resulting in a failure area, resulting in light leakage from the edge of the dark state pixel. Therefore, the shielding layer 40 is required for this part of the failure area. to block.
  • the orthographic projection of the transistor 36 of the sub-pixel unit mentioned above on the first substrate 30 may be located in the orthographic projection of the first shielding portion 402 on the first substrate 30, wherein the pixel electrode 34 of the sub-pixel unit It has a first failure region, and the first failure region is connected with the second pole 363 through the second via structure H2; wherein, the orthographic projection of the first failure region on the first substrate 30 is located at the first shielding portion 402 in the first In the orthographic projection on the substrate 30, the ratio of the size of the first failure region in the column direction Y to the first width of the first electrode strips 202 is 1.5 to 5.5; for example: 1.5, 2.5, 3.5, 4.5, 5.5, etc.
  • the size of the first invalid region in the column direction Y may be 5 ⁇ m to 10 ⁇ m, such as: 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc., that is, the first shielding portion 402 covers the pixels
  • the electrode 34 is at least 5um. It should be noted that when the color filter layer is located on the opposite substrate, considering the cell-to-cell accuracy of the upper and lower substrates, it needs to be wider, but it should not exceed 10 ⁇ m to avoid excessively affecting the pixel aperture ratio.
  • a coupling electric field also exists between the data line 33 and the edge of the pixel electrode 34 , that is to say, the pixel electrode 34 in the embodiment of the present disclosure also has a second dead area, and the orthographic projection of the second dead area on the first substrate 30 can be It is located in the orthographic projection of the second shielding portion 403 on the first substrate 30; wherein, the liquid crystal molecules 5 are negative liquid crystal molecules, the electric field will not cause the liquid crystal to rotate, and the size of the second failure area in the row direction X is the same as
  • the ratio of the first width of the first electrode strip 202 is 0.3 to 0.5, such as: 0.3, 0.4, 0.5, etc.
  • the size of the second failure region in the row direction X can be 1 ⁇ m, that is, The second shielding portion 403 covers the pixel electrode 341 ⁇ m to shield the shadow area near the data line 33 .
  • the liquid crystal molecules 5 are positive liquid crystal molecules, the coupled electric field between the data lines 33 and the pixel electrodes 34 will not cause obvious dark light leakage, but will cause the liquid crystal molecules to cause aggravation of the Crosstalk (crosstalk) phenomenon. Therefore, at this time, , the ratio of the size of the second invalid region of the pixel electrode 34 in the row direction X to the first width of the first electrode strip 202 may be 2 to 5.5, for example: 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, etc.
  • the size of the second failure area in the row direction X may be 6 ⁇ m to 10 ⁇ m, such as: 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, etc., that is, the coverage of the second shielding portion 403
  • the pixel electrode 34 is at least 6um to block the coupled electric field area.
  • the color filter layer used in the liquid crystal display panel may be located on the opposite substrate 4 or on the array substrate 3, depending on the specific situation.
  • Embodiments of the present disclosure also provide a display device including the display panel described in any of the above embodiments.
  • the display device may be a liquid crystal display device.
  • the specific type of the display device is not particularly limited, and any type of display device commonly used in the art can be used, such as liquid crystal display screens, mobile devices such as mobile phones and notebook computers, wearable devices such as watches, VR The device, etc., can be selected by those skilled in the art according to the specific use of the display device, which will not be repeated here.
  • the display device also includes other necessary components and components. Taking the display as an example, it may also include a backlight module, a casing, a main circuit board, a power cord, etc., which are well understood in the art. It is desirable to make corresponding supplements according to the specific usage requirements of the display device, which will not be repeated here.
  • on may mean that one layer is directly formed or disposed on another layer, or may mean that a layer is formed directly on or disposed on another layer.
  • a layer is formed or disposed indirectly on another layer, ie there are other layers in between.
  • the term “same layer arrangement” is used to mean that two layers, components, components, elements or sections may be formed by the same patterning process, and that the two layers, components, components , elements or parts are generally formed of the same material.
  • patterning process generally includes steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-shot patterning process means a process of forming patterned layers, features, members, etc. using one mask.

Abstract

一种电极结构、显示面板及显示装置。电极结构包括：第一电极部(20)，包括在第一方向(Y)上延伸的第一连接条(201)以及在第一方向(Y)上间隔排布的多个第一电极条(202)，第一连接条(201)具有在第二方向(X)上相对的第一侧和第二侧，多个第一电极条(202)位于第一连接条(201)的第一侧并与第一连接条(201)连接，且相邻第一电极条(202)中远离第一连接条(201)的端部之间呈开口状；第二电极部(21)，与第一电极部(20)在第一方向(Y)上间隔排布，第二电极部(21)包括在第一方向(Y)上延伸的第二连接条(211)以及在第一方向(Y)上间隔排布的多个第二电极条(212)，第二连接条(211)位于第一侧远离第二侧的位置，第二连接条(211)具有在第二方向(X)上相对的第三侧和第四侧，第三侧位于第四侧靠近第一侧的位置；多个第二电极条(212)位于第二连接条(211)的第三侧并与第二连接条(211)连接，且相邻第二电极条(212)的远离第二连接条(211)的端部之间呈开口状；导电连接部(22)，位于第一电极部(20)与第二电极部(21)之间，导电连接部(22)的两端分别与第一连接条(201)和第二连接条(211)连接；且导电连接部(22)的面积大于第一电极条(202)的面积和第二电极条(212)的面积。电极结构在提高像素光效及透过率的同时，还可降低制造过程中的断线不良，提高生产良率。

Description

电极结构、显示面板及显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种电极结构、显示面板及显示装置。
背景技术
随着液晶面板的不断发展，高分辨率的产品被不断开发；目前，为了提高像素光效及透过率，将阵列基板上的ITO(氧化铟锡)电极结构制作的越来越小、越来越细，这样使其极易在制造过程中受到杂质颗粒(Partical)的影响，从而极易形成断线等不良情况，导致像素失效，降低了产品良率。
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种电极结构、显示面板及显示装置，在提高像素光效及透过率的同时，还可降低制造过程中的断线不良，提高生产良率。
本公开第一方面提供了一种电极结构，其包括：
第一电极部，包括在第一方向上延伸的第一连接条以及在所述第一方向上间隔排布的多个第一电极条，所述第一连接条具有在第二方向上相对的第一侧和第二侧，所述多个第一电极条位于所述第一连接条的第一侧并与所述第一连接条连接，且相邻所述第一电极条中远离所述第一连接条的端部之间呈开口状；
第二电极部，与所述第一电极部在所述第一方向上间隔排布，所述第二电极部包括在所述第一方向上延伸的第二连接条以及在所述第一方向上间隔排布的多个第二电极条，所述第二连接条位于所述第一侧远离所述第二侧的位置，所述第二连接条具有在所述第二方向上相对的第三侧和第四侧，所述第三侧位于所述第四侧靠近所述第一侧的位置；所述多个第二电极条位于所述第二连接条的第三侧并与所述第二连接条连接，且相邻所述第二电极条的远离所述第二连接条的端部之间呈开口状；
导电连接部，位于所述第一电极部与所述第二电极部之间，所述导电连接部的两端分别与所述第一连接条和所述第二连接条连接；且所述导电连接部的面积大于所述第一电极条的面积和所述第二电极条的面积；
其中，所述第一方向与所述第二方向相互垂直。
在本公开的一种示例性实施例中，所述第一电极部、所述第二电极部与所述导电连接部在参考平面上的正投影相互重合；其中，所述参考平面为与所述第一方向相垂直的平面。
在本公开的一种示例性实施例中，所述第一电极条、所述第二电极条、所述导电连接部的延伸方向均与第三方向相互平行，所述第一电极条的第一宽度和所述第二电极条的第一宽度相等，且所述第一电极条的第一宽度小于所述导电连接部的第一宽度；
其中，所述第一宽度为在第四方向上的尺寸，所述第三方向与所述第四方向相垂直，且所述第三方向与所述第一方向和所述第二方向均相交。
在本公开的一种示例性实施例中，所述导电连接部包括在所述第二方向上间隔排布且均在所述第一方向上延伸的第一导电连接条和第二导电连接条，以及位于所述第一导 电连接条和所述第二导电连接条之间并在所述第一方向上间隔排布的至少两条第三导电连接条，各所述第三导电连接条的两端分别与所述第一导电连接条和所述第二导电连接条连接，所述第三导电连接条的延伸方向与所述第三方向相互平行；
其中，所述第一导电连接条与所述第一连接条连接，所述第二导电连接条与所述第二连接条连接。
在本公开的一种示例性实施例中，所述第三导电连接条的第一宽度与所述第一电极条的第一宽度相等，所述第一导电连接条的第二宽度与所述第一连接条的第二宽度相等，所述第二导电连接条的第二宽度与所述第二连接条的第二宽度相等；其中，所述第二宽度为在所述第二方向上的尺寸。
在本公开的一种示例性实施例中，相邻所述第一电极条之间的缝隙为第一缝隙，相邻所述第二电极条之间的缝隙为第二缝隙，相邻所述第三导电连接条之间的缝隙为第三缝隙，所述第三导电连接条与所述第一电极条之间的缝隙为第四缝隙，所述第三导电连接条与所述第二电极条之间的缝隙为第五缝隙，其中，所述第一缝隙的第一宽度、所述第二缝隙的第一宽度、所述第三缝隙的第一宽度、所述第四缝隙的第一宽度与所述第五缝隙的第一宽度均相等。
在本公开的一种示例性实施例中，所述第一缝隙的第一宽度与所述第一电极条的第一宽度之比为1至4。
在本公开的一种示例性实施例中，所述第一导电连接条的长度和所述第二导电连接条的长度均小于所述第一连接条的长度以及小于所述第二连接条的长度，所述长度为在所述第一方向上的尺寸。
在本公开的一种示例性实施例中，所述导电连接部为一条导电连接条，所述导电连接条在所述第三方向上延伸，所述导电连接条的第一宽度与所述第一电极条的第一宽度之比为1.5至5.5。
在本公开的一种示例性实施例中，第一电极部还包括信号连接条，位于所述第一连接条的第一侧并与所述第一连接条连接，且位于所述多个第一电极条远离所述导电连接部的一侧。
本公开第二方面提供了一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板包括：
第一衬底，具有沿行方向和列方向呈阵列排布的多个子像素区、位于相邻两行所述子像素区之间的第一布线区以及位于相邻两列之间的第二布线区，所述第一布线区与所述第二布线区之间存在交叠；
多个子像素单元，形成在所述第一衬底上，每个所述子像素单元包括至少部分位于所述子像素区内的像素电极、公共电极以及至少部分位于所述第一布线区的晶体管；所述晶体管包括栅极、第一极和第二极；所述像素电极与所述第一极连接；所述公共电极在所述第一衬底上的正投影与所述像素电极在所述第一衬底上的正投影存在交叠；且所述像素电极和所述公共电极中的至少一者为上述任一项所述的电极结构，所述行方向为所述第二方向，所述列方向为所述第一方向；
多行扫描线，形成在所述第一衬底上，至少一行所述扫描线位于一所述第一布线区内，所述扫描线与所述栅极连接，被配置为向所述子像素单元提供扫描信号，
多行公共线，形成在所述第一衬底上，至少一行所述公共线位于一所述第一布线区内，所述公共线与所述公共电极连接，被配置为向所述子像素单元提供公共信号；
多列数据线，形成在所述第一衬底上，至少一列所述数据线位于一所述第二布线区内，所述数据线与所述第二极连接，被配置为向所述子像素单元提供数据信号；
其中，所述扫描线在所述第一衬底上的正投影与所述公共线在所述第一衬底上行的正投影不交叠；所述数据线在所述第一衬底上的正投影与所述扫描线和所述公共线在所 述第一衬底上的正投影存在交叠。
在本公开的一种示例性实施例中，所述公共电极位于所述像素电极远离所述第一衬底的一侧，所述公共电极为所述电极结构。
在本公开的一种示例性实施例中，至少部分列所述数据线具有对位部；所述对位部位于所述第一布线区与第二布线区的交叠区域，且所述对位部在所述第一衬底上的正投影与所述公共线和所述扫描线在所述第一衬底上的正投影不重合；其中，所述显示面板还包括：
多个隔垫物，位于所述数据线远离所述第一衬底的一侧，每个所述隔垫物在所述第一衬底上的正投影位于一所述对位部在所述第一衬底上的正投影内。
在本公开的一种示例性实施例中，每一所述第一布线区内设置有一行所述扫描线和一行所述公共线，所述对位部在所述第一衬底上的正投影位于所述扫描线和所述公共线在所述第一衬底上的正投影之间。
在本公开的一种示例性实施例中，所述数据线还具有与所述扫描线在所述第一衬底上的正投影存在交叠的第一交叠部及与所述公共线在所述第一衬底上的正投影存在交叠的第二交叠部；其中，所述第一交叠部与所述对位部在所述列方向上的间距为第一间距，所述第二交叠部与所述对位部在所述列方向上的间距为第二间距，所述第一间距和所述第二间距与所述第一电极条的第一宽度之比为1.5至17。
在本公开的一种示例性实施例中，在所述公共电极为前述所述的电极结构时，所述公共电极的信号连接条位于所述第一布线区内；
所述公共电极位于所述公共线远离所述第一衬底的一侧，所述信号连接条通过第一过孔结构与所述公共线连接；
所述公共线具有位于所述第二布线区之外且位于所述第一布线区之内的第一段，所述第一段具有在所述行方向上依次排布的第一部、第二部及第三部，所述第三部远离所述扫描线的一侧比所述第一部远离所述扫描线的一侧更远离所述扫描线，所述第二部远离所述扫描线的一侧比所述第一部远离所述扫描线的一侧更靠近所述扫描线，且所述第二部远离所述扫描线的一侧与所述第一部和所述第三部之间形成有缺口；
其中，所述第一过孔结构在所述第一衬底上的正投影的部分与所述第二部和所述第三部在所述第一衬底上的正投影存在交叠，另一部分与所述缺口在所述第一衬底上的正投影存在交叠；且所述第一过孔结构的边界线与所述第三部的边界线在所述列方向上的间距为第三间距，所述第一过孔结构的边界线与所述第三部中远离所述第二部的边界线在所述行方向上的间距为第四间距，所述第一过孔结构的边界线与所述第二部中远离所述第三部的边界线在所述行方向上的间距为第五间距，所述第三间距、所述第四间距及所述第五间距与所述第一电极条的第一宽度之比为1至6。
在本公开的一种示例性实施例中，每列数据线与一列子像素单元中各所述子像素单元的晶体管的第一极连接。
在本公开的一种示例性实施例中，位于所述数据线在所述行方向上相对两侧且相邻的两个第一极与所述数据线在所述行方向上的间距相等。
在本公开的一种示例性实施例中，在一列子像素单元中，各所述子像素单元中晶体管的第一极和与其相连的数据线在所述行方向上的间距相等。
在本公开的一种示例性实施例中，位于所述数据线在所述行方向上相对两侧且相邻的两个像素电极关于所述数据线呈对称设置，位于所述数据线在所述行方向上相对两侧且相邻的两个公共电极关于所述数据线呈对称设置。
在本公开的一种示例性实施例中，还包括：与所述阵列基板对盒设置的对置基板及位于所述对置基板与所述阵列基板之间的液晶分子；
所述对置基板包括位于所述隔垫物远离所述阵列基板一侧的第二衬底及位于所述第 二衬底靠近所述阵列基板一侧的遮挡层，所述遮挡层具有交叉遮挡部、位于所述交叉遮挡部在行方向相对两侧的第一遮挡部、以及位于所述交叉遮挡部在列方向上相对两侧的第二遮挡部；其中，
所述交叉遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区与所述第二布线区的交叉区域，所述第一遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区且位于与所述第二布线区之外，所述第二遮挡部在所述第一衬底上的正投影至少覆盖所述第二布线区且位于所述第一布线区之外；
且与所述隔垫物对应的所述交叉遮挡部在列方向上的最大尺寸大于所述第一遮挡部在列方向上的最大尺寸，且所述交叉遮挡部在行方向上的最大尺寸大于所述第二遮挡部在行方向上的最大尺寸。
在本公开的一种示例性实施例中，所述隔垫物在所述第二衬底上的正投影位于所述交叉遮挡部在所述第二衬底上的正投影的中心区域内，
所述隔垫物在所述第二衬底上的正投影的边缘与所述交叉遮挡部在所述第二衬底上的正投影的边缘之间的间距为第六间距，所述第六间距与所述第一电极条的第一宽度之比为11至33。
在本公开的一种示例性实施例中，所述晶体管在所述第一衬底上的正投影位于所述第一遮挡部在所述第一衬底上的正投影内，所述像素电极具有第一失效区，所述第一失效区与所述第二极通过第二过孔结构连接；其中，所述第一失效区在所述第一衬底上的正投影位于所述第一遮挡部在所述第一衬底上的正投影内，所述第一失效区在所述列方向上的尺寸与所述第一电极条的第一宽度之比为1.5至5.5。
在本公开的一种示例性实施例中，所述像素电极还具有第二失效区，所述第二失效区在所述第一衬底上的正投影位于所述第二遮挡部在所述第一衬底上的正投影内，其中，
所述液晶分子为负性液晶分子，所述第二失效区在所述行方向上的尺寸与所述第一电极条的第一宽度之比为0.3至0.5；或
所述液晶分子为正性液晶分子，所述第二失效区在所述行方向上的尺寸与所述第一电极条的第一宽度之比为2至5.5。
本公开第三方面提供了一种显示装置，其包括上述任一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了相关技术中的电极结构的结构示意图；
图2示出了本公开一实施例所述的电极结构的结构示意图；
图3示出了本公开另一实施例所述的电极结构的结构示意图；
图4示出了本公开一实施例所述的显示面板的局部结构示意图；
图5示出了本公开一实施例所述的显示面板中阵列基板的结构示意图；
图6示出了图5中所示的晶体管的放大结构示意图；
图7示出了图5中A部的放大结构示意图；
图8示出了图5中B部的放大结构示意图；
图9示出了本公开实施例中所述的隔垫物与阵列基板之间的位置关系示意图；
图10示出了图5中所示的阵列基板与遮挡层及黑矩阵之间的位置关系示意图；
图11示出了图10中所示的遮挡层的结构示意图。
图1中附图标记：
10、电极结构；11、狭缝；
图2至图11中附图标记：
20、第一电极部；201、第一连接条；202、第一电极条；203、21、第二电极部；211、第二连接条；212、第二电极条；22、导电连接部；221、第一导电连接条；222、第二导电连接条；223、第三导电连接条；
3、阵列基板；30、第一衬底；301、子像素区；302、第一布线区；303、第二布线区；31、扫描线；32、公共线；320、第一段；3201、第一部；3202、第二部；3203、第三部；321、第二段；33、数据线；330、对位部；331、第一交叠部；332、第二交叠部；34、像素电极；35、公共电极；36、晶体管；360、有源层；361、栅极；362、第一极；363、第二极；4、对置基板；40、遮挡层；401、交叉遮挡部；402、第一遮挡部；403、第二遮挡部；404、透光孔；5、液晶分子；6、隔垫物。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
相关技术中，液晶显示面板中电极结构10的图形设计为内部开设有狭缝11，且狭缝11四周闭合，如图1所示；但这种电极结构10周边光效较差，从而容易出现显示不良。
为解决上述问题，本公开提供了一种电极结构，此电极结构可用于液晶显示面板中，并可作为液晶显示面板的像素电极或公共电极使用；举例而言，此电极结构可为ITO电极。详细说明，如图2所示，电极结构可包括在第一方向Y上依次排布的第一电极部20、导电连接部22及第二电极部21；其中：
第一电极部20可包括在第一方向Y上延伸的第一连接条201以及在第一方向Y上间隔排布的多个第一电极条202，第一连接条201具有在第二方向X上相对的第一侧和第二侧，多个第一电极条202位于第一连接条201的第一侧并与第一连接条201连接，且相邻第一电极条202中远离第一连接条201的端部之间呈开口状，也就是说，相邻第一电极条202中远离第一连接条201的端部之间无连接。
需要说明的是，前述提到多个第一电极条202在第一方向Y上间隔排布，也就说明，相邻第一电极条202之间具有第一缝隙S1，此第一缝隙S1呈半开放状。
第二电极部21包括在第一方向Y上延伸的第二连接条211以及在第一方向Y上间隔排布的多个第二电极条212，第二连接条211位于第一侧远离第二侧的位置，第二连接条211具有在第二方向X上相对的第三侧和第四侧，第三侧位于第四侧靠近第一侧的位置，需要说明的是，第二方向X与第一方向Y相互垂直；多个第二电极条212位于第二连接条211的第三侧并与第二连接条211连接，且相邻第二电极条212的远离第二连接条211的端部之间呈开口状，也就是说，相邻第二电极条212的远离第二连接条211的端部之间无连接。
需要说明的是，前述提到多个第二电极条212在第一方向Y上间隔排布，也就说明，相邻第二电极条212之间具有第二缝隙S2，此第二缝隙S2呈半开放状。
导电连接部22位于第一电极部20与第二电极部21之间，导电连接部22的两端分别与第一连接条201和第二连接条211连接。
在本公开的实施例中，通过将电极结构的第一电极部20和第二电极部21分别设计有呈半开放式的第一缝隙S1和第二缝隙S2，使得第一缝隙S1和第二缝隙S2开口处也可发生液晶分子偏转；因此，相比于图1示出的缝隙周围呈闭合的电极结构，可提高电极结构周围的光效。此外，如图2所示，第一电极部20的第一缝隙S1和第二电极部21的第二缝隙S2中一者开口方向朝右，另一者开口方向朝左；即：第一电极部20的第一缝隙S1和第二电极部21的第二缝隙S2的开口朝向相反，这样可均衡电极结构在第二方向X的两侧(即：图2中的左右两侧)的光效，从而使得电极结构周边光效更加均衡，以提高显示效果。
可选地，第一电极部20、第二电极部21与导电连接部22在参考平面上的正投影相互重合，此处提到的重合指的是在误差允许的范围内完全重合，这样设计可降低电极结构的设计难度，从而利于阵列基板中多个电极结构的排，但不限于此，第一电极部20、第二电极部21与导电连接部22在参考平面上的正投影也可不重合，视具体情况而定。
需要说明的是，本公开提到的参考平面为与第一方向Y相垂直的平面。
其中，前述提到的第一电极条202和第二电极条212可相互平行，即：第一电极条202和第二电极条212的延伸方向相互平行，以均衡第一电极部20和第二电极部21处的光效。具体地，第一电极条202和第二电极条212的延伸方向可与第三方向Q相互平行，此第三方向Q与第一方向Y和第二方向X相交，也就是说，第三方向Q不与第一方向Y和第二方向X平行或共线，这样设计可减小色偏，以提高显示效果。
举例而言，第三方向Q与第二方向X之间所夹锐角可为5°至15°，比如：5°、7°、9°、11°、13°、15°等等。
可选地，第一电极条202的第一宽度可与第二电极条212的第一宽度相等；此外，第一缝隙S1的第一宽度可与第二缝隙S2的第一宽度相等，这样可进一步均衡第一电极部20和第二电极部21处的光效，以提高产品显示效果。
需要说明的是，本公开中提到的第一宽度指的是在第四方向P上的尺寸，此第四方向P与第三方向Q相互垂直。
其中，为了保证第一电极部20和第二电极部21处的液晶分子偏转良好，以提高第一电极部20和第二电极部21处的光效；第一电极条202的第一宽度、第一缝隙S1的第一宽度、第二电极条212的第一宽度及第二缝隙S2的第一宽度需满足一定的要求；即：第一缝隙S1的第一宽度与第一电极条202的第一宽度之比可为1至4，比如：1、1.5、2、2.5、3、3.5、4等等。
具体地，本公开实施例的第一电极条202和第二电极条212的第一宽度可为1.8μm至3μm，比如：1.8μm、2μm、2.2μm、2.4μm、2.6μm、2.8μm、3μm等等；第一缝隙S1和第二缝隙S2的第一宽度可为3μm至7μm，比如：3μm、3.5μm、4μm、4.5μm、5μm、5.5μm、6μm、6.5μm、7μm等等。
此外，为进一步均衡第一电极部20和第二电极部21处的光效，以提高产品显示效果；第一连接条201的第二宽度与第二连接条211的第二宽度可相等。其中，第一连接条201与第二连接条211的第二宽度可与第一电极条202和第二电极条212的第一宽度相等，但不限于此，也可略大于第一电极条202和第二电极条212的第一宽度，以在提高光效的同时，还可改善由于第一连接条201和第二连接条211的第一宽度过小而导致其容易断线的情况，提高了产品良率。
需要说明的是，本公开实施例提到的第二宽度为在第二方向X上的尺寸。
其中，前述提到电极结构的第一电极部20和第二电极部21通过导电连接部22连接，为了避免在制造过程中导电连接部22受到Partical(杂质颗粒)影响而发生断线的情况，本公开实施例中将导电连接部22的面积设计的较大，以避免其极易形成断线而导致像素失效的情况，具体地，本公开实施例的导电连接部22的面积大于第一电极条202的面积和第二电极条212的面积。
应当理解的是，此导电连接部22整体的延伸方向也可与第三方向相互平行，以降低加工设计难度。举例而言，当导电连接部22在参考平面上的正投影与第一电极部20和第二电极部21在参考平面上的正投影重合时，为了使得导电连接部22的面积大于第一电极条202和第二电极条212的面积，本实施例可使第一电极条202的第一宽度和第二电极条212的第一宽度小于导电连接部22整体的第一宽度。
在本公开的一实施例中，如图3所示，导电连接部22可包括第一导电连接条221、第二导电连接条222及至少两条第三导电连接条223；其中，第一导电连接条221和第二导电连接条222均在第一方向Y上延伸，且第一导电连接条221和第二导电连接条222在第二方向X上间隔排布，第一导电连接条221与第一连接条201连接，第二导电连接条222与第二连接条211连接；至少两条第三导电连接条223在第一方向Y上间隔排布，并位于第一导电连接条221和第二导电连接条222之间，且各第三导电连接条223的两端(即：在其延伸方向上的两端)分别与第一导电连接条221和第二导电连接条222连接，也就是说，相邻第三导电连接条223之间具有为第三缝隙S3，且此第三缝隙S3四周闭合。
本公开实施例中，通过在导电连接部22内部进行开缝(即：第三缝隙S3)设计，一方面可减小导电连接部22上方的光效损失，从而可提高电极结构整体光效，另一方面，可以使得第一电极部20和第二电极部21通过至少两条导线(即：第三导电连接条223)连接导通，这样即使Partical导致其中一条导线断开，仍有其他导线连接导通第一电极部20和第二电极部21，从而可大大降低了像素失效的发生率，即：提高了产品良率。
可选地，第三导电连接条223设置两条，在保证第一电极部20和第二电极部21连接导通稳定的同时，还可适当减小导电连接部22在电极结构中的占比，即：为第一电极部20和第二电极部21提供更多的设计空间，换言之，第一电极部20和第二电极部21的面积可大于导电连接部22的面积，由于第一电极部20和第二电极部21的缝隙呈半开放设计，而导电连接部22的缝隙为封闭式设计，因此，第一电极部20和第二电极部21处的光效优于导电连接部22处的光效；这样通过使第一电极部20和第二电极部21的面积大于导电连接部22的面积，可提高电极结构整体的光效，提高产品质量。此外，由于开设第三缝隙S3，还可缓解在制作过程中Partical落到导电连接部22上的情况，从而可缓解导电连接部22的阻值因Partical增加的情况，继而缓解对像素的驱动产生的影响。
但应当理解的是，第三导电连接条223不限于设置两条，也可设置为三条、四条等，视具体情况而定。
其中，为了进一步减小导电连接部22在电极结构中的占比，第一导电连接条221的长度和第二导电连接条222的长度均小于第一连接条201的长度以及小于第二连接条211的长度。应当理解的是，此处提到的长度为在第一方向Y上的尺寸。
可选地，第一导电连接条221的第二宽度与第一连接条201的第二宽度可相等，第二导电连接条222的第二宽度与第二连接条211的第二宽度可相等。
在本公开的实施例中，第三导电连接条223的延伸方向与第三方向Q相互平行。其中，第三导电连接条223的第一宽度可与第一电极条202的第一宽度相等；此外，且相邻第三导电连接条223之间的第三缝隙S3可与相邻第一电极条202之间的第一缝隙S1、相邻第二电极条212之间的第二缝隙S2的相等，这样可均衡导电连接部22与第一电极部20和第二电极部21处的光效，以提高产品显示效果。
进一步地，第三导电连接条223与第一电极条202之间的第四缝隙S4、第三导电连接条223与第二电极条212之间的第五缝隙S5与前述提到的第一缝隙S1、第二缝隙S2、第三缝隙S3均相等，以均衡导电连接部22、第一电极部20、第二电极部21处以及三者之间处的光效，从而可提高产品显示效果。
在本公开的另一实施例中，如图2所示，导电连接部22可为一条导电连接条，此导电连接条在第三方向Q上延伸，其中，导电连接条的第一宽度与第一电极条202的第一宽度之比可为1.5至5.5，也就是说，导电连接部22相比于第一电极条202进行了加宽处理，以改善导电连接部22容易断线的情况，保证产品质量。
举例而言，在导电连接部22仅为一条导电连接条时，此导电连接条的第一宽度可为5μm至10μm，比如：5μm、6μm、7μm、8μm、9μm、10μm等等。
在本公开的一实施例中，如图2和图3所示，第一电极部20还包括信号连接条203，位于第一连接条201的第一侧并与第一连接条201连接，且位于多个第一电极条202远离导电连接部22的一侧。举例而言，在本公开的电极结构为公共电极时，此信号连接条203可与阵列基板中的公共线连接，也就是说，此信号连接条203处可用于接收公共信号；但不限于此，在本公开的电极结构为像素电极时，此信号连接条203还可与阵列基板中的晶体管的源漏电极连接，用于接收来自源漏电极传递过来的信号，例如：数据信号。
需要说明的是，图2和图3中虚线不具有实际意义，仅仅是为了将前述提到的各结构进行区分，以方便理解前述提到的各结构之间的位置关系，应当理解的是，本公开实施例提到的电极结构整体为一体式结构。
本公开还提供了一种显示面板，此显示面板可为液晶显示面板；如图4所示，显示面板可包括阵列基板3、与阵列基板3对盒设置的对置基板4以及位于对置基板4与阵列基板3之间的液晶分子5和多个隔垫物6；多个隔垫物6设置可以提高显示面板整体厚度的均一性，提高显示面板对液晶分子波动的容忍度，进而提高显示面板的良率。
举例而言，液晶分子5可为负性液晶分子，但不限于此，也可为正性液晶分子。多个隔垫物6中可包括主隔垫物和辅隔垫物，该主隔垫物在显示面板未收到外界压力时，其两端可分别与阵列基板3和对置基板4相接触，主要起到支撑作用；而辅隔垫物在显示面板未收到外界压力时，辅隔垫物若形成在对置基板4上，该辅隔垫物与阵列基板1之间具有一定的间距，也就是说，主隔垫物与辅隔垫物之间存在段差(高度差)，通过调节主隔垫物与辅隔垫物之间的段差可以对显示面板的厚度进行微调。示例地，主隔垫物的高度大于辅隔垫物的高度，当显示面板受到外界压力时，主隔垫物先承受所有压力并压缩，当主隔垫物压缩至主隔垫物与辅隔垫物之间的段差降为0时，主隔垫物和辅隔垫物共同承受外界压力。
需要说明的是，主隔垫物和辅隔垫物这两种可按照一定周期排布。工艺制作过程中需要对不同种类隔垫物的尺寸高度进行监控。因隔垫物尺寸较小，且主隔垫物一般较少，单独依靠尺寸，设备很难准确识别主隔垫物位置，通常将主隔垫物周围某个位置空缺隔垫物设计(即：不设置任何隔垫物)，以方便更快更准确的识别主隔垫物位置对其进行监控，例如：在设计时将主隔垫物下方不设置任何隔垫物，在监控时，可先快速确定不设置任何隔垫物的位置，然后前述提到的设计规则，可明确不设置任何隔垫物的上方位置处的隔垫物即为主隔垫物。
在本公开的实施例中，阵列基板3可包括第一衬底30及形成在第一衬底30上的多个子像素单元、多行扫描线31、多行公共线32、多列数据线33，其中：
如图5所示，第一衬底30可具有沿行方向X和列方向Y呈阵列排布的多个子像素区301、位于相邻两行子像素区301之间的第一布线区302以及位于相邻两列之间的第二布线区303，第一布线区302与第二布线区303之间存在交叠。举例而言，此第一衬 底30可为单层结构，该第一衬底30的材料可为玻璃。但不限于此，此第一衬底30还可多层结构；且第一衬底30的材料不限于玻璃，也可为其他材料，例如：聚酰亚胺(PI)等材料，视具体情况而定。
多个子像素单元形成在第一衬底30上，每个子像素单元包括至少部分位于子像素区301内的像素电极34、公共电极35以及至少部分位于第一布线区302的晶体管36。此外，子像素单元中还可包括电容器(图中未示出)。
在本公开的实施例中，如图6所示，晶体管36可包括有源层360、栅极361及同层设置的第一极362和第二极363；其中，栅极361与有源层360之间还可设置绝缘层37，以使栅极361与有源层360之间相互绝缘，此绝缘层37可采用无机材料制作而成，例如，氧化硅、氮化硅等无机材料。需要说明的是，栅极361可与扫描线31同层设置，栅极361可属于前述提到的扫描线31的一部分。
其中，晶体管36可为顶栅型，也可为底栅型。在本公开的实施例中主要以晶体管36为底栅型为例进行说明。在晶体管36为底栅型时，栅极361形成在第一衬底30上，此栅极361可包括金属材料或者合金材料，例如包括钼、铝及钛等，以保证其良好的导电性能；绝缘层形成在第一衬底30上并覆盖栅极361，此绝缘层可采用无机材料制作而成，例如：氧化硅、氮化硅等无机材料；有源层360形成在绝缘层背离第一衬底30的一侧，第一极362和第二极363分别与有源层360的两掺杂区连接，第一极362和第二极363可包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
应当理解的是，子像素单元中晶体管36的数量可设置有多个，此晶体管36还分为N型和P型等。
在本公开的实施例中，像素电极34可与第一极362连接；其中，在与像素电极34连接的晶体管36为N型时，晶体管36的第一极362可为漏电极，第二极363可为源电极；在与像素电极34连接的晶体管36为P型时，晶体管36的第一极362可为源电极，第二极363可为漏电极。公共电极35在第一衬底30上的正投影与像素电极34在第一衬底30上的正投影存在交叠。其中，像素电极34和公共电极35中的至少一者为前述任一实施例所描述的电极结构，从而可提高像素周边光效，提高产品质量。需要说明的是，本实施例中提到的行方向X可为前述提到的第二方向X平行，而列方向Y可为前述提到的第一方向Y。
在本公开的实施例中，像素电极34可位于公共电极35靠近第一衬底30的一侧，也就是说，像素电极34可先于公共电极35制作在第一衬底30上；举例而言，此像素电极34可为板状电极；即：像素电极34为一整块并未开设狭缝；而公共电极35可为前述任一实施例所描述的电极结构；通过像素电极34和公共电极35之间产生的电场，使在电极之间和电极正上方的所有液晶分子发生偏转，可提高液晶的工作效率，且增加了透光效率。但不限于此，也可像素电极34位于公共电极35远离第一衬底30的一侧，此像素电极34为前述任一实施例所描述的电极结构；公共电极35为板状电极。
需要说明的是，本公开实施例主要以像素电极34位于公共电极35靠近第一衬底30的一侧，且像素电极34可为板状电极；而公共电极35可为前述任一实施例所描述的电极结构为例进行说明。
其中，为了保证阵列基板的透光率，像素电极34可采用ITO材料制作而成，但不限于此，也可采用氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成；也就是说，由于像素电极34采用的材料与晶体管36的栅极361、第一极362和第二极363的材料不同，因此，该像素电极34与晶体管36的栅极361、第一极362和第二极363可采用不同构图工艺制作而成。
举例而言，像素电极34可位于晶体管36的第一极362和第二极363靠近第一衬底 30的一侧，如图5所示，像素电极34可通过第二过孔结构H2与晶体管36的第一极362连接。其中，像素电极34可在形成晶体管36的栅极361之前形成在第一衬底30上，也就是说，在制作阵列基板时，可先采用一构图工艺在第一衬底30上形成像素电极34，然后再采用另一构图工艺在第一衬底30上形成晶体管36的栅极361。需要说明的是，像素电极34与栅极361虽然都形成在第一衬底30上，但像素电极34与栅极361之间相互断开(即：无连接)。但不限于此，像素电极34还可在形成晶体管36的栅极361之后形成在第一衬底30上，且此像素电极34还可位于栅极361远离第一衬底30的一侧。
同理，为了保证阵列基板的透光率，公共电极35也可采用ITO等透明导电材料制作而成；此公共电极35可形成在晶体管36的第一极362和第二极363远离第一衬底30的一侧，应当理解的是，此公共电极35和晶体管36的第一极362和第二极363之间还具有一层绝缘层。
至少一行扫描线31可位于一第一布线区302内，换言之，每一第一布线区302内可设置有至少一行扫描线31；其中，扫描线31与子像素单元中晶体管36的栅极361连接，前述提到扫描线31可与晶体管36的栅极361同层设置且为一体式结构，此扫描线31被配置为向子像素单元提供扫描信号。
至少一行公共线32可位于一第一布线区302内，换言之，每一第一布线区302内可设置有至少一行公共线32；其中，公共线32与公共电极35连接，其被配置为向子像素单元提供公共信号；举例而言，公共线32可与扫描线31同层设置，也就是说，公共线32可位于公共电极35靠近第一衬底30的一侧，如图5所示，此公共线32可通过第一过孔结构H1与公共电极35连接；具体地，公共线32可通过第一过孔结构H1与公共电极35的信号连接条连接；应当理解的是，此信号连接条可位于第一布线区302内。
在本公开的实施例中，如图7所示，公共线32具有位于第二布线区303之外且位于第一布线区302之内的第一段320，此第一段320在行方向X上可间隔排布并通过第二段321连接，此第二段321的部分位于第二布线区303，另一部位于第一布线区302。
具体地，如图7所示，公共线32的第一段320可具有在行方向X上依次排布的第一部3201、第二部3202及第三部3203，此第三部3203远离扫描线31的一侧比第一部3201远离扫描线31的一侧更远离扫描线31，第二部3202远离扫描线31的一侧比第一部3201远离扫描线31的一侧更靠近扫描线31，且第二部3202远离扫描线31的一侧与第一部3201和第三部3203之间形成有缺口a；也就是说，在第一段320靠近扫描线31的一侧为在行方向X上延伸的直线时，第三部3203在列方向Y上的尺寸大于第一部3201在列方向Y上的尺寸，即：第三部3203相比于第一部3201凸出设置；而第二部3202在列方向Y上的尺寸小于第一部3201在列方向Y上的尺寸，此第二部3202相比于第一部3201和第三部3203内缩设置，因此，第一部3201、第二部3202及第三部3203之间可形成有一缺口a；也就是说，公共线32不是平直的，既有缺口a，又有凸出的部分。
其中，如图7所示，第一过孔结构H1在第一衬底30上的正投影的部分与第二部3202和第三部3203在第一衬底30上的正投影存在交叠，另一部分与缺口a在第一衬底30上的正投影存在交叠，此关系可理解为公共线32处的第一过孔结构H1为半过孔设计，即：第一过孔结构H1的一部分正投影在公共线32上，另一部分投影在缺口a处，这样设计在保证第一过孔结构H1位于公共线32上的同时，还可改善取向层PI扩散均一性。
进一步地，第一过孔结构H1的边界线与第三部3203的边界线在列方向Y上的间距为第三间距，第一过孔结构H1的边界线与第三部3203中远离第二部3202的边界线在行方向X上的间距为第四间距，第一过孔结构H1的边界线与第二部3202中远离第三部3203的边界线在行方向X上的间距为第五间距，其中，为了确保第一过孔结构H1可以形成在公共线32上，前述提到的第三间距、第四间距及第五间距与第一电极条202的第一宽度之比可为1至6，比如：1、2、3、4、5、6等等，举例而言，第三间距、第四间 距及第五间距可为3μm至10μm，比如：3μm、5μm、7μm、10μm等等。
举例而言，如图5所示，每一第一布线区302内可设置有一行扫描线31和一行公共线32，应当理解的是，此扫描线31与公共线32之间相互断开，即：扫描线31在第一衬底30上的正投影与公共线32在第一衬底30上行的正投影不交叠。需要说明的是，第一布线区302内不限于设置一行扫描线31和一行公共线32，也可设置两行扫描线31，或不设置公共线32等等，视具体情况而定。本公开实施例主要以每一第一布线区302内设置有一行扫描线31和一行公共线32进行说明。
至少一列数据线33可位于一第二布线区303内，换言之，每一第二布线区303内设置至少一列数据线33，此数据线33可与子像素单元中晶体管36的第二极363连接，其被配置为向子像素单元提供数据信号。其中，数据线33在第一衬底30上的正投影与扫描线31和公共线32在第一衬底30上的正投影存在交叠。需要说明的是，本公开实施例的数据线33可与子像素单元中晶体管36的第一极362和第二极363同层设置，即：可采用同一构图工艺制作而成，以降低掩膜成本；但不限于此，也可采用不同构图工艺制作而成，视具体情况而定。
举例而言，如图5所示，每一第二布线区303内可设置一列数据线33，此数据线33可与同一列中各子像素单元的第二极363连接，也就是说，数据线33可为同一列子像素单元提供数据信号。
其中，每列数据线33可关于其中轴线呈对称设置，需要说明的是，此处提到的中轴线为经过数据线33的中心并在列方向Y上延伸的线。
可选地，位于数据线33在行方向X上相对两侧且相邻的两个第一极362与数据线33在行方向X上的间距可相等，以保证数据线33与两侧晶体管36耦合电容接近一致，从而保证数据线33两侧光效均一性。
同理，位于数据线33在行方向X上相对两侧且相邻的像素电极34可关于数据线33呈对称设置，位于数据线33在行方向X上相对两侧且相邻的两个公共电极35关于数据线33呈对称设置，以保证数据线33与两侧的像素电极34和公共电极35耦合电容接近一致，从而保证数据线33两侧光效均一性。
可选地，在一列子像素单元中，各子像素单元的第一极362和与其相连的数据线33在行方向X上的间距相等，以保证每列中各子像素单元的晶体管36和数据线33之间的耦合电容接近一致，保证每列各子像素单元处的光效均一性。需要说明的是，在一列子像素单元中各子像素单元的第一极362和与其相连的数据线33在行方向X上的间距相等的同时，该列第一极362与栅极361交叠面积需要与其他列保持一致。
在本公开的一实施例中，如图8所示，至少部分列数据线33具有对位部330，此对位部330位于第一布线区302与第二布线区303的交叠区域，且对位部330在第一衬底30上的正投影与公共线32和扫描线31在第一衬底30上的正投影不重合；其中，如图9所示，每个隔垫物6在第一衬底30上的正投影位于一对位部330在第一衬底30上的正投影内，也就是说，隔垫物6在第一衬底30上的正投影的外轮廓位于对位部330在第一衬底30上的正投影的外轮廓的内侧，确保了隔垫物6支撑处的平坦度，以保证隔垫物6稳定地支撑在阵列基板上。
需要说明的是，对位部330周围扫描线31呈异性设计，此扫描线31图案尽肯能保持相对数据线33对称，以保证数据线33两侧光效均一性。
其中，数据线33中对位部330在行方向X上的最大尺寸大于其他部位在行方向X上的最大尺寸；在本公开的实施例中，通过将数据线33中对位部330在行方向X上的尺寸设计的较大，以确保隔垫物6支撑处的平坦度，通过将数据线33中除对位部330之外的其他部位在行方向X上的尺寸设计的较小，可提高像素开口率。
可选地，如图8和图9所示，对位部330在第一衬底30上的正投影位于同一第一布 线区302内的扫描线31和公共线32在第一衬底30上的正投影之间，这样设计使得隔垫物6投影的对位部330的上、下、左、右四个方向均有金属块存在，即：上方存在扫描线31与数据线33交叠的部分，下方存在公共线32与数据线33交叠的部分，而左、右方分别存在一晶体管36，也就是说，阵列基板3中与隔垫物6相对应的区域的厚度小于此区域上、下、左、右四个方向具有前述提到的金属块的区域的厚度，这样可限定隔垫物6的滑动距离，阻止隔垫物6向有效区滑动，以保证显示效果，应当理解的是，有效区指的是能正常发光的区域，此有效区位于子像素区301内。
其中，如图8和图9所示，数据线33与扫描线31在第一衬底30上的正投影存在交叠的部分可定义为第一交叠部331，与公共线32在所述第一衬底30上的正投影存在交叠的部分可定义为第二交叠部332；此第一交叠部331与对位部330在列方向Y上的间距可为第一间距，第二交叠部332与对位部330在列方向Y上的间距可为第二间距，此第一间距和第二间距与第一电极条202的第一宽度之比为1.5至17，比如：1.5、3、5、8、11、14、17等等；举例而言，此第一间距和第二间距可为5um至30um，比如：5um、10um、15um、20um、25um、30um等等，但不限于此，具体可根据阵列基板与对置基板实际对合精度、第一交叠部331所在区域、第二交叠部332所在区域对隔垫物6的阻挡作用、对DNU(Dark Not Uniformly，暗态不均匀)的影响而决定。
举例而言，本公开实施例中提到的对位部330在第一衬底30上的正投影形状可类似为菱形、椭圆形或六边形等，视具体情况而定。需要说明的是，阵列基板中对位部330设置的数量和位置可与隔垫物6的数量和位置相匹配，即：对位部330与隔垫物6一一对应。
在本公开的一实施例中，对置基板可包括位于隔垫物6远离阵列基板3一侧的第二衬底(图中未标示出)及位于第二衬底靠近阵列基板3一侧的遮挡层40，此遮挡层40具有交叉遮挡部401、位于交叉遮挡部401在行方向X相对两侧的第一遮挡部402、以及位于交叉遮挡部401在列方向Y上相对两侧的第二遮挡部403；需要说明的是，交叉遮挡部401在第一衬底30上的正投影至少覆盖第一布线区302与第二布线区303的交叠区域，而第一遮挡部402在第一衬底30上的正投影至少覆盖第一布线区302且位于与第二布线区303之外，第二遮挡部403在第一衬底30上的正投影至少覆盖第二布线区303且位于第一布线区302之外。
其中，结合图10和图11所示，遮挡层40中第一遮挡部402、第二遮挡部403和交叉遮挡部401可呈阵列排布，阵列排布的第一遮挡部402、第二遮挡部403和交叉遮挡部401可围成透光孔404，此透光孔404在第一衬底30上的正投影位于子像素区301内，该透光孔404用于允许光线透过。在整个显示面板的面积一定时，透光孔404的面积总和越大，也就是说，遮挡部的面积总和越小，则显示面板的光透过率越高，显示效果越好。应当理解的是，图11中虚线均不具有实际含义，仅仅是为了方便本领域技术人员理解遮挡层22中各部分。
需要说明的是，为了保证遮挡层40能够将阵列基板3上布线区完全遮盖，可使遮挡层40中第一遮挡部402、第二遮挡部403和交叉遮挡部401在第一衬底30上的正投影还可覆盖部分子像素区301。
在本公开的实施例中，当显示面板受到较大外力时，尤其是跌落测试等冲击力较大时，隔垫物6主要表现为在列方向Y滑动，因采用隔垫物6在数据线33的对位部330上这一设计，隔垫物6滑动始终在数据线33上方，由于数据线33的支撑作用，隔垫物6不会划伤有效区，此外，因数据线33上方有第二遮挡部403和交叉遮挡部401进行遮挡，即使数据线33上方的膜层(即：取向膜层)出现划伤而导致漏光，也会被第二遮挡部403和交叉遮挡部401遮挡住，不会形成点状或大面积的暗态漏光不良，继而可提高显示效果。
此外，即使隔垫物6在受到压力时表现为在行方向X上滑动，由于第一布线区302上方有第一遮挡部402和交叉遮挡部401进行遮挡，也不会形成点状或大面积的暗态漏光不良，继而可提高显示效果。
在本公开的一实施例中，如图10和图11所示，交叉遮挡部401在列方向Y上的最大尺寸可大于第一遮挡部402在列方向Y上的最大尺寸，且交叉遮挡部401在行方向X上的最大尺寸大于第二遮挡部403在行方向X上的最大尺寸，这样设计可避免隔垫物6在压力测试过程中滑出遮挡区域，从而可改善暗态漏光不良的问题。
应当理解的是，在本公开实施中，如图10和图11所示，不限于所有的交叉遮挡部401在列方向Y上的最大尺寸大于第一遮挡部402在列方向Y上的最大尺寸、在行方向X上的最大尺寸大于第二遮挡部403在行方向X上的最大尺寸；可仅使与隔垫物6对应的交叉遮挡部401这样设计，而其他未与隔垫物6对应的交叉遮挡部401在列方向Y上的尺寸可与第一遮挡部402在列方向Y上的尺寸相等，在行方向X上的尺寸可与第二遮挡部403在行方向X上的尺寸相等，这样可提高像素开口率。
举例而言，如图11所示，与隔垫物6对应的交叉遮挡部401可近似为六边形，未与隔垫物6对应的交叉遮挡部401、第一遮挡部402和第二遮挡部403可近似为矩形，但不限于此，也可为其他形状，视具体情况而定。
其中，隔垫物6在第二衬底上的正投影可位于交叉遮挡部401在第二衬底上的正投影的中心区域内，且隔垫物6在第二衬底上的正投影的边缘与交叉遮挡部401在第二衬底上的正投影的边缘之间的间距为第六间距，此第六间距与第一电极条202的第一宽度之比为11至33，比如：11、17、23、28、33等等；举例而言，第六间距可为35μm至60μm，比如：35μm、40μm、45μm、50μm、55μm、60μm等等；这样设计可避免隔垫物6在压力测试过程中滑出遮挡区域，从而可改善暗态漏光不良的问题。
在本公开的实施例中，遮挡层40除了覆盖数据线33、公共线32、扫描线31、晶体管36和部分公共电极35之外，还可覆盖部分像素电极34。其中，像素电极34边缘靠近扫描线31、数据线33区域存在耦合电场，显示过程中会导致液晶排布紊乱，产生失效区，导致暗态像素边缘漏光，因此需要遮挡层40对这部分失效区进行遮挡。
其中，前述提到的子像素单元的晶体管36在第一衬底30上的正投影可位于第一遮挡部402在第一衬底30上的正投影内，其中，子像素单元的像素电极34具有第一失效区，此第一失效区与第二极363通过第二过孔结构H2连接；其中，第一失效区在第一衬底30上的正投影位于第一遮挡部402在第一衬底30上的正投影内，此第一失效区在列方向Y上的尺寸与第一电极条202的第一宽度之比为1.5至5.5；比如：1.5、2.5、3.5、4.5、5.5等等，举例而言，第一失效区在列方向Y上的尺寸可为5μm至10μm，比如：5μm、6μm、7μm、8μm、9μm、10μm等等，也就是说，第一遮挡部402覆盖像素电极34至少5um，需要说明的是，在彩膜层位于对置基板上时，考虑上下基板对盒精度，需加宽更多，但也不得超过10μm，以避免过多影响像素开口率。
此外，数据线33与像素电极34边缘同样存在耦合电场，也就是说，本公开实施例的像素电极34还具有第二失效区，此第二失效区在第一衬底30上的正投影可位于第二遮挡部403在第一衬底30上的正投影内；其中，在液晶分子5为负性液晶分子，该电场不会导致液晶旋转，第二失效区在行方向X上的尺寸与第一电极条202的第一宽度之比为0.3至0.5，比如：0.3、0.4、0.5等等，举例而言，第二失效区在行方向X上的尺寸可为1μm作用，也就是说，第二遮挡部403的覆盖像素电极341μm左右，以遮挡数据线33附近的Shadow(阴暗)区。若在液晶分子5为正性液晶分子时，数据线33与像素电极34之间的耦合电场不会导致明显的暗态漏光，但是会导致液晶分子造成Crosstalk(串扰)现象加重，因此，此时，像素电极34的第二失效区在行方向X上的尺寸与第一电极条202的第一宽度之比可为2至5.5，比如：2、2.5、3、3.5、4、4.5、5、5.5等等， 举例而言，第二失效区在行方向X上的尺寸可为6μm至10μm，比如：6μm、7μm、8μm、9μm、10μm等等，也就是说，第二遮挡部403的覆盖像素电极34至少6um，以遮挡耦合电场区域。
需要说明的是，液晶显示面板中用到的彩膜层可位于对置基板4上，也可位于阵列基板3上，视具体情况而定。
本公开的实施例还提供了一种显示装置，其包括上述任一实施例所描述的显示面板。此显示装置可为液晶显示装置。
根据本公开的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如液晶显示屏、手机、笔记本电脑等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，还可包括背光模组、外壳、主电路板、电源线，等等，本领域善解人意可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (25)

  1. 一种电极结构，其中，包括：
    第一电极部，包括在第一方向上延伸的第一连接条以及在所述第一方向上间隔排布的多个第一电极条，所述第一连接条具有在第二方向上相对的第一侧和第二侧，所述多个第一电极条位于所述第一连接条的第一侧并与所述第一连接条连接，且相邻所述第一电极条中远离所述第一连接条的端部之间呈开口状；
    第二电极部，与所述第一电极部在所述第一方向上间隔排布，所述第二电极部包括在所述第一方向上延伸的第二连接条以及在所述第一方向上间隔排布的多个第二电极条，所述第二连接条位于所述第一侧远离所述第二侧的位置，所述第二连接条具有在所述第二方向上相对的第三侧和第四侧，所述第三侧位于所述第四侧靠近所述第一侧的位置；所述多个第二电极条位于所述第二连接条的第三侧并与所述第二连接条连接，且相邻所述第二电极条的远离所述第二连接条的端部之间呈开口状；
    导电连接部，位于所述第一电极部与所述第二电极部之间，所述导电连接部的两端分别与所述第一连接条和所述第二连接条连接；且所述导电连接部的面积大于所述第一电极条的面积和所述第二电极条的面积；
    其中，所述第一方向与所述第二方向相互垂直。
  2. 根据权利要求1所述的电极结构，其中，所述第一电极部、所述第二电极部与所述导电连接部在参考平面上的正投影相互重合；其中，所述参考平面为与所述第一方向相垂直的平面。
  3. 根据权利要求1或2所述的电极结构，其中，所述第一电极条、所述第二电极条、所述导电连接部的延伸方向均与第三方向相互平行，所述第一电极条的第一宽度和所述第二电极条的第一宽度相等，且所述第一电极条的第一宽度小于所述导电连接部的第一宽度；
    其中，所述第一宽度为在第四方向上的尺寸，所述第三方向与所述第四方向相垂直，且所述第三方向与所述第一方向和所述第二方向均相交。
  4. 根据权利要求3所述的电极结构，其中，所述导电连接部包括在所述第二方向上间隔排布且均在所述第一方向上延伸的第一导电连接条和第二导电连接条，以及位于所述第一导电连接条和所述第二导电连接条之间并在所述第一方向上间隔排布的至少两条第三导电连接条，各所述第三导电连接条的两端分别与所述第一导电连接条和所述第二导电连接条连接，所述第三导电连接条的延伸方向与所述第三方向相互平行；
    其中，所述第一导电连接条与所述第一连接条连接，所述第二导电连接条与所述第二连接条连接。
  5. 根据权利要求4所述的电极结构，其中，所述第三导电连接条的第一宽度与所述第一电极条的第一宽度相等，所述第一导电连接条的第二宽度与所述第一连接条的第二宽度相等，所述第二导电连接条的第二宽度与所述第二连接条的第二宽度相等；其中，所述第二宽度为在所述第二方向上的尺寸。
  6. 根据权利要求5所述的电极结构，其中，相邻所述第一电极条之间的缝隙为第一缝隙，相邻所述第二电极条之间的缝隙为第二缝隙，相邻所述第三导电连接条之间的缝隙为第三缝隙，所述第三导电连接条与所述第一电极条之间的缝隙为第四缝隙，所述第三导电连接条与所述第二电极条之间的缝隙为第五缝隙，其中，所述第一缝隙的第一宽度、所述第二缝隙的第一宽度、所述第三缝隙的第一宽度、所述第四缝隙的第一宽度与所述第五缝隙的第一宽度均相等。
  7. 根据权利要求5所述的电极结构，其中，所述第一缝隙的第一宽度与所述 第一电极条的第一宽度之比为1至4。
  8. 根据权利要求6所述的电极结构，其中，所述第一导电连接条的长度和所述第二导电连接条的长度均小于所述第一连接条的长度以及小于所述第二连接条的长度，所述长度为在所述第一方向上的尺寸。
  9. 根据权利要求3所述的电极结构，其中，所述导电连接部为一条导电连接条，所述导电连接条在所述第三方向上延伸，所述导电连接条的第一宽度与所述第一电极条的第一宽度之比为1.5至5.5。
  10. 根据权利要求1或2所述的电极结构，其中，第一电极部还包括信号连接条，位于所述第一连接条的第一侧并与所述第一连接条连接，且位于所述多个第一电极条远离所述导电连接部的一侧。
  11. 一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板包括：
    第一衬底，具有沿行方向和列方向呈阵列排布的多个子像素区、位于相邻两行所述子像素区之间的第一布线区以及位于相邻两列之间的第二布线区，所述第一布线区与所述第二布线区之间存在交叠；
    多个子像素单元，形成在所述第一衬底上，每个所述子像素单元包括至少部分位于所述子像素区内的像素电极、公共电极以及至少部分位于所述第一布线区的晶体管；所述晶体管包括栅极、第一极和第二极；所述像素电极与所述第一极连接；所述公共电极在所述第一衬底上的正投影与所述像素电极在所述第一衬底上的正投影存在交叠；且所述像素电极和所述公共电极中的至少一者为权利要求1至9中任一项所述的电极结构，所述行方向为所述第二方向，所述列方向为所述第一方向；
    多行扫描线，形成在所述第一衬底上，至少一行所述扫描线位于一所述第一布线区内，所述扫描线与所述栅极连接，被配置为向所述子像素单元提供扫描信号，
    多行公共线，形成在所述第一衬底上，至少一行所述公共线位于一所述第一布线区内，所述公共线与所述公共电极连接，被配置为向所述子像素单元提供公共信号；
    多列数据线，形成在所述第一衬底上，至少一列所述数据线位于一所述第二布线区内，所述数据线与所述第二极连接，被配置为向所述子像素单元提供数据信号；
    其中，所述扫描线在所述第一衬底上的正投影与所述公共线在所述第一衬底上行的正投影不交叠；所述数据线在所述第一衬底上的正投影与所述扫描线和所述公共线在所述第一衬底上的正投影存在交叠。
  12. 根据权利要求11所述的显示面板，其中，所述公共电极位于所述像素电极远离所述第一衬底的一侧，所述公共电极为所述电极结构。
  13. 根据权利要求12所述的显示面板，其中，至少部分列所述数据线具有对位部，所述对位部位于所述第一布线区与第二布线区的交叠区域，且所述对位部在所述第一衬底上的正投影与所述公共线和所述扫描线在所述第一衬底上的正投影不重合；其中，所述显示面板还包括：
    多个隔垫物，位于所述数据线远离所述第一衬底的一侧，每个所述隔垫物在所述第一衬底上的正投影位于一所述对位部在所述第一衬底上的正投影内。
  14. 根据权利要求13所述的显示面板，其中，每一所述第一布线区内设置有一行所述扫描线和一行所述公共线，所述对位部在所述第一衬底上的正投影位于所述扫描线和所述公共线在所述第一衬底上的正投影之间。
  15. 根据权利要求14所述的显示面板，其中，所述数据线还具有与所述扫描 线在所述第一衬底上的正投影存在交叠的第一交叠部及与所述公共线在所述第一衬底上的正投影存在交叠的第二交叠部；其中，所述第一交叠部与所述对位部在所述列方向上的间距为第一间距，所述第二交叠部与所述对位部在所述列方向上的间距为第二间距，所述第一间距和所述第二间距与所述第一电极条的第一宽度之比为1.5至17。
  16. 根据权利要求12所述的显示面板，其中，
    在所述公共电极为如权利要求10所述的电极结构时，所述公共电极的信号连接条位于所述第一布线区内；
    所述公共电极位于所述公共线远离所述第一衬底的一侧，所述信号连接条通过第一过孔结构与所述公共线连接；
    所述公共线具有位于所述第二布线区之外且位于所述第一布线区之内的第一段，所述第一段具有在所述行方向上依次排布的第一部、第二部及第三部，所述第三部远离所述扫描线的一侧比所述第一部远离所述扫描线的一侧更远离所述扫描线，所述第二部远离所述扫描线的一侧比所述第一部远离所述扫描线的一侧更靠近所述扫描线，且所述第二部远离所述扫描线的一侧与所述第一部和所述第三部之间形成有缺口；
    其中，所述第一过孔结构在所述第一衬底上的正投影的部分与所述第二部和所述第三部在所述第一衬底上的正投影存在交叠，另一部分与所述缺口在所述第一衬底上的正投影存在交叠；且所述第一过孔结构的边界线与所述第三部的边界线在所述列方向上的间距为第三间距，所述第一过孔结构的边界线与所述第三部中远离所述第二部的边界线在所述行方向上的间距为第四间距，所述第一过孔结构的边界线与所述第二部中远离所述第三部的边界线在所述行方向上的间距为第五间距，所述第三间距、所述第四间距及所述第五间距与所述第一电极条的第一宽度之比为1至6。
  17. 根据权利要求11所述的显示面板，其中，每列数据线与一列子像素单元中各所述子像素单元的晶体管的第一极连接。
  18. 根据权利要求17所述的显示面板，其中，位于所述数据线在所述行方向上相对两侧且相邻的两个第一极与所述数据线在所述行方向上的间距相等。
  19. 根据权利要求17所述的显示面板，其中，在一列子像素单元中，各所述子像素单元中晶体管的第一极和与其相连的数据线在所述行方向上的间距相等。
  20. 根据权利要求17所述的显示面板，其中，位于所述数据线在所述行方向上相对两侧且相邻的两个像素电极关于所述数据线呈对称设置，位于所述数据线在所述行方向上相对两侧且相邻的两个公共电极关于所述数据线呈对称设置。
  21. 根据权利要求14所述的显示面板，其中，还包括：与所述阵列基板对盒设置的对置基板及位于所述对置基板与所述阵列基板之间的液晶分子；
    所述对置基板包括位于所述隔垫物远离所述阵列基板一侧的第二衬底及位于所述第二衬底靠近所述阵列基板一侧的遮挡层，所述遮挡层具有交叉遮挡部、位于所述交叉遮挡部在行方向相对两侧的第一遮挡部、以及位于所述交叉遮挡部在列方向上相对两侧的第二遮挡部；其中，
    所述交叉遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区与所述第二布线区的交叉区域，所述第一遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区且位于与所述第二布线区之外，所述第二遮挡部在所述第一衬底上的正投影至少覆盖所述第二布线区且位于所述第一布线区之外；
    且与所述隔垫物对应的所述交叉遮挡部在列方向上的最大尺寸大于所述第一遮挡部在列方向上的最大尺寸，且所述交叉遮挡部在行方向上的最大尺寸大于所 述第二遮挡部在行方向上的最大尺寸。
  22. 根据权利要求21所述的显示面板，其中，所述隔垫物在所述第二衬底上的正投影位于所述交叉遮挡部在所述第二衬底上的正投影的中心区域内，
    所述隔垫物在所述第二衬底上的正投影的边缘与所述交叉遮挡部在所述第二衬底上的正投影的边缘之间的间距为第六间距，所述第六间距与所述第一电极条的第一宽度之比为11至33。
  23. 根据权利要求21所述的显示面板，其中，所述晶体管在所述第一衬底上的正投影位于所述第一遮挡部在所述第一衬底上的正投影内，所述像素电极具有第一失效区，所述第一失效区与所述第二极通过第二过孔结构连接；其中，所述第一失效区在所述第一衬底上的正投影位于所述第一遮挡部在所述第一衬底上的正投影内，所述第一失效区在所述列方向上的尺寸与所述第一电极条的第一宽度之比为1.5至5.5。
  24. 根据权利要求23所述的显示面板，其中，所述像素电极还具有第二失效区，所述第二失效区在所述第一衬底上的正投影位于所述第二遮挡部在所述第一衬底上的正投影内，其中，
    所述液晶分子为负性液晶分子，所述第二失效区在所述行方向上的尺寸与所述第一电极条的第一宽度之比为0.3至0.5；或
    所述液晶分子为正性液晶分子，所述第二失效区在所述行方向上的尺寸与所述第一电极条的第一宽度之比为2至5.5。
  25. 一种显示装置，其中，包括权利要求11至24中任一项所述的显示面板。
PCT/CN2020/125534 2020-10-30 2020-10-30 电极结构、显示面板及显示装置 WO2022088102A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202080002577.XA CN114981719B (zh) 2020-10-30 2020-10-30 电极结构、显示面板及显示装置
US17/425,397 US11921378B2 (en) 2020-10-30 2020-10-30 Electrode structure, display panel and display device
PCT/CN2020/125534 WO2022088102A1 (zh) 2020-10-30 2020-10-30 电极结构、显示面板及显示装置
US18/396,474 US20240126122A1 (en) 2020-10-30 2023-12-26 Electrode structure, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/125534 WO2022088102A1 (zh) 2020-10-30 2020-10-30 电极结构、显示面板及显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/425,397 A-371-Of-International US11921378B2 (en) 2020-10-30 2020-10-30 Electrode structure, display panel and display device
US18/396,474 Continuation US20240126122A1 (en) 2020-10-30 2023-12-26 Electrode structure, display panel and display device

Publications (1)

Publication Number Publication Date
WO2022088102A1 true WO2022088102A1 (zh) 2022-05-05

Family

ID=81383463

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/125534 WO2022088102A1 (zh) 2020-10-30 2020-10-30 电极结构、显示面板及显示装置

Country Status (3)

Country Link
US (2) US11921378B2 (zh)
CN (1) CN114981719B (zh)
WO (1) WO2022088102A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1374546A (zh) * 2001-03-07 2002-10-16 株式会社日立制作所 液晶显示器
US20070024789A1 (en) * 2005-07-29 2007-02-01 Osamu Itou Liquid crystal display device
CN101344687A (zh) * 2007-07-13 2009-01-14 株式会社日立显示器 液晶显示装置
CN103488002A (zh) * 2013-09-18 2014-01-01 京东方科技集团股份有限公司 像素电极、阵列基板和显示装置
CN109581761A (zh) * 2018-12-29 2019-04-05 厦门天马微电子有限公司 一种阵列基板及显示装置
CN110764329A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 阵列基板及其制备方法、液晶显示面板、显示装置
CN111338144A (zh) * 2020-04-14 2020-06-26 京东方科技集团股份有限公司 显示面板及显示装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11352512A (ja) * 1998-06-05 1999-12-24 Nec Corp 広視野角液晶表示装置
KR100881357B1 (ko) * 1999-09-07 2009-02-02 가부시키가이샤 히타치세이사쿠쇼 액정표시장치
KR20080071231A (ko) * 2007-01-30 2008-08-04 삼성전자주식회사 액정 표시 장치
JP5177887B2 (ja) * 2008-12-19 2013-04-10 株式会社ジャパンディスプレイセントラル 液晶表示装置
CN103364987B (zh) 2013-07-19 2015-11-25 深圳市华星光电技术有限公司 一种阵列基板及显示面板
KR102067966B1 (ko) 2013-08-30 2020-01-20 엘지디스플레이 주식회사 유기발광 다이오드 디스플레이 장치 및 그 제조방법
KR20150098278A (ko) 2014-02-19 2015-08-28 삼성디스플레이 주식회사 표시 장치
JP6470264B2 (ja) 2014-04-15 2019-02-13 株式会社Ｖｔｓタッチセンサー タッチセンサ用電極、タッチパネル、および、表示装置
CN104516162B (zh) 2014-12-16 2017-01-25 南京中电熊猫液晶显示科技有限公司 一种垂直配向型液晶显示面板
CN106526937B (zh) 2016-12-06 2019-10-29 昆山龙腾光电有限公司 Tft阵列基板、液晶显示面板和显示装置
CN106684101B (zh) * 2017-02-15 2019-12-20 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
KR102555144B1 (ko) 2017-12-29 2023-07-12 엘지디스플레이 주식회사 디스플레이 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1374546A (zh) * 2001-03-07 2002-10-16 株式会社日立制作所 液晶显示器
US20070024789A1 (en) * 2005-07-29 2007-02-01 Osamu Itou Liquid crystal display device
CN101344687A (zh) * 2007-07-13 2009-01-14 株式会社日立显示器 液晶显示装置
CN103488002A (zh) * 2013-09-18 2014-01-01 京东方科技集团股份有限公司 像素电极、阵列基板和显示装置
CN109581761A (zh) * 2018-12-29 2019-04-05 厦门天马微电子有限公司 一种阵列基板及显示装置
CN110764329A (zh) * 2019-10-31 2020-02-07 京东方科技集团股份有限公司 阵列基板及其制备方法、液晶显示面板、显示装置
CN111338144A (zh) * 2020-04-14 2020-06-26 京东方科技集团股份有限公司 显示面板及显示装置

Also Published As

Publication number Publication date
US20240126122A1 (en) 2024-04-18
US20220373843A1 (en) 2022-11-24
CN114981719A (zh) 2022-08-30
US11921378B2 (en) 2024-03-05
CN114981719B (zh) 2023-09-01

Similar Documents

Publication Publication Date Title
US9151992B2 (en) Color filter substrate and liquid crystal display device including the same
US6912024B2 (en) Array substrate of liquid crystal display device having thin film transistor on color filter structure and method of fabricating the same
WO2021208643A1 (zh) 显示面板及显示装置
US20050243232A1 (en) Array substrate for liquid crystal display device and fabricating method thereof
CN214375724U (zh) 显示面板及电子设备
WO2021212620A1 (zh) 液晶显示面板及显示装置
WO2022193692A1 (zh) 显示面板与显示装置
CN101950101A (zh) 液晶显示面板
US8304768B2 (en) Thin film transistor array substrate and method for manufacturing the same
TWI635342B (zh) 顯示面板
TW201901267A (zh) 陣列基板及液晶顯示面板
WO2022088102A1 (zh) 电极结构、显示面板及显示装置
TWI643009B (zh) 畫素結構以及包含此畫素結構的顯示面板
US20230152635A1 (en) Display panel and display device
CN214896130U (zh) 显示面板与显示装置
WO2022152223A1 (zh) 电极结构、显示面板及电子设备
US11971620B2 (en) Display panel and electronic device
WO2022151836A1 (zh) 显示面板及电子设备
WO2022193710A1 (zh) 阵列基板与显示装置
CN215006188U (zh) 阵列基板与显示装置
WO2022246794A1 (zh) 阵列基板及其制作方法、显示装置
KR20130064262A (ko) 박막트랜지스터 기판 및 그 제조 방법
EP4209835A1 (en) Pixel electrode, array substrate, and display apparatus
WO2023184426A1 (zh) 阵列基板、显示面板及显示装置
CN114967254A (zh) 阵列基板及液晶显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20959263

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 17/08/2023)

122 Ep: pct application non-entry in european phase

Ref document number: 20959263

Country of ref document: EP

Kind code of ref document: A1