JP6572388B2 - Ips型tft−lcdアレイ基板の製造方法及びips型tft−lcdアレイ基板 - Google Patents
Ips型tft−lcdアレイ基板の製造方法及びips型tft−lcdアレイ基板 Download PDFInfo
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- JP6572388B2 JP6572388B2 JP2018519435A JP2018519435A JP6572388B2 JP 6572388 B2 JP6572388 B2 JP 6572388B2 JP 2018519435 A JP2018519435 A JP 2018519435A JP 2018519435 A JP2018519435 A JP 2018519435A JP 6572388 B2 JP6572388 B2 JP 6572388B2
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- 239000000758 substrate Substances 0.000 title claims description 105
- 238000004519 manufacturing process Methods 0.000 title claims description 37
- 239000010410 layer Substances 0.000 claims description 221
- 239000011241 protective layer Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 67
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000000059 patterning Methods 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 20
- 238000000576 coating method Methods 0.000 claims description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 16
- 239000011248 coating agent Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 229910052750 molybdenum Inorganic materials 0.000 claims description 11
- 239000011733 molybdenum Substances 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 9
- -1 aluminum tin oxide Chemical compound 0.000 claims description 8
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 8
- RQIPKMUHKBASFK-UHFFFAOYSA-N [O-2].[Zn+2].[Ge+2].[In+3] Chemical compound [O-2].[Zn+2].[Ge+2].[In+3] RQIPKMUHKBASFK-UHFFFAOYSA-N 0.000 claims description 7
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000012044 organic layer Substances 0.000 claims description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 239000011787 zinc oxide Substances 0.000 claims 1
- 239000004973 liquid crystal related substance Substances 0.000 description 24
- 239000010408 film Substances 0.000 description 18
- 230000005684 electric field Effects 0.000 description 10
- 239000010409 thin film Substances 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
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- 238000003860 storage Methods 0.000 description 2
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- FYQBHPUWNUUKIH-UHFFFAOYSA-N [Zn].[In].[Ge] Chemical compound [Zn].[In].[Ge] FYQBHPUWNUUKIH-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Description
101、11 ゲート電極
102、12 ゲート電極絶縁層
103、13 半導体層
104、14 ソース電極
105、15 ドレイン電極
106、16 絶縁保護層
107、17 画素電極
110、20 ゲート電極走査線
120 共通電極層
161 ビアホール
162 チャネル
18 共通電極
30 データ線
Claims (11)
- IPS型TFT−LCDアレイ基板の製造方法であって、
その製造方法は、
基板を提供し、前記基板上にゲート電極金属層を堆積するとともに、前記ゲート電極金属層にパターニング処理を施し、ゲート電極及びゲート電極走査線を取得する手順1と、
ゲート電極金属層上にゲート電極絶縁層を堆積し、前記ゲート電極絶縁層上に一層のアモルファスシリコン層を堆積するとともに、アモルファスシリコン層にn型ドーピングを行った後、前記アモルファスシリコン層にパターニング処理を施し、前記ゲート電極の上方に対応する半導体層を取得する手順2と、
前記半導体層及びゲート電極絶縁層上にソース・ドレイン電極金属層を堆積するとともに、前記ソース・ドレイン電極の金属層にパターニング処理を施し、ソース電極、ドレイン電極、及びデータ線を取得し、前記ソース電極とドレイン電極を、それぞれ前記半導体層の両端と互いに接触させ、そのうち、データ線とゲート電極走査線が囲むことにより、複数の画素領域を形成する手順3と、
前記ソース・ドレイン電極金属層上に絶縁保護層を形成するとともに、絶縁保護層にパターニング処理を施し、前記絶縁保護層上に前記ドレイン電極の上方に対応するビアホールと画素領域内に位置する複数の互いに平行した棒状のチャネルを形成し、隣り合う前記チャネルの間に前記絶縁保護層からなる棒状の突起が残るようにする手順4と、
前記絶縁保護層上に一層の透明導電層を堆積するとともに、前記透明導電層にパターニング処理を施し、画素電極及び共通電極を取得し、前記画素電極をビアホールによってドレイン電極と互いに接触させ、前記画素電極と共通電極を、各画素領域内に、間隔を置いて設置し、前記画素電極と共通電極を、チャネルの両側の突起に沿って交互に分布させるとともにチャネルの側壁にまで延在させる手順5と、からなり、
前記手順4において、前記チャネルのそれぞれは前記データ線に平行であって、各前記画素領域内において前記ゲート電極走査線の方向に沿って4本の前記チャネルが並ぶように形成され、
前記4本のチャネルを第1チャネル、第2チャネル、第3チャネル、第4チャネル、とし、前記第1チャネルと前記第2チャネルとの間の前記突起を第1棒状突起とし、前記第2チャネルと前記第3チャネルとの間の前記突起を第2棒状突起とし、前記第3チャネルと前記第4チャネルとの間の前記突起を第3棒状突起とし、
前記手順5において、前記画素電極は、平面視でコ字状であって、前記第1棒状突起と前記第3棒状突起との上に前記コ字の互いに向かい合う二本の辺に相当する部分を有し、前記コ字の残りの辺は平面視したときに前記ドレイン電極に重なる位置にあって、この画素電極の周囲をエッチングすることによって孤立した当該画素電極を形成するとともに、前記透明電極のうちの当該画素電極以外の領域を共通電極とする
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 請求項1に記載のIPS型TFT−LCDアレイ基板の製造方法において、
前記手順1では、物理蒸着法によりゲート電極金属層を堆積し、
堆積されたゲート電極金属層の膜厚は3000〜6000Åであり、
前記ゲート電極金属層の材料は、モリブデン、チタン、アルミニウム、銅のうちの1つまたは複数を組み合わせて積み重ねたものであり、
前記ゲート電極金属層にパターニング処理を施す手順には、順番にフォトレジスト塗布、露光、現像、ウェットエッチング、及びフォトレジスト剥離が含まれる
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 請求項1に記載のIPS型TFT−LCDアレイ基板の製造方法において、
前記手順2では、化学蒸着法によってゲート電極絶縁層とアモルファスシリコン層を堆積し、
堆積されたゲート電極絶縁層の膜厚は2000〜5000Åであり、
堆積されたアモルファスシリコン層の膜厚は1500〜3000Åであり、
前記ゲート電極絶縁層は窒化シリコン層であり、
前記アモルファスシリコン層にパターニング処理を施す手順には、順番にフォトレジスト塗布、露光、現像、ドライエッチング、及びフォトレジスト剥離が含まれる
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 請求項1に記載のIPS型TFT−LCDアレイ基板の製造方法において、
前記手順3では、物理蒸着法によりソース・ドレイン電極金属層を堆積し、
堆積されたソース・ドレイン電極金属層の膜厚は3000〜6000Åであり、
前記ソース・ドレイン電極金属層の材料は、モリブデン、チタン、アルミニウム、銅のうちの1つまたは複数を組み合わせて積み重ねたものであり、
前記ソース・ドレイン電極金属層にパターニング処理を施す手順には、順番にフォトレジスト塗布、露光、現像、ウェットエッチング、及びフォトレジスト剥離が含まれる
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 請求項1に記載のIPS型TFT−LCDアレイ基板の製造方法において、
前記手順4において形成された絶縁保護層は、窒化シリコン層と、窒化シリコン層上に設けられる有機膜層を備え、
前記絶縁保護層の窒化シリコン層の膜厚は2000〜5000Åであり、化学蒸着法によって形成され、前記絶縁保護層の有機膜層の膜厚は0.2〜0.4μmであり、コーティングプロセスによって形成され、
前記絶縁保護層にパターニング処理を施す手順には、順番にフォトレジスト塗布、露光、現像、ドライエッチング、及びフォトレジスト剥離が含まれる
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 請求項1に記載のIPS型TFT−LCDアレイ基板の製造方法において、
前記手順5では、物理蒸着法により透明導電層を堆積し、
堆積された透明導電層の膜厚は400〜1000Åであり、前記透明導電層の材料は、インジウム錫酸化物、インジウム亜鉛酸化物、アルミニウム錫酸化物、アルミニウム酸化亜鉛、インジウムゲルマニウム亜鉛酸化物のうちの1つまたは複数であり、
前記透明導電層にパターニング処理を施す手順には、順番にフォトレジスト塗布、露光、現像、ウェットエッチング、及びフォトレジスト剥離が含まれる
ことを特徴とするIPS型TFT−LCDアレイ基板の製造方法。 - 基板と、前記基板上に設けられる複数のゲート電極走査線と、複数のデータ線と、複数のゲート電極走査線と複数のデータ線が互いに絶縁し且つ交差して画定されてなる複数のアレイ状に配置された画素単位と、からなるIPS型TFT−LCDアレイ基板であって、
各画素単位は、基板上に形成されるゲート電極と、ゲート電極及び基板上に形成されるゲート電極絶縁層と、ゲート電極上方に対応するとともにゲート電極絶縁層上に形成される半導体層と、半導体層とゲート電極絶縁層上に形成されるソース電極とドレイン電極と、前記ソース電極、ドレイン電極、半導体層、及びゲート電極絶縁層上に形成される絶縁保護層と、前記絶縁保護層上に形成される画素電極と共通電極を備え、
前記ソース電極とドレイン電極は、それぞれ前記半導体層の両端と互いに接触し、
前記絶縁保護層上の前記ドレイン電極に対応する上方にはビアホールが設けられ、前記画素電極は、ビアホールによって前記ドレイン電極と互いに接触し、
前記絶縁保護層上には、画素単位範囲内に位置する複数の互いに平行した棒状のチャネルが設けられ、
前記チャネルのそれぞれは前記データ線に平行であって、各前記画素領域内において前記ゲート電極走査線の方向に沿って4本の前記チャネルが並ぶように形成され、
前記4本のチャネルを第1チャネル、第2チャネル、第3チャネル、第4チャネル、とし、前記第1チャネルと前記第2チャネルとの間の前記突起を第1棒状突起とし、前記第2チャネルと前記第3チャネルとの間の前記突起を第2棒状突起とし、前記第3チャネルと前記第4チャネルとの間の前記突起を第3棒状突起とし、
前記画素電極と共通電極は、同じ透明導電層によってパターニングされることによって取得され、前記画素電極と共通電極は、各画素単位の範囲内に、間隔を置いて設置され、前記画素電極と共通電極は、チャネルの両側の突起に沿って交互に分布するとともにチャネルの側壁にまで延在しており、
前記画素電極は、平面視でコ字状であって、前記第1棒状突起と前記第3棒状突起との上に前記コ字の互いに向かい合う二本の辺に相当する部分を有し、前記コ字の残りの辺は平面視したときに前記ドレイン電極に重なる位置にあって、この画素電極の周囲がエッチングされることによって孤立した当該画素電極が形成されているとともに、前記透明電極のうちの当該画素電極以外の領域が共通電極となっている
ことを特徴とするIPS型TFT−LCDアレイ基板。 - 請求項7に記載のIPS型TFT−LCDアレイ基板において、
前記画素電極と共通電極の材料は透明導電材料であり、前記透明導電材料は、インジウム錫酸化物、インジウム亜鉛酸化物、アルミニウム錫酸化物、アルミニウム酸化亜鉛、インジウムゲルマニウム亜鉛酸化物のうちの1つまたは複数であり、前記画素電極と共通電極の膜厚は400〜1000Åである
ことを特徴とするIPS型TFT−LCDアレイ基板。 - 請求項7に記載のIPS型TFT−LCDアレイ基板において、
前記ソース・ドレイン電極金属層の材料は、モリブデン、チタン、アルミニウム、銅のうちの1つまたは複数を組み合わせて積み重ねたものであり、前記ソース・ドレイン電極金属層の膜厚は3000〜6000Åである
ことを特徴とするIPS型TFT−LCDアレイ基板。 - 請求項7に記載のIPS型TFT−LCDアレイ基板において、
前記絶縁保護層は、窒化シリコン層と、窒化シリコン層上に設けられる有機膜層を備え、前記絶縁保護層の窒化シリコン層の膜厚は2000〜5000Åであり、前記絶縁保護層の有機膜層の膜厚は0.2〜0.4μmである
ことを特徴とするIPS型TFT−LCDアレイ基板。 - 基板と、前記基板上に設けられる複数のゲート電極走査線と、複数のデータ線と、複数のゲート電極走査線と複数のデータ線が互いに絶縁し且つ交差して画定されてなる複数のアレイ状に配置された画素単位と、からなるIPS型TFT−LCDアレイ基板であって、
各画素単位は、基板上に形成されるゲート電極と、ゲート電極及び基板上に形成されるゲート電極絶縁層と、ゲート電極上方に対応するとともにゲート電極絶縁層上に形成される半導体層と、半導体層とゲート電極絶縁層上に形成されるソース電極とドレイン電極と、前記ソース電極、ドレイン電極、半導体層、及びゲート電極絶縁層上に形成される絶縁保護層と、前記絶縁保護層上に形成される画素電極と共通電極を備え、
前記ソース電極とドレイン電極は、それぞれ前記半導体層の両端と互いに接触し、
前記絶縁保護層上の前記ドレイン電極に対応する上方にはビアホールが設けられ、前記画素電極は、ビアホールによって前記ドレイン電極と互いに接触し、
前記絶縁保護層上には、画素単位範囲内に位置する複数の互いに平行した棒状のチャネルが設けられ、
前記チャネルのそれぞれは前記データ線に平行であって、各前記画素領域内において前記ゲート電極走査線の方向に沿って4本の前記チャネルが並ぶように形成され、
前記4本のチャネルを第1チャネル、第2チャネル、第3チャネル、第4チャネル、とし、前記第1チャネルと前記第2チャネルとの間の前記突起を第1棒状突起とし、前記第2チャネルと前記第3チャネルとの間の前記突起を第2棒状突起とし、前記第3チャネルと前記第4チャネルとの間の前記突起を第3棒状突起とし、
前記画素電極と共通電極は、同じ透明導電層によってパターニングされることによって取得され、前記画素電極と共通電極は、各画素単位の範囲内に、間隔を置いて設置され、前記画素電極と共通電極は、チャネルの両側の突起に沿って交互に分布するとともにチャネルの側壁にまで延在しており、
前記画素電極は、平面視でコ字状であって、前記第1棒状突起と前記第3棒状突起との上に前記コ字の互いに向かい合う二本の辺に相当する部分を有し、前記コ字の残りの辺は平面視したときに前記ドレイン電極に重なる位置にあって、この画素電極の周囲がエッチングされることによって孤立した当該画素電極が形成されているとともに、前記透明電極のうちの当該画素電極以外の領域が共通電極となっていて、
そのうち、前記画素電極と共通電極の材料は透明導電材料であり、前記透明導電材料は、インジウム錫酸化物、インジウム亜鉛酸化物、アルミニウム錫酸化物、アルミニウム酸化亜鉛、インジウムゲルマニウム亜鉛酸化物のうちの1つまたは複数であり、前記画素電極と共通電極の膜厚は400〜1000Åであり、
そのうち、前記ソース・ドレイン電極金属層の材料は、モリブデン、チタン、アルミニウム、銅のうちの1つまたは複数を組み合わせて積み重ねたものであり、前記ソース・ドレイン電極金属層の膜厚は3000〜6000Åであり、
そのうち、前記絶縁保護層は、窒化シリコン層と、窒化シリコン層上に設けられる有機膜層を備え、前記絶縁保護層の窒化シリコン層の膜厚は2000〜5000Åであり、前記絶縁保護層の有機膜層の膜厚は0.2〜0.4μmである
ことを特徴とするIPS型TFT−LCDアレイ基板。
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