CN102629588B - Method for manufacturing array substrate - Google Patents
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- CN102629588B CN102629588B CN201110415306.XA CN201110415306A CN102629588B CN 102629588 B CN102629588 B CN 102629588B CN 201110415306 A CN201110415306 A CN 201110415306A CN 102629588 B CN102629588 B CN 102629588B
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- passivation layer
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- base palte
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Abstract
The invention, which relates to the liquid crystal display technology field, discloses a method for manufacturing an array substrate, so that a problem that there is great possibility to reduce cost in the existing manufacturing method for an array substrate can be solved. The manufacturing method comprises: forming a graph containing a gate electrode and a gate line; forming a graph containing a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a via hole on the passivation layer by utilizing a one-time composition process; and forming a graph containing a pixel electrode. During the whole manufacturing process for the array substrate, only three mask plates are used; therefore, compared with the existing 4-mask technology, the employed technology in the invention enables the manufacturing cost of the array substrate to be further reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to the manufacture method of array base palte.
Background technology
Array base palte is one of chief component of Thin Film Transistor-LCD (TFT LCD), in the process of manufacturing array substrate, by reducing the quantity of the lithography mask version (Mask) using, the manufacturing cost of array base palte can be significantly reduced, and then the manufacturing cost of TFT LCD can be reduced.
Fig. 1 shows the have bottom gate thin film transistor typical structure of array base palte of (TFT), and it is formed with successively from bottom to up on substrate 11: gate electrode 12, gate insulator 13, active layer 14, source electrode 15, drain electrode 16, passivation layer 17 and pixel electrode 18.In addition, in passivation layer 16, be also formed with for being electrically connected to the pixel electrode via hole 19 of pixel electrode 18 and drain electrode 16.Wherein, owing to there is difference in height between gate electrode 12 surfaces and substrate 11 surfaces, therefore, each more than 12 layer of gate electrode all has jump in the region corresponding to gate electrode 12 edges, thereby formed step-like source electrode 15 and step-like drain electrode 16.
The method of the array base palte shown in existing shop drawings 1 has been current 4Mask technology from initial 7Mask technical development, and 4 Mask are respectively used to form: the pixel electrode of the gate electrode of patterning, the active layer of patterning and source/drain electrode, pixel electrode via hole, patterning.
In manufacturing the process of above-mentioned array base palte, inventor finds: although 4Mask technology is compared with 7Mask technology, in technological process, greatly simplify, utilization rate of equipment and installations and production capacity also significantly improve, and it still exists the larger space reducing costs.
Summary of the invention
Embodiments of the invention provide a kind of manufacture method of array base palte, can further reduce the quantity of used mask plate, further to reduce the manufacturing cost of array base palte.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A manufacture method for array base palte, comprising:
Formation comprises the figure of grid and grid line;
By a composition technique, form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole;
Formation comprises the figure of pixel electrode.
Further, the active layer of described array base palte comprises intrinsic semiconductor layer and doping semiconductor layer, in the described plasma ashing technique of utilizing, remove the photoresist of described the first recess, then, after etching away source/leakage metal level of channel region, also comprise the doping semiconductor layer that etches away channel region.
Further, the described figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole by a composition technique formation, specifically comprises:
Form gate insulation layer, active layer and source/leakage metal level;
Coating photoresist, by duotone mask plate, expose, develop, removal is positioned at TFT regions with the photoresist of exterior domain, in TFT regions, form photoetching agent pattern, described photoetching agent pattern comprises corresponding to the first recess of channel region and corresponding to the second recess of lower region in the electrode of step-like source, and the thickness of the photoresist that wherein the second recess retains is greater than the thickness of the photoresist that the first recess retains;
Source/leakage the metal level and the active layer that etch away the region that does not cover described photoetching agent pattern, expose described gate insulation layer;
Utilize plasma ashing technique, remove the photoresist of described the first recess, then etch away source/leakage metal level of channel region;
Utilize plasma ashing technique, get rid of the photoresist in region top, in step-like drain electrode lower region;
Form passivation layer, the thickness of described passivation layer is less than the thickness of the photoresist that drain electrode region retains, so that described passivation layer forms tomography above the photoresist of described reservation;
Remove described reservation photoresist and on described passivation layer, to form passivation layer via hole in the described passivation layer above described drain electrode.
Further, described formation comprises the figure of grid and grid line, specifically comprises:
On substrate, deposit grid metal level, utilize common mask board to explosure, development and etching, obtain comprising the figure of grid and grid line.
Further, described formation comprises the figure of pixel electrode, specifically comprises:
On described passivation layer and in described passivation layer via hole, form pixel electrode film;
Utilize common mask plate to carry out patterning to described pixel electrode film, to form the figure that comprises pixel electrode.
Further, when the thickness of described grid is 250nm, the thickness of described passivation layer is 200nm.
Further, the material of described grid is one of in aluminium, copper, molybdenum, chromium or combination in any.
Further, described passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, or is the composite membrane that in silicon nitride, silica, silicon oxynitride, combination in any forms.
Further, the formation technique of described grid metal level, described source/leakage metal level is sputtering technology.
Further, the formation technique of described gate insulation layer, described active layer and described passivation layer is chemical vapor deposition method.
In the manufacture method of the array base palte that the embodiment of the present invention provides, owing to forming by a composition technique figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole, make only to have used three mask plates in the manufacture process of whole array base palte, than existing 4Ma sk technology, further lowered the manufacturing cost of array base palte.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 has the generalized section of the array base palte of bottom gate thin film transistor in prior art;
The generalized section of the array base palte manufacturing process that Fig. 2 A～2L provides for the embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of manufacture method of array base palte, comprising: form the figure that comprises grid and grid line; By a composition technique, form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole; Formation comprises the figure of pixel electrode.
Preferably, the described figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole by a composition technique formation, specifically comprises:
Form gate insulation layer, active layer and source/leakage metal level;
Coating photoresist, by duotone mask plate, expose, develop, removal is positioned at TFT regions with the photoresist of exterior domain, in TFT regions, form photoetching agent pattern, described photoetching agent pattern comprises corresponding to the first recess of channel region and corresponding to the second recess of lower region in the electrode of step-like source, and the thickness of the photoresist that wherein the second recess retains is greater than the thickness of the photoresist that the first recess retains;
Carry out dry etching, etch away source/leakage metal level and the active layer in the region that does not cover described photoetching agent pattern, expose described gate insulation layer;
Utilize plasma ashing technique, remove the photoresist of described the first recess, then etch away source/leakage metal level of channel region;
Utilize plasma ashing technique, get rid of the photoresist in region top, in step-like drain electrode lower region;
Form passivation layer, the thickness of described passivation layer is less than the thickness of the photoresist that drain electrode region retains, so that described passivation layer forms tomography above the photoresist of described reservation;
Remove described reservation photoresist and on described passivation layer, to form passivation layer via hole in the described passivation layer above described drain electrode.
In the manufacture method of the array base palte that the embodiment of the present invention provides, owing to forming by a composition technique figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole, make only to have used three mask plates in the manufacture process of whole array base palte, than existing 4Ma sk technology, further lowered the manufacturing cost of array base palte.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
In an embodiment of the present invention, composition technique, comprises that exposure, development, etching etc. form the technique of figure; Source/drain electrode refers to source electrode and drain electrode; Source/leakage metal level, the metal of finger-type Cheng Yuan/drain electrode.A composition technique, refers to use the composition technique of a mask plate (mask).
The embodiment of the present invention provides a kind of manufacture method of array base palte, with reference to Fig. 2 A～Fig. 2 L, the method is elaborated.
Step 1, formation comprise the figure of grid and grid line.
This step can adopt any prior art that can realize by a composition technique to realize.Such as, utilize common mask technique to realize, as shown in Figure 2 A, by common mask plate (not shown), the gate metal layer (not shown) on substrate 201 is carried out to patterning, with the figure that comprises grid 202 and grid line (not shown) of the patterning that forms.Particularly, comprising: at the upper deposition of substrate (substrate) grid metal level, utilize common mask board to explosure, development and etching, obtain comprising the figure of grid and grid line.
Common (routine) mask plate refers to the mask plate with He Fei transparent area, transparent area conventionally using, by this first conventional mask plate, the photoresist layer being formed in gate metal layer is carried out after exposure imaging, in the gate metal layer that needs to retain, be coated with photoresist, and photoresist in the gate metal layer that does not need to retain is removed, pass through etch step, unwanted gate metal layer is etched away, and remaining gate metal layer is the gate electrode 202 of required patterning.
The technique that forms gate metal layer can be sputtering technology, other technique that also can be known to those skilled in the art.
Step 2, by composition technique, form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole.
Said method, can adopt masstone (Multi-tone) mask plate to realize, and also can adopt duotone mask plate binding plasma ashing, the liftoff technique such as peel off to realize.Wherein, liftoff peeling off refers to the film material that simultaneously peels off photoresist top by peeling off of the photoresist below rete, realizes the technique of some specific pattern, and specific implementation process can be referring to the description of following specific embodiment.
The present embodiment will be introduced in detail below, adopt duotone mask plate binding plasma ashing, the liftoff technique such as peel off to realize the technical scheme that forms the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole by composition technique.
Particularly, comprise the steps:
Particularly, on the substrate 201 of grid 202 and grid line, form successively from the bottom to top gate insulator 203, active layer 204 and source/leakage metal level 205 comprising.Wherein, the technique that forms gate insulator 203 and active layer 204 can be chemical vapor deposition method, can be also other technique known to those skilled in the art; The technique of formation source/leakage metal level can be sputtering technology, other technique that also can be known to those skilled in the art.
As shown in Fig. 2 C and Fig. 2 D, this step has specifically been included on the described substrate 201 of described step 201 and has formed a photoresist layer 206 again, (this sentences gray-tone mask plate is example to use gray level mask plate 207, also can use other duotone mask plates, such as half-tone mask plate etc.) this photoresist layer 206 is exposed.Because gray level mask plate 207 comprises corresponding to the first half exposure region A1 of the channel region that will form and corresponding to the second half exposure region A2 of lower region in the step-like source electrode that will form, after using 207 pairs of these photoresist layers 206 of this gray level mask plate to expose, develop, can be on photoresist layer 206 form corresponding to the first recess B1 of described channel region and corresponding to the second recess B2 of lower region in the electrode of described step-like source.
On gray level mask plate 207, also comprise the first light shielding part A3 corresponding to upper zone in the electrode of described step-like source, and corresponding to the second light shielding part A4 of the step-like drain electrode that will form, on gray level mask plate 207 corresponding to the Dou Wei transparent area, region of substrate 201 other parts.Therefore, after this photoresist layer 206 is exposed, is developed, can form the photoetching agent pattern 206 shown in Fig. 2 D ', and this photoetching agent pattern 206 ' only cover region of the thin-film transistor that will form.
By described photoetching agent pattern 206 ' carry out etching to completing the described substrate of described step 202, as shown in Figure 2 D, etch away source/leakage metal level 205 and the active layer 204 in the region that does not cover photoetching agent pattern, to expose described gate insulator 203 on the substrate not covering described photoetching agent pattern, and form source/leakage metal level 205 of patterning ' and the active layer 204 of patterning ', obtain figure as shown in Figure 2 E.When source/leakage metal level is carried out to etching, wet etching can be adopted, when active layer is carried out to etching, dry etching can be adopted.
To completing the substrate of above-mentioned technique, carry out plasma ashing processing, remove the photoresist of the first recess B1, form photoetching offset plate figure 206 as shown in Figure 2 F ".It will be appreciated by those skilled in the art that, when plasma ashing is processed, the photoresist in other regions also can be removed identical thickness, but because the photoresist thickness in other regions is all greater than the photoresist of the first recess B1, when the photoresist of the first recess B1 is removed, other regions still remain with photoresist.
Utilize photoetching offset plate figure 206 as shown in Figure 2 F ", etch away source/leakages metal level of channel region, formation figure as shown in Figure 2 G, forms source electrode 208 and drain electrode 209.
When active layer is the semiconductor layer of intrinsic semiconductor and doped semiconductor formation, need to further etch away the doping semiconductor layer of channel region.When active layer is organic semiconductor or metal oxide, only need etching source/leakage metal level.
Substrate shown in Fig. 2 G is carried out to plasma ashing PROCESS FOR TREATMENT, owing to being provided with the second recess on photoetching agent pattern, the photoresist shape of electrode 208 tops, step-like source and the shape of step-like source electrode 208 are matched, when carrying out cineration step, photoresist and the photoresist in upper zone in the electrode 208 of step-like source on lower region can be completely removed at synchronization.Again because the photoresist above step-like drain electrode 209 has an even surface, do not there is the shape matching with step-like drain electrode 209, therefore in podzolic process, when the photoresist in step-like drain electrode 209 in upper zone is etched away completely, on lower region, also can remain some photoresists, thereby form the residual portion 210 of photoresist (photoresist of reservation).That is, got rid of the photoresist in region top, in step-like drain electrode lower region, as shown in Fig. 2 H.
Particularly, the formation technique of passivation layer can be chemical vapor deposition method, or other technique known to those skilled in the art.As shown in Fig. 2 I, because the thickness of passivation layer 211 is less than the thickness of the residual portion 210 of described photoresist, therefore, above the residual portion 210 of described photoresist, passivation layer 211 forms tomographies, and the passivation layer 211 at this place is discontinuous.
In Practical manufacturing technique, the thickness of the residual portion 210 of photoresist under normal conditions can be identical with the thickness of grid, therefore, as long as the thickness of passivation layer 211 is less than the thickness of gate electrode, can form above-mentioned tomography equally.When the thickness of gate electrode is 250nm, the thickness of passivation layer 211 is preferably 200nm, can not only form above-mentioned tomography, can also embody excellent insulation property.
Particularly, utilize stripper that the photoresist 210 (the residual portion of photoresist) retaining is carried out to lift-off processing, the passivation layer of the photoresist top retaining also can be peeled off along with the peeling off of photoresist retaining (being liftoff stripping technology herein) together, thereby in the described passivation layer 211 on described drain electrode 209, form passivation layer via hole 212, as shown in Fig. 2 J.
Step 3, formation comprise the figure of pixel electrode.
Wherein a kind of implementation method can be, specifically comprises: as shown in Fig. 2 K, form pixel electrode film 213 (such as indium tin oxide films etc.) on described passivation layer 211 and in described passivation layer via hole 212; As shown in Fig. 2 L, utilize common mask plate to carry out patterning to described pixel electrode film, with form comprise pixel electrode 213 ' figure.
Particularly, the formation technique of pixel electrode film 213 can be sputtering technology, or other technique known to those skilled in the art.
By this common mask plate to after being formed on photoresist layer on indium tin oxide films and exposing, develop, on the pixel electrode film that needs to retain, be coated with photoresist, and photoresist on the pixel electrode film that does not need to retain is removed, pass through etch step, unwanted indium tin oxide films is etched away, remaining pixel electrode film be the pixel electrode 213 of required patterning '.
It should be noted that: the material of described grid metal level can be for one of in aluminium, copper, molybdenum, chromium or combination in any; Described passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, or is the composite membrane that in silicon nitride, silica, silicon oxynitride, combination in any forms.
In the manufacture method of the array base palte that the embodiment of the present invention provides, owing to forming by a composition technique figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole, make only to have used three mask plates in the manufacture process of whole array base palte, than existing 4Mask technology, further lowered the manufacturing cost of array base palte.
The embodiment of the present invention is mainly used in the manufacture of liquid crystal indicator.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (9)
1. a manufacture method for array base palte, is characterized in that, comprising:
Formation comprises the figure of grid and grid line;
By a composition technique, form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole;
Formation comprises the figure of pixel electrode;
The described figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole by a composition technique formation, specifically comprises:
Form gate insulation layer, active layer and source/leakage metal level;
Coating photoresist, by duotone mask plate, expose, develop, removal is positioned at TFT regions with the photoresist of exterior domain, in TFT regions, form photoetching agent pattern, described photoetching agent pattern comprises corresponding to the first recess of channel region and corresponding to the second recess of lower region in the electrode of step-like source, and the thickness of the photoresist that wherein the second recess retains is greater than the thickness of the photoresist that the first recess retains;
Source/leakage the metal level and the active layer that etch away the region that does not cover described photoetching agent pattern, expose described gate insulation layer;
Utilize plasma ashing technique, remove the photoresist of described the first recess, then etch away source/leakage metal level of channel region;
Utilize plasma ashing technique, get rid of the photoresist in region top, in step-like drain electrode lower region;
Form passivation layer, the thickness of described passivation layer is less than the thickness of the photoresist that drain electrode region retains, so that described passivation layer forms tomography above the photoresist of described reservation;
Remove described reservation photoresist and on described passivation layer, to form passivation layer via hole in the described passivation layer above described drain electrode.
2. the manufacture method of array base palte according to claim 1, it is characterized in that, the active layer of described array base palte comprises intrinsic semiconductor layer and doping semiconductor layer, in the described plasma ashing technique of utilizing, remove the photoresist of described the first recess, then, after etching away source/leakage metal level of channel region, also comprise the doping semiconductor layer that etches away channel region.
3. the manufacture method of array base palte according to claim 1, is characterized in that, described formation comprises the figure of grid and grid line, specifically comprises:
On substrate, deposit grid metal level, utilize common mask board to explosure, development and etching, obtain comprising the figure of grid and grid line.
4. the manufacture method of array base palte according to claim 1, is characterized in that, described formation comprises the figure of pixel electrode, specifically comprises:
On described passivation layer and in described passivation layer via hole, form pixel electrode film;
Utilize common mask plate to carry out patterning to described pixel electrode film, to form the figure that comprises pixel electrode.
5. the manufacture method of array base palte according to claim 1, is characterized in that, when the thickness of described grid is 250nm, the thickness of described passivation layer is 200nm.
6. the manufacture method of array base palte according to claim 1, is characterized in that, the material of described grid is one of in aluminium, copper, molybdenum, chromium or combination in any.
7. the manufacture method of array base palte according to claim 1, is characterized in that, described passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, or is the composite membrane that in silicon nitride, silica, silicon oxynitride, combination in any forms.
8. the manufacture method of array base palte according to claim 2, is characterized in that, the formation technique of grid metal level, described source/leakage metal level is sputtering technology.
9. the manufacture method of array base palte according to claim 1, is characterized in that, the formation technique of described gate insulation layer, described active layer and described passivation layer is chemical vapor deposition method.
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| CN103500730B (en) * | 2013-10-17 | 2016-08-17 | 北京京东方光电科技有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN103700707B (en) * | 2013-12-18 | 2018-12-11 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), array substrate and preparation method thereof, display device |
| CN105977210A (en) * | 2016-05-20 | 2016-09-28 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN106449666B (en) * | 2016-12-02 | 2018-04-03 | 京东方科技集团股份有限公司 | Array base palte and display device |
| CN111192855A (en) * | 2018-11-14 | 2020-05-22 | 惠科股份有限公司 | Manufacturing method of array substrate, display panel and display device |
| CN109616510B (en) | 2018-12-03 | 2020-04-14 | 惠科股份有限公司 | Thin film transistor structure, manufacturing method thereof and display device |
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| CN101452163A (en) * | 2007-12-07 | 2009-06-10 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and method for manufacturing same |
| CN101770121A (en) * | 2008-12-26 | 2010-07-07 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
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| JP2005215275A (en) * | 2004-01-29 | 2005-08-11 | Quanta Display Japan Inc | Liquid crystal display and its manufacturing method |
| CN101807550B (en) * | 2009-02-18 | 2013-05-22 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and LCD monitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101452163A (en) * | 2007-12-07 | 2009-06-10 | 北京京东方光电科技有限公司 | TFT-LCD array substrate structure and method for manufacturing same |
| CN101770121A (en) * | 2008-12-26 | 2010-07-07 | 北京京东方光电科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
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