CN102629588A - Method for manufacturing array substrate - Google Patents
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- CN102629588A CN102629588A CN201110415306XA CN201110415306A CN102629588A CN 102629588 A CN102629588 A CN 102629588A CN 201110415306X A CN201110415306X A CN 201110415306XA CN 201110415306 A CN201110415306 A CN 201110415306A CN 102629588 A CN102629588 A CN 102629588A
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Abstract
The invention, which relates to the liquid crystal display technology field, discloses a method for manufacturing an array substrate, so that a problem that there is great possibility to reduce cost in the existing manufacturing method for an array substrate can be solved. The manufacturing method comprises: forming a graph containing a gate electrode and a gate line; forming a graph containing a gate insulation layer, an active layer, a source electrode, a drain electrode, a passivation layer and a via hole on the passivation layer by utilizing a one-time composition process; and forming a graph containing a pixel electrode. During the whole manufacturing process for the array substrate, only three mask plates are used; therefore, compared with the existing 4-mask technology, the employed technology in the invention enables the manufacturing cost of the array substrate to be further reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, relate in particular to the manufacturing approach of array base palte.
Background technology
Array base palte is one of main composition of Thin Film Transistor-LCD (TFT LCD); In the process of manufacturing array substrate; Through reducing the quantity of employed lithography mask version (Mask), can significantly reduce the manufacturing cost of array base palte, and then can reduce the manufacturing cost of TFT LCD.
Fig. 1 shows the have bottom gate thin film transistor typical structure of array base palte of (TFT), and it is formed with on substrate 11 from bottom to up successively: gate electrode 12, gate insulator 13, active layer 14, source electrode 15, drain electrode 16, passivation layer 17 and pixel electrode 18.In addition, in passivation layer 16, also be formed with the pixel electrode via hole 19 that is used to be electrically connected pixel electrode 18 and drain electrode 16.Wherein, owing to have difference in height between gate electrode 12 surfaces and substrate 11 surfaces, therefore, gate electrode each layer more than 12 all has jump in the zone corresponding to gate electrode 12 edges, thereby formed step-like source electrode 15 and step-like drain electrode 16.
The method of the array base palte that existing manufacturing is shown in Figure 1 has been present 4Mask technology from initial 7Mask technical development, and 4 Mask are respectively applied for formation: the pixel electrode of the gate electrode of patterning, the active layer of patterning and source/drain electrode, pixel electrode via hole, patterning.
In the process of making above-mentioned array base palte, the inventor finds: though 4Mask compared with techniques and 7Mask technology are simplified in technological process greatly, utilization rate of equipment and installations and production capacity also significantly improve, and still there is the bigger space that reduces cost in it.
Summary of the invention
Embodiments of the invention provide a kind of manufacturing approach of array base palte, can further reduce the quantity of the mask of using, with the manufacturing cost of further reduction array base palte.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of manufacturing approach of array base palte comprises:
Formation comprises the figure of grid and grid line;
Form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology;
Formation comprises pattern of pixel electrodes.
Further; The active layer of said array base palte comprises intrinsic semiconductor layer and doping semiconductor layer; In the said plasma ashing technology of utilizing; Remove the photoresist of said first recess, etch away then after the source/leakage metal level of channel region, also comprise the doping semiconductor layer that etches away channel region.
Further, saidly form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole, specifically comprise through composition technology:
Form gate insulation layer, active layer and source/leakage metal level;
The coating photoresist; Make public, develop through the duotone mask; Removal is positioned at the photoresist of TFT regions with exterior domain; Form the photoresist pattern in TFT regions, said photoresist pattern comprises that first recess corresponding to channel region reaches second recess corresponding to lower region in the electrode of step-like source, and wherein the thickness of the photoresist of second recess reservation is greater than the thickness of the photoresist of first recess reservation;
Etch away the source/leakage metal level and the active layer in the zone that does not cover said photoresist pattern, expose said gate insulation layer;
Utilize plasma ashing technology, remove the photoresist of said first recess, etch away the source/leakage metal level of channel region then;
Utilize plasma ashing technology, get rid of the photoresist in zone the top, in step-like drain electrode lower region;
Form passivation layer, the thickness of the photoresist that the thickness of said passivation layer keeps less than the drain electrode zone is so that said passivation layer forms tomography above the photoresist of said reservation;
Remove said reservation photoresist and on said passivation layer, to form passivation layer via hole in the said passivation layer above said drain electrode.
Further, said formation comprises the figure of grid and grid line, specifically comprises:
Deposition grid metal level utilizes common mask board to explosure, development and etching on substrate, obtains comprising the figure of grid and grid line.
Further, said formation comprises pattern of pixel electrodes, specifically comprises:
Form the pixel electrode film on said passivation layer and in the said passivation layer via hole;
Utilize common mask that said pixel electrode film is carried out patterning, comprise pattern of pixel electrodes with formation.
Further, when the thickness of said grid was 250nm, the thickness of said passivation layer was 200nm.
Further, the material of said grid is one of in aluminium, copper, molybdenum, the chromium or combination in any.
Further, said passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, perhaps is the composite membrane that combination in any constituted in silicon nitride, silica, the silicon oxynitride.
Further, the formation technology of said grid metal level, said source/leakage metal level is sputtering technology.
Further, the formation technology of said gate insulation layer, said active layer and said passivation layer is chemical vapor deposition method.
In the manufacturing approach of the array base palte that the embodiment of the invention provides; Owing to form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology; Make and only used three mask in the manufacture process of whole array base palte, further lowered the manufacturing cost of array base palte than existing 4Ma sk technology.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is for having the generalized section of the array base palte of bottom gate thin film transistor in the prior art;
Fig. 2 A～2L is the generalized section of the array base palte manufacturing process that provides of the embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of manufacturing approach of array base palte, comprising: form the figure that comprises grid and grid line; Form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology; Formation comprises pattern of pixel electrodes.
Preferably, saidly form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole, specifically comprise through composition technology:
Form gate insulation layer, active layer and source/leakage metal level;
The coating photoresist; Make public, develop through the duotone mask; Removal is positioned at the photoresist of TFT regions with exterior domain; Form the photoresist pattern in TFT regions, said photoresist pattern comprises that first recess corresponding to channel region reaches second recess corresponding to lower region in the electrode of step-like source, and wherein the thickness of the photoresist of second recess reservation is greater than the thickness of the photoresist of first recess reservation;
Carry out dry etching, etch away the source/leakage metal level and the active layer in the zone that does not cover said photoresist pattern, expose said gate insulation layer;
Utilize plasma ashing technology, remove the photoresist of said first recess, etch away the source/leakage metal level of channel region then;
Utilize plasma ashing technology, get rid of the photoresist in zone the top, in step-like drain electrode lower region;
Form passivation layer, the thickness of the photoresist that the thickness of said passivation layer keeps less than the drain electrode zone is so that said passivation layer forms tomography above the photoresist of said reservation;
Remove said reservation photoresist and on said passivation layer, to form passivation layer via hole in the said passivation layer above said drain electrode.
In the manufacturing approach of the array base palte that the embodiment of the invention provides; Owing to form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology; Make and only used three mask in the manufacture process of whole array base palte, further lowered the manufacturing cost of array base palte than existing 4Ma sk technology.
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
In an embodiment of the present invention, composition technology comprises that exposure, development, etching etc. form the technology of figure; Source/drain electrode refers to source electrode and drain electrode; Source/leakage metal level, the metal of finger-type Cheng Yuan/drain electrode.A composition technology refers to use the composition technology of a mask plate (mask).
The embodiment of the invention provides a kind of manufacturing approach of array base palte, with reference to Fig. 2 A～Fig. 2 L this method is elaborated.
Step 1, formation comprise the figure of grid and grid line.
This step can adopt any can realization through the prior art that a composition technology realizes.Such as; Utilize common mask technology to realize; Shown in Fig. 2 A, by common mask (not shown) the gate metal layer (not shown) on the substrate 201 is carried out patterning, with the figure that comprises grid 202 and grid line (not shown) of the patterning that forms.Particularly, comprising: go up deposition grid metal level at substrate (substrate), utilize common mask board to explosure, development and etching, obtain comprising the figure of grid and grid line.
Common (routine) mask refers to employed mask with transparent area and non-transparent area usually; By this first conventional mask to after being formed on photoresist layer on the gate metal layer and carrying out exposure imaging; Be coated with photoresist on the gate metal layer that needs to keep, and the photoresist on the gate metal layer that need not keep is removed, through etch step; Unwanted gate metal layer is etched away, and remaining gate metal layer is the gate electrode 202 of required patterning.
The technology that forms gate metal layer can be sputtering technology, also can be other technology that those skilled in the art knew.
Step 2, form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through composition technology.
Said method can adopt masstone (Multi-tone) mask plate to realize, also can adopt duotone mask plate and binding plasma ashing, liftoff technology such as peel off to realize.Wherein, liftoff peeling off is meant the film material that peels off the photoresist top by peeling off of the photoresist below the rete simultaneously, realizes the technology of some specific pattern, and concrete implementation procedure can be referring to the description of following specific embodiment.
Following present embodiment will be introduced in detail, adopt duotone mask plate and binding plasma ashing, liftoffly the technical scheme that technology realizes forming through composition technology the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole such as peel off.
Particularly, comprise the steps:
Particularly, on the substrate 201 that comprises grid 202 and grid line, form gate insulator 203, active layer 204 and source/leakage metal level 205 from the bottom to top successively.Wherein, the technology that forms gate insulator 203 and active layer 204 can be chemical vapor deposition method, also can be other technology that those skilled in the art know; The technology of formation source/leakage metal level can be sputtering technology, also can be other technology that those skilled in the art knew.
Shown in Fig. 2 C and Fig. 2 D; This step specifically is included on the said substrate 201 of accomplishing said step 201 and forms a photoresist layer 206 again; (this sentences the gray-tone mask plate and is example to use gray level mask plate 207; Also can use other duotone mask plates, such as half-tone mask plate etc.) this photoresist layer 206 is made public.Because gray level mask plate 207 comprises corresponding to the first half exposure region A1 of the channel region that will form and corresponding to the second half exposure region A2 of lower region in the step-like source electrode that will form; After using 207 pairs of these photoresist layers 206 of this gray level mask plate to make public, develop, the first recess B1 that can on photoresist layer 206, form corresponding to said channel region reaches the second recess B2 corresponding to lower region in the electrode of said step-like source.
Also comprise the first light shielding part A3 on the gray level mask plate 207 corresponding to upper zone in the electrode of said step-like source; Reach the second light shielding part A4 corresponding to the step-like drain electrode that will form, the zone corresponding to substrate 201 other parts on the gray level mask plate 207 all is a transparent area.Therefore, after this photoresist layer 206 made public, develops, can form the photoresist pattern 206 shown in Fig. 2 D ', and this photoresist pattern 206 ' only cover zone of the thin-film transistor that will form.
By the said photoresist pattern 206 ' said substrate of accomplishing said step 202 is carried out etching; Shown in Fig. 2 D; Etch away the source/leakage metal level 205 and active layer 204 in the zone that does not cover the photoresist pattern; On the substrate that does not cover said photoresist pattern, exposing said gate insulator 203, and form the active layer 204 of source/the leakages metal level 205 of patterning ' reach patterning ', obtain the figure shown in Fig. 2 E.To source/when the leakage metal level carries out etching, can adopt wet etching, when active layer is carried out etching, can adopt dry etching.
The substrate of accomplishing above-mentioned technology is carried out plasma ashing handle, remove the photoresist of the first recess B1, form the photoresist figure 206 shown in Fig. 2 F ".It will be appreciated by those skilled in the art that; When plasma ashing is handled; Other regional photoresists also can be removed identical thickness; But because other regional photoresist thickness are all greater than the photoresist of the first recess B1, other zones still remain with photoresist when the photoresist of the first recess B1 is removed.
The photoresist figure 206 of utilization shown in Fig. 2 F ", etch away the source/leakage metal level of channel region, form the figure shown in Fig. 2 G, promptly form source electrode 208 and drain electrode 209.
When active layer is the semiconductor layer of intrinsic semiconductor and doped semiconductor formation, need further etch away the doping semiconductor layer of channel region.When active layer is organic semiconductor or metal oxide, then only need etching source/leakage metal level to get final product.
Substrate shown in Fig. 2 G is carried out the plasma ashing PROCESS FOR TREATMENT; Owing on the photoresist pattern, be provided with second recess; Make the photoresist shape of electrode 208 tops, step-like source and the shape of step-like source electrode 208 be complementary; When carrying out cineration step, photoresist in the electrode 208 of step-like source on the lower region and the photoresist on the upper zone can be removed at synchronization fully.Again owing to the photoresist above step-like drain electrode 209 has an even surface; Do not have the shape that is complementary with step-like drain electrode 209; Therefore in podzolic process; When the photoresist in the step-like drain electrode 209 on the upper zone is etched away fully, also some photoresists can residually be arranged on the lower region, thereby form residual 210 of photoresist (photoresist of reservation).That is, got rid of the photoresist in zone the top, in step-like drain electrode lower region, shown in Fig. 2 H.
Particularly, the formation technology of passivation layer can be chemical vapor deposition method, or other technology that those skilled in the art knew.Shown in Fig. 2 I, because the thickness of passivation layer 211 is less than the thickness of residual 210 of said photoresist, therefore, above residual 210 of said photoresist, passivation layer 211 forms tomographies, and passivation layer 211 that promptly should the place is discontinuous.
In actual manufacturing process, the thickness that photoresist is residual 210 under normal conditions can be identical with the thickness of grid, therefore, as long as the thickness of passivation layer 211 can form above-mentioned tomography equally less than the thickness of gate electrode.When the thickness of gate electrode was 250nm, the thickness of passivation layer 211 was preferably 200nm, can not only form above-mentioned tomography, can also embody excellent insulation property.
Particularly; Utilize stripper that the photoresist 210 (the residual portion of photoresist) that keeps is carried out lift-off processing; The passivation layer of the photoresist top that keeps also can be peeled off (being liftoff stripping technology here) along with the peeling off of photoresist that keeps together; Thereby form passivation layer via hole 212 in the said passivation layer 211 on said drain electrode 209, shown in Fig. 2 J.
Step 3, formation comprise pattern of pixel electrodes.
Wherein a kind of implementation method can for, specifically comprise: shown in Fig. 2 K, on said passivation layer 211 and in the said passivation layer via hole 212, form pixel electrode film 213 (such as indium tin oxide films etc.); Shown in Fig. 2 L, utilize common mask that said pixel electrode film is carried out patterning, with formation comprise pixel electrode 213 ' figure.
Particularly, the formation technology of pixel electrode film 213 can be sputtering technology, or other technology that those skilled in the art knew.
By this common mask to after being formed on photoresist layer on the indium tin oxide films and making public, develop; Be coated with photoresist on the pixel electrode film that needs to keep; And the photoresist on the pixel electrode film that need not keep is removed; Through etch step, unwanted indium tin oxide films is etched away, remaining pixel electrode film be the pixel electrode 213 of required patterning '.
Need to prove: the material of said grid metal level can be for one of in aluminium, copper, molybdenum, the chromium or combination in any; Said passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, perhaps is the composite membrane that combination in any constituted in silicon nitride, silica, the silicon oxynitride.
In the manufacturing approach of the array base palte that the embodiment of the invention provides; Owing to form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology; Make and only used three mask in the manufacture process of whole array base palte, further lowered the manufacturing cost of array base palte than existing 4Mask technology.
The embodiment of the invention is mainly used in the manufacturing of liquid crystal indicator.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (10)
1. the manufacturing approach of an array base palte is characterized in that, comprising:
Formation comprises the figure of grid and grid line;
Form the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through a composition technology;
Formation comprises pattern of pixel electrodes.
2. the manufacturing approach of array base palte according to claim 1 is characterized in that, saidly forms the figure that comprises gate insulation layer, active layer, source electrode, drain electrode, passivation layer and passivation layer via hole through composition technology, specifically comprises:
Form gate insulation layer, active layer and source/leakage metal level;
The coating photoresist; Make public, develop through the duotone mask; Removal is positioned at the photoresist of TFT regions with exterior domain; Form the photoresist pattern in TFT regions, said photoresist pattern comprises that first recess corresponding to channel region reaches second recess corresponding to lower region in the electrode of step-like source, and wherein the thickness of the photoresist of second recess reservation is greater than the thickness of the photoresist of first recess reservation;
Etch away the source/leakage metal level and the active layer in the zone that does not cover said photoresist pattern, expose said gate insulation layer;
Utilize plasma ashing technology, remove the photoresist of said first recess, etch away the source/leakage metal level of channel region then;
Utilize plasma ashing technology, get rid of the photoresist in zone the top, in step-like drain electrode lower region;
Form passivation layer, the thickness of the photoresist that the thickness of said passivation layer keeps less than the drain electrode zone is so that said passivation layer forms tomography above the photoresist of said reservation;
Remove said reservation photoresist and on said passivation layer, to form passivation layer via hole in the said passivation layer above said drain electrode.
3. the manufacturing approach of array base palte according to claim 2; It is characterized in that; The active layer of said array base palte comprises intrinsic semiconductor layer and doping semiconductor layer, in the said plasma ashing technology of utilizing, removes the photoresist of said first recess; Etch away then after the source/leakage metal level of channel region, also comprise the doping semiconductor layer that etches away channel region.
4. the manufacturing approach of array base palte according to claim 1 and 2 is characterized in that, said formation comprises the figure of grid and grid line, specifically comprises:
Deposition grid metal level utilizes common mask board to explosure, development and etching on substrate, obtains comprising the figure of grid and grid line.
5. the manufacturing approach of array base palte according to claim 1 and 2 is characterized in that, said formation comprises pattern of pixel electrodes, specifically comprises:
Form the pixel electrode film on said passivation layer and in the said passivation layer via hole;
Utilize common mask that said pixel electrode film is carried out patterning, comprise pattern of pixel electrodes with formation.
6. the manufacturing approach of array base palte according to claim 1 is characterized in that, when the thickness of said grid was 250nm, the thickness of said passivation layer was 200nm.
7. the manufacturing approach of array base palte according to claim 1 and 2 is characterized in that, the material of said grid is one of in aluminium, copper, molybdenum, the chromium or combination in any.
8. the manufacturing approach of array base palte according to claim 1 and 2 is characterized in that, said passivation layer is the monofilm of silicon nitride, silica or silicon oxynitride, perhaps is the composite membrane that combination in any constituted in silicon nitride, silica, the silicon oxynitride.
9. the manufacturing approach of array base palte according to claim 3 is characterized in that, the formation technology of said grid metal level, said source/leakage metal level is sputtering technology.
10. the manufacturing approach of array base palte according to claim 2 is characterized in that, the formation technology of said gate insulation layer, said active layer and said passivation layer is chemical vapor deposition method.
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| WO2015055030A1 (en) * | 2013-10-17 | 2015-04-23 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display device |
| CN105977210A (en) * | 2016-05-20 | 2016-09-28 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| CN106449666A (en) * | 2016-12-02 | 2017-02-22 | 京东方科技集团股份有限公司 | Array substrate and display device |
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| CN111192855A (en) * | 2018-11-14 | 2020-05-22 | 惠科股份有限公司 | Manufacturing method of array substrate, display panel and display device |
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| US10804298B2 (en) | 2016-12-02 | 2020-10-13 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN111192855A (en) * | 2018-11-14 | 2020-05-22 | 惠科股份有限公司 | Manufacturing method of array substrate, display panel and display device |
| WO2020098024A1 (en) * | 2018-11-14 | 2020-05-22 | 惠科股份有限公司 | Method for fabricating array substrate and display panel |
| CN109616510A (en) * | 2018-12-03 | 2019-04-12 | 惠科股份有限公司 | Thin film transistor structure, manufacturing method thereof and display device |
| US11227938B2 (en) | 2018-12-03 | 2022-01-18 | HKC Corporation Limited | Thin film transistor structure, manufacturing method thereof, and display device |
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