CN102937767B - The method for making of array base palte, display device and array base palte - Google Patents
The method for making of array base palte, display device and array base palte Download PDFInfo
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- CN102937767B CN102937767B CN201210421322.4A CN201210421322A CN102937767B CN 102937767 B CN102937767 B CN 102937767B CN 201210421322 A CN201210421322 A CN 201210421322A CN 102937767 B CN102937767 B CN 102937767B
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Abstract
The invention discloses the method for making of a kind of array base palte, display device and array base palte, relate to technical field of liquid crystal display, reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.This array base palte, comprises multiple pixel cell, and each described pixel cell comprises pixel electrode and public electrode, also comprises: be positioned at the metal wire of different layers with described public electrode; Described metal wire place layer and described public electrode are provided with insulation course between layers; Described insulation course is provided with multiple via hole in the region of described metal wire, and described metal wire is connected with described public electrode by described via hole.This display device comprises above-mentioned array base palte.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to the method for making of a kind of array base palte, display device and array base palte.
Background technology
In current liquid crystal display, multiple situation is provided with for public electrode in panel, wherein one is arranged in color membrane substrates by public electrode, also having a kind of is situation about public electrode and pixel electrode being all arranged on array base palte, such as senior super dimension field switch (Advanced-Super DimensionalSwitching is called for short ADS) technology.ADS technology is that the electric field that the electric field and gap electrode layer that are produced by gap electrode edge in same plane and plate electrode interlayer are produced forms multi-dimensional electric field, makes in liquid crystal cell that between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation.
But for situation about public electrode and pixel electrode being all arranged on array base palte, public electrode has larger resistance, and due to the area of public electrode comparatively large, make the homogeneity of public electrode voltages poor.
Summary of the invention
Embodiments of the invention provide the method for making of a kind of array base palte, display device and array base palte, reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.
For solving the problems of the technologies described above, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprise multiple pixel cell, each described pixel cell comprises pixel electrode and public electrode, also comprises:
The metal wire of different layers is positioned at described public electrode;
Described metal wire place layer and described public electrode are provided with insulation course between layers;
Described insulation course is provided with multiple via hole in the region of described metal wire, and described metal wire is connected with described public electrode by described via hole.
Further, described metal wire is between adjacent pixel cell.
Further, described via hole is arranged at the grid line region overlapping with described metal wire.
Further, described metal wire is arranged between two adjacent row pixel cells.
Further, the described metal wire of one row is set every two row pixel cells.
Further, often row pixel cell is divided into multiple pixel cell group, and each pixel cell group is made up of adjacent two pixel cells;
Often be provided with the first grid line above row pixel cell, often be provided with the second grid line below row pixel cell, described first grid line and the second grid line are used for driving two pixel cells in described each pixel cell group respectively, and two pixel cells in each pixel cell group are connected to same data line;
Be provided with virtual data line between adjacent pixel cell group, described metal wire is described virtual data line.
Further, described via hole is arranged at the region of the first grid line adjacent between adjacent rows pixel cell and the second grid line and described virtual data line overlap.
A kind of display device, comprises above-mentioned array base palte.
A manufacture method for array base palte, comprising:
Substrate is formed the pattern comprising grid line;
The substrate forming above-mentioned pattern forms the first insulation course;
The substrate forming above-mentioned pattern is formed the pattern comprising data line, metal wire and pixel electrode;
The substrate forming above-mentioned pattern forms the second insulation course, and by patterning processes, described second insulation course forms multiple via hole;
The substrate forming above-mentioned pattern is formed the pattern comprising public electrode, and described public electrode is connected with described metal wire by described via hole.
The method for making of the array base palte in the embodiment of the present invention, display device and array base palte, owing to being interconnected by multiple positions of multiple via hole by metal wire and public electrode, be equivalent to metal wire and public electrode parallel connection, because this reducing the resistance of public electrode, and improve the homogeneity of public electrode voltages.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of array base palte in the embodiment of the present invention;
Fig. 2 is the structural representation of another kind of array base palte in the embodiment of the present invention;
Fig. 3 be in Fig. 2 AA ' to sectional view;
Fig. 4 be in Fig. 2 BB ' to sectional view;
Fig. 5 is the manufacture method process flow diagram of a kind of array base palte in the embodiment of the present invention.
Description of reference numerals:
1-pixel electrode; 2-public electrode; 3-metal wire; 4-via hole; 5-data line; 6-grid line.7-second insulation course; 8-pixel cell group; 9-glass substrate; 10-first insulation course.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, the embodiment of the present invention provides a kind of array base palte, comprise longitudinal data line 5 and horizontal grid line 6, data line 5 and the multiple pixel cell of grid line 6 intersection definition, each pixel cell comprises pixel electrode 1 and public electrode 2, in Fig. 1, point-like fill area is public electrode 2, also public electrode 2 is had to be communicated with the public electrode in each pixel cell in data line 5 and the position of grid line 6, pixel electrode 1 in each pixel cell and public electrode 2 are tabular and slit-shaped respectively, this array base palte also comprises: be positioned at the metal wire 3 of different layers with public electrode 2, particularly, metal wire 3 can be line longitudinal as shown in Figure 1, also can be horizontal line, metal wire 3 place layer and public electrode 2 are provided with insulation course between layers, insulation course is provided with multiple via hole 4 in the region of metal wire 3, and metal wire 3 is connected with public electrode 2 by via hole 4, and multiple via hole 4 is positioned at viewing area.
It should be noted that, except the pixel electrode 1 shown in Fig. 1 in each pixel cell is tabular, public electrode 2 is situations of slit-shaped, and can also be slit-shaped for pixel electrode 1, public electrode 2 be situations of tabular.
Array base palte in the embodiment of the present invention, owing to being interconnected by multiple positions of multiple via hole by metal wire and public electrode, be equivalent to metal wire and public electrode parallel connection, not only reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.
Further, metal wire 3 can between adjacent pixel cell.Metal wire 3 can be blocked by the black matrix at data line and grid line place, can not transmitance be affected.
Further, as shown in Figure 2, via hole 4 can be arranged at the position in grid line 6 region overlapping with metal wire 3, is convenient to block via hole 4 by the black matrix at grid line 6 place.
Further, metal wire 3 is arranged between two adjacent row pixel cells.The number that metal wire 3 is concrete and distribution mode can be arranged according to the uniformity requirements of cost and public electrode voltages.
Further, one row metal wire 3 is set every two row pixel cells.
As shown in Figure 2, particularly, above-mentioned array base palte can be double grid (Dual Gate) array base palte, is namely driven the pixel of same a line by two grid lines 6, the quantity of data line 5 can be reduced by half like this, thus decrease the number of data IC joint.In double grid array base palte, often row pixel cell is divided into multiple pixel cell group 8, and each pixel cell group 8 is made up of adjacent two pixel cells; Often be provided with the first grid line above row pixel cell, often be provided with the second grid line below row pixel cell, first grid line and the second grid line are used for driving two pixel cells in each pixel cell group 8 respectively, and two pixel cells in each pixel cell group 8 are connected to same data line 5; Be provided with virtual data line (Dummy Data Line) between adjacent pixel cell group 8, virtual data line does not have actual effect in the process driven.Above-mentioned metal wire 3 can be virtual data line.Effectively can utilize like this and in driving process, originally there is no the virtual data line of practical function as metal wire 3 to reduce the resistance of public electrode and to improve the homogeneity of public electrode voltages.
Accordingly, in double grid array base palte, between two adjacent row pixel cells, be provided with two row grid lines 6; Via hole 4 is arranged at the first grid line adjacent between adjacent rows pixel cell and the region of the second grid line and virtual data line overlap.This is because virtual data line is thinner, too large-sized black matrix is not needed to block, and make the larger size of via hole needs, if make via hole 4 in other positions of virtual data line, the black matrix of large-size is then needed to block, thus reduce transmitance, and the size of two row grid lines 6 is enough large to cover via hole 4, therefore can not reduce transmitance.
It should be noted that, a line via hole 4 can be all set at every a line pixel cell, or a line via hole 4 is just set in every line.Above-mentioned via hole 4 does not need extra mask (Mask) manufacturing process, because the viewing area periphery of array base palte just needs to make via hole usually, only needs the figure increasing above-mentioned via hole 4 in original mask plate to realize.Array base palte in the embodiment of the present invention is applicable to variously all be arranged in the display device on array base palte by public electrode and pixel electrode, such as adopt the screen of ADS technology or adopt plane conversion (In-Plane Switching, be called for short IPS) screen of technology, for different application, the improvement opportunity of ADS technology has high permeability I-ADS technology, high aperture H-ADS and high resolving power S-ADS technology etc., and the array base palte that the embodiment of the present invention provides is the array base palte adopting HADS technology display device.
Array base palte in the embodiment of the present invention, owing to being interconnected by multiple positions of multiple via hole by metal wire and public electrode, be equivalent to metal wire and public electrode parallel connection, not only reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.
The embodiment of the present invention also provides a kind of display device, comprises above-mentioned array base palte.
Display device in the embodiment of the present invention, because array base palte is interconnected by multiple positions of multiple via hole by metal wire and public electrode, be equivalent to metal wire and public electrode parallel connection, not only reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.
Shown in Fig. 5, the embodiment of the present invention also provides a kind of manufacture method of array base palte, may be used for manufacturing the array base palte in the various embodiments described above, and this manufacture method comprises:
Step 101, with reference to shown in figure 2, Fig. 3 and Fig. 4, glass substrate 9 is formed and comprises the pattern of grid line 6;
Step 102, formed above-mentioned pattern substrate on form the first insulation course 10;
Step 103, the substrate forming above-mentioned pattern is formed comprise the pattern of data line, metal wire 3 and pixel electrode 1;
Step 104, on the substrate forming above-mentioned pattern, form the second insulation course 7, and by patterning processes, the second insulation course 7 forms multiple via hole 4;
Step 105, the substrate forming above-mentioned pattern is formed comprise the pattern of public electrode 2, public electrode 2 is connected with metal wire 3 by via hole 4.
Concrete array base-plate structure is same as the previously described embodiments, does not repeat them here.
The method for making of array base palte in the embodiment of the present invention, because array base palte is interconnected by multiple positions of multiple via hole by metal wire and public electrode, be equivalent to metal wire and public electrode parallel connection, not only reduce the resistance of public electrode, and improve the homogeneity of public electrode voltages.
In addition, for the array base palte such as adopting the pixel electrode of ADS technology above public electrode, also the manufacture method similar with the embodiment of the present invention can be adopted, difference is only first to make the pattern comprising public electrode, the substrate forming above-mentioned pattern forms insulation course, and by patterning processes, forms multiple via hole on which insulating layer, the substrate forming above-mentioned pattern is formed the pattern comprising metal wire, and metal wire is connected with public electrode by described via hole.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (8)
1. an array base palte, comprises multiple pixel cell, and each described pixel cell comprises pixel electrode and public electrode, it is characterized in that, also comprises:
The metal wire of different layers is positioned at described public electrode;
Described metal wire place layer and described public electrode are provided with insulation course between layers;
Described insulation course is provided with multiple via hole in the region of described metal wire, and described metal wire is connected with described public electrode by described via hole;
Often row pixel cell is divided into multiple pixel cell group, and each pixel cell group is made up of adjacent two pixel cells;
Often be provided with the first grid line above row pixel cell, often be provided with the second grid line below row pixel cell, described first grid line and the second grid line are used for driving two pixel cells in described each pixel cell group respectively, and two pixel cells in each pixel cell group are connected to same data line;
Be provided with virtual data line between adjacent pixel cell group, described metal wire is described virtual data line.
2. array base palte according to claim 1, is characterized in that,
Described metal wire is between adjacent pixel cell.
3. array base palte according to claim 1, is characterized in that,
Described via hole is arranged at the grid line region overlapping with described metal wire.
4. array base palte according to claim 2, is characterized in that,
Described metal wire is arranged between two adjacent row pixel cells.
5. array base palte according to claim 2, is characterized in that,
Every two row pixel cells, the described metal wire of one row is set.
6. array base palte according to claim 1, is characterized in that,
Described via hole is arranged at the region of the first grid line adjacent between adjacent rows pixel cell and the second grid line and described virtual data line overlap.
7. a display device, is characterized in that, comprise as arbitrary in claim 1-6 as described in array base palte.
8. a manufacture method for array base palte, is characterized in that, for the manufacture of the array base palte described in any one of claim 1 ~ 6, described manufacture method comprises:
Substrate is formed the pattern comprising grid line;
The substrate forming above-mentioned pattern forms the first insulation course;
The substrate forming above-mentioned pattern is formed the pattern comprising data line, metal wire and pixel electrode;
The substrate forming above-mentioned pattern forms the second insulation course, and by patterning processes, described second insulation course forms multiple via hole;
The substrate forming above-mentioned pattern is formed the pattern comprising public electrode, and described public electrode is connected with described metal wire by described via hole.
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| CN201210421322.4A CN102937767B (en) | 2012-10-29 | 2012-10-29 | The method for making of array base palte, display device and array base palte |
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| CN201210421322.4A CN102937767B (en) | 2012-10-29 | 2012-10-29 | The method for making of array base palte, display device and array base palte |
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| CN102937767B true CN102937767B (en) | 2015-08-05 |
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| CN104598089B (en) * | 2013-05-31 | 2017-12-08 | 京东方科技集团股份有限公司 | Array base palte, touch-screen and driving method and display device |
| US20150035741A1 (en) * | 2013-07-30 | 2015-02-05 | Samsung Display Co., Ltd. | Display apparatus |
| CN103474436B (en) | 2013-09-18 | 2016-03-09 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display unit |
| CN103839888B (en) * | 2014-02-27 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN104199220A (en) * | 2014-07-10 | 2014-12-10 | 合肥鑫晟光电科技有限公司 | Display panel and display device |
| CN104730781A (en) * | 2015-03-27 | 2015-06-24 | 京东方科技集团股份有限公司 | ADS array substrate, manufacturing method thereof, and display device comprising same |
| CN105204251B (en) * | 2015-08-28 | 2019-07-02 | 重庆京东方光电科技有限公司 | A kind of display base plate and preparation method thereof and display device |
| CN105607369B (en) | 2016-01-05 | 2019-03-26 | 京东方科技集团股份有限公司 | A kind of array substrate, liquid crystal display panel and display device |
| CN106773372B (en) * | 2016-12-30 | 2019-12-31 | 深圳市华星光电技术有限公司 | Common electrode structure, liquid crystal display panel and manufacturing method |
| CN106502012A (en) * | 2017-01-03 | 2017-03-15 | 深圳市华星光电技术有限公司 | Array base palte of FFS mode and preparation method thereof |
| CN106855670A (en) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
| CN109541861A (en) * | 2017-09-22 | 2019-03-29 | 京东方科技集团股份有限公司 | Dot structure, array substrate and display device |
| CN108983484A (en) * | 2018-08-06 | 2018-12-11 | 深圳市华星光电技术有限公司 | A kind of colored filter and preparation method, display device |
| CN113934032B (en) * | 2020-06-29 | 2023-01-17 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN111948848A (en) * | 2020-08-06 | 2020-11-17 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN114911102B (en) * | 2022-04-08 | 2024-08-16 | 上海天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
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