WO2013149467A1

WO2013149467A1 - Array substrate, and manufacturing method thereof and display device

Info

Publication number: WO2013149467A1
Application number: PCT/CN2012/084162
Authority: WO
Inventors: 姜文博; 董学; 陈东; 李成; 徐宇博; 陈小川; 薛海林; 陈希; 张弥; 李小和
Original assignee: 北京京东方光电科技有限公司
Priority date: 2012-04-06
Filing date: 2012-11-06
Publication date: 2013-10-10
Also published as: CN102651371A

Abstract

Provided are an array substrate, and a manufacturing method thereof and a display device. The array substrate comprises multiple gate lines (1) formed on the substrate, multiple data lines (2), and multiple thin film transistor pixel structures (3) formed between the gate lines (1) and the data lines (2), each thin film transistor pixel structure (3) comprising a thin film transistor and a display area, and the display area being provided with a common electrode; the array substrate further comprises at least one common electrode line (4) connected with the common electrode. The array substrate can prevent the crosstalk interference phenomenon generated in display frames.

Description

Array substrate, manufacturing method thereof and display device

Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique

The ADVanced Super Dimension Switch (ADS) is a planar electric field wide viewing angle technology, which is characterized by: an electric field generated by the edge of the slit electrode in the same plane, and a slit electrode layer and a plate electrode layer. The electric field generated between the two forms a multi-dimensional electric field, so that all liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency. Advanced Super Dimensional Field Conversion Technology (ADS) improves the picture quality of TFT-LCDs with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeeze water ripple (push Mura) )Etc.

Retina display - advanced super-dimensional field conversion technology (Retina display-ADvanced Super

Dimension Switch (referred to as R-ADS) is a new technology that applies ADS technology to Retina Display. It features: Apply ADS technology to retina display to make ADS display devices (such as array substrates or LCD panels). ) With ultra-high pixel density, the pixel density is above 300PPI. In addition to the above advantages of ADS, the display screen using R-ADS technology can make it impossible for the human eye to distinguish individual pixels, so that the image is no longer grainy and the display is more realistic, which allows the viewer to have the feeling of viewing the paper products. Therefore, this display has broad application prospects.

With the application of ADS technology, especially R-ADS technology, the requirements for display effects are getting higher and higher. However, defects in production, especially flicker, crosstalk, and shadow, are important factors influencing product quality. Many products encounter these defects in the production process, but there is no effective means to control these defects, which has become a major problem in process design.

The fluctuation of the storage capacitor of ADS products has always been one of the important reasons for the flicker. Because the pixel electrodes of some existing ADS products are blocks in which each pixel is independent of each other, the common electrode is formed into a strip shape, and the overlapping area of the two electrodes fluctuates due to the layout process deviation between the different layers. (a) and (b) in Fig. 1 show layout process variations between layers, and block pixels in (b) The electrode 200 is shifted to the left with respect to the common electrode 100 having the strip hole 100' therein, thereby causing fluctuations in the storage capacitance to cause flicker. The design shown in FIG. 1(c) uses the pixel electrode on the upper side, the common electrode on the lower side, and the pixel electrode as a strip, and the common electrode is integrated into one body, so that the offset of the pixel electrode does not cause fluctuation of the storage capacitor. Thereby effectively reducing the occurrence of flicker. As shown in FIG. 1(c), the pixel electrode 200 has a strip shape, 200' is a strip-shaped hole, and the common electrode 100 has a block shape.

The common electrode of the above ADS product is formed as a whole, but due to the influence of large resistance, the coupling effect of the source/drain (SD) signal line on the common electrode cannot be eliminated in time, resulting in a voltage change of the common electrode and a driving voltage in the pixel. Differences will cause differences, causing crosstalk on the display and affecting the display. The R-ADS technology using the above technical solution also has the problem of crosstalk. Summary of the invention

An embodiment of the present invention provides an array substrate including a plurality of gate lines formed on a substrate, a plurality of data lines, and a plurality of thin film transistor pixel structures formed between the gate lines and the data lines, The thin film transistor pixel structure includes a thin film transistor and a display region, and a common electrode is disposed in the display region, wherein the array substrate further includes at least one common electrode line connected to the common electrode.

Another embodiment of the present invention further provides a method of fabricating an array substrate, including the following steps:

S1: forming at least one common electrode line pattern on the substrate while forming a gate line pattern and a gate pattern of the thin film transistor on the substrate;

S2: after forming the gate line pattern, the gate pattern, and the common electrode line pattern, forming a common electrode pattern including a thin film transistor and over the thin film transistor, a pixel electrode pattern, and connecting the common electrode a line pattern and a first via of the common electrode pattern.

Still another embodiment of the present invention also provides a display device comprising the array substrate as described above.

In the array substrate according to the embodiment of the present invention, a common electrode line connected to the common electrode is disposed in the pixel transistor pixel structure, thereby greatly reducing the resistance of the common electrode, thereby eliminating source-drain (SD) signal line pairs in time. The coupling effect of the common electrode does not cause a voltage change of the common electrode, and the voltage difference of the driving in the pixel does not cause a difference, thereby avoiding the display screen Crosstalk occurs in the middle. DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 is a schematic view showing the arrangement of a pixel electrode and a common electrode in an array substrate in the prior art; FIG. 2 is a plan view showing the structure of the array substrate according to the first embodiment of the present invention;

3 is a schematic cross-sectional view of the array substrate structure shown in FIG. 2 taken along line A'-A; FIG. 4 is a schematic view showing the structure of the array substrate according to the second embodiment of the present invention;

Fig. 5 is a schematic view showing the principle of increasing the aperture ratio of the array substrate according to the second embodiment; Fig. 6 is a view showing another principle of increasing the aperture ratio of the array substrate according to the second embodiment. detailed description

The technical solutions of the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present invention. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of ordinary meaning as understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the specification and claims of the invention are not intended to indicate any order, quantity or importance, but are merely used to distinguish different components. Similarly, the words "a" or "an" do not denote a quantity limitation, but rather mean that there is at least one. The words "including" or "comprising", etc., are intended to mean that the elements or objects preceding "including" or "comprising" are intended to encompass the elements or Component or object. "Connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "Bottom", "Left", "Right", etc. are only used to indicate the relative positional relationship. When the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly. The array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and The pixel electrode and the common electrode that control the arrangement of the liquid crystals. For example, the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line, the source is electrically connected or integrally formed with the corresponding data line, and the drain is electrically connected or integrally formed with the corresponding pixel electrode. The following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.

First embodiment

As shown in FIG. 2, the ADS type array substrate according to the present embodiment may include a gate line 1, a data line 2, and a plurality of thin film transistor pixel structures 3 between the gate line 1 and the data line 2 (each thin film transistor pixel structure) Corresponds to one pixel unit). Each of the thin film transistor pixel structures 3 may include a thin film transistor and a display region. The thin film transistor may include a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode (not shown in Fig. 2). The display area refers to a region for display other than the thin film transistor (corresponding to a region where the pixel electrode is located), and includes a pixel electrode 39 and a common electrode (not shown in Fig. 2) located under the pixel electrode 39. The common electrode may be a unitary block-shaped common electrode on the entire array substrate. The array substrate may further include at least one common electrode line 4 connected to the common electrode of the thin film transistor pixel structure 3. The common electrode line 4 can penetrate a plurality of pixel units. The common electrode line 4 may be located at any position in the pixel structure of the thin film transistor. Specifically, the common electrode line 4 may be located in a display area of a row or column of pixel units (ie, a thin film transistor pixel structure) (refer to a display area of the pixel unit, but Not at the intersection of two or two adjacent pixel units), or at the intersection of two rows (or two columns) of adjacent pixel units (this can further include the following three cases: (1) only located a display area of one of the two rows of pixel units at the junction; (2) a display area of two rows of pixel units at the same time; (3) at the junction, but not falling into any one of the adjacent two rows of pixel units The display area) can also be located at other suitable locations without being limited to the position shown in FIG. 2. For purposes of illustration, the common electrode line 4 can be shown in Figure 2 as being located at the junction of two adjacent thin film transistor pixel structures 3.

3 is a schematic cross-sectional view of the array substrate structure taken along line A'-A of FIG. 2 according to the present embodiment. The array substrate structure may include, in order from bottom to top, a gate 31, a gate insulating layer 32, an active layer 33, source and drain electrodes 34 (including source and drain electrodes), a first passivation layer 35, a barrier layer 36, and a common The electrode 37, the second passivation layer 38, and the pixel electrode 39. In this embodiment, the common electrode line 4 can be It is located in the same layer as the gate 31 of the thin film transistor TFT (that is, in the same layer as the gate line 1), and is parallel to the gate line 1. The pixel electrode 39 may be a strip electrode and may be connected to a drain electrode in the source/drain electrode 34 through a through hole penetrating through the second passivation layer 38, the barrier layer 36, and the first passivation layer 35. The strip-shaped pixel electrode 39 may have a strip-shaped hole 39'. The via may include a via hole 5 through the second passivation layer 38 and a via 6 (also referred to as a second via) through the barrier layer 36 and the first passivation layer 35. The common electrode 37 may be a monolithic electrode covering the substrate. In order to avoid contact with the pixel electrode 39, the common electrode 37 may be formed with an isolation hole 7 having a diameter larger than the sleeve hole 5 around the sleeve hole 5, that is, at a position of the through hole connecting the pixel electrode and the drain electrode, the common electrode is in the through hole An isolation hole having a diameter larger than a through hole (specifically, a hole portion of the through hole) is formed around the hole. The common electrode line 4 may be connected to the common electrode 37 through a via 8 (which may also be referred to as a first via) passing through the barrier layer 36, the first passivation layer 35, and the gate insulating layer 32. In order to connect the common electrode line 4 and the common electrode 37 in parallel to reduce the resistance of the common electrode 37, the common electrode line 4 may be connected to the common electrode 37 through at least two via holes 8 to achieve the effect of the parallel connection (the common electrode line 4) Unlike the existing common electrode lines that provide signals to the common electrodes).

In this embodiment, the structure of the array substrate is merely for the sake of example, and the array substrate structure of the embodiment of the present invention is not limited. For example, in practical applications, the barrier layer 36 may not be included, or the common electrode 37 may be located between the barrier layer 36 and the first passivation layer 35 (in this case, the barrier layer 36 and the second passivation layer 38 may be a unitary structure). For example, the common electrode 37 may not be integrated into a bulk common electrode, but may be independently formed into blocks in each pixel unit; for example, the common electrode may also be located above the pixel electrode; for example, the common electrode The lines may also be disposed and fabricated in the same layer as the gate lines, but may be fabricated from other layers (eg, data line metal layers) or newly added metal layers. Therefore, the actual structure of the array substrate can be changed according to actual needs. Of course, in the present embodiment, the barrier layer 36 is exemplarily disposed and the common electrode 37 is positioned above the barrier layer 36, so that the array substrate can have a higher aperture ratio. When the structure of the array substrate is changed, the layer (for example, the barrier layer, etc.) through which the via hole 6, the via 8 and the like are passed in the embodiment of the present invention can be adjusted accordingly (ie, more or less can be passed according to actual needs). Layer).

A method of fabricating the above array substrate will be described below. It is only necessary to make at least one common electrode line 4 connected to the common electrode 37 when fabricating the above array substrate. In order to make the manufacturing process simple, the common electrode line 4 can be formed on the same layer of the gate line.

A method of fabricating an ADS type array substrate provided by the present embodiment will be specifically described below. The array substrate fabricated according to the method may have at least one common electrode line connected to the common electrode. For the convenience of description, the following is an example of manufacturing an ADS type array substrate having the structure shown in FIG. 3, and the manufacturing method specifically includes the following steps:

51. The common electrode line 4 is also formed on the glass substrate by patterning the gate 31 and the gate line 1 by a series of patterning processes such as exposure, development, etching, and peeling. The common electrode line 4 can be parallel to the gate line 1. The common electrode line 4 may be located in a display area of one row of pixel units or at a boundary of two adjacent pixel units. In order to influence the aperture ratio less, the common electrode line 4 may be disposed at the boundary of two adjacent pixel units.

52. After forming the pattern of the gate electrode 31, the gate line 1 and the common electrode line 4, the TFT is formed by a patterning process (the gate insulating layer 32 except the gate electrode 31, the active layer 33, the source/drain electrode 34, the first blunt a layer 35) and a barrier layer 36 on the TFT, and etched down through the barrier layer 36 in a region of the barrier layer 36 corresponding to the drain electrode in the source and drain electrode 34 and the pattern of the common electrode line 4, The via 6 of the first passivation layer 35 and the via 8 passing through the barrier layer 36, the first passivation layer 35, and the gate insulating layer 32. Preferably, at least two vias 8 can be etched.

S3. Depositing a first conductive film and forming an isolation hole 7 by a patterning process at a region where the first conductive film corresponds to the drain electrode connection of the pixel electrode 39 and the source/drain electrode 34 to form a pattern of the common electrode 37.

54. depositing an insulating film on the substrate on which the pattern of the common electrode 37 is formed to form a second passivation layer 38, and corresponding to the drain electrode in the pixel electrode 39 and the source/drain electrode 34 on the second passivation layer 38 A through hole 5 is formed through the second passivation layer 38 by a patterning process at the region. The diameter of the sleeve hole 5 may be greater than or equal to the diameter of the via hole 6 and smaller than the diameter of the isolation hole 7.

55. Depositing a second conductive film, and patterning the second conductive film to form a stripe pixel electrode 39, and the pixel electrode 39 is connected to the drain electrode in the source/drain electrode 34 through the via hole 5 and the via hole 6.

In this embodiment, the common electrode line 4 is added to the array substrate, and is connected to the common electrode 37 through at least two via holes 8, so that the upper and lower two resistors, that is, the common electrode 37 and the common electrode line 4 are connected in parallel, thereby greatly The electric resistance of the common electrode 37 is reduced, and occurrence of a defect such as crosstalk due to an increase in the resistance of the common electrode 37 is prevented.

The above is only a manufacturing method of the embodiment of the present invention. When the specific structure of the array substrate changes, the manufacturing method can be adjusted according to actual conditions. For example, in practical applications, The barrier layer 36 is not formed, or the common electrode 37 may be located between the barrier layer 36 and the first passivation layer 35 (in this case, the barrier layer 36 and the second passivation layer 38 may be a unitary structure); for example, a common electrode 37 may also be a block-shaped common electrode that is not integrated into a whole, but is independently formed into blocks in each pixel unit; for example, the common electrode may also be located above the pixel electrode; for example, the common electrode line may not be connected to the gate line. The same layer is set and fabricated, but is made by other layers (such as the data line metal layer) or the newly added metal layer. There are no restrictions here.

In order to further reduce the resistance of the common electrode 37, a plurality of via holes 8 for connecting the common electrode line 4 and the common electrode 37 may be disposed on the array substrate. For example, each of the common electrode lines 4 may be connected to the common electrode 37 through N via holes 8 on the array substrate, where 2≤N≤A, and A is the total number of columns of the multi-column thin film transistor pixel structure divided by the data lines. . As shown in Fig. 2, the common electrode line 4 passing through 3 pixels per line is connected to the common electrode 37 through the two via holes 8. Preferably, the N via holes 8 may be periodically arranged with the same number of pixel columns (or the same number of pixel rows, when the common electrode lines are vertically disposed on the array substrate and parallel to the data lines), and the common electrode may be made at this time. 37 The resistance of each pixel unit tends to be uniform, and the uniformity of the display picture is ensured to some extent.

Further, a plurality of common electrode lines 4 connected to the common electrode 37 may be disposed on the array substrate, and each of the common electrode lines 4 corresponds to a row of thin film transistor pixel structures. Since the common electrode line 4 affects the pixel aperture ratio of the entire substrate (the aperture ratio of the pixel provided with the common electrode line 4 and the pixel not provided with the common electrode line 4 is different), in order to ensure the aperture ratio of the entire array substrate Uniformity, in the multi-line thin film transistor pixel structure 3 divided by the gate line 1, the common electrode line 4 may be arranged periodically with M-line thin film transistor pixel structures, wherein M represents multiple lines divided by the gate lines 1. The number of rows of the thin film transistor pixel structure 3, M is greater than 0 and less than the total number of rows. Optionally, each of the thin film transistor pixel structures in the multi-row thin film transistor pixel structure 3 divided by the gate line 1 may be provided with a common electrode line 4 (the common electrode line 4 may be located in the display area of the row of pixel units, also It may be located at the intersection of the row of pixel cells and the adjacent row of pixel cells, such that the uniformity of the pixel aperture ratio of the entire substrate is better, and the resistance of the common electrode 37 is lower.

The ADS type array substrate according to the present embodiment can be applied to an R-ADS type array substrate, thereby realizing retinal display, resulting in a better user experience.

Second embodiment

Since a plurality of common electrode lines 4 are added to the array substrate structure according to the first embodiment, if the conventional ADS method is used, the common electrode line 4 needs to be spaced apart from the gate line 1 by a certain distance. The illuminating area that causes it to block normal has a great influence on the aperture ratio. In order to increase the aperture ratio, the array substrate of the present embodiment is disposed in a manner opposite to the TFT. As shown in FIG. 4 (the cross-sectional view of each of the thin film transistor pixel structures is similar to FIG. 3), adjacent two rows of thin film transistor pixel structures 3 of the plurality of thin film transistor pixel structures 3 divided by the gate lines 1 (ie, adjacent two The thin film transistor regions of the row pixel units are adjacently arranged, and the respective display regions of the adjacent two rows of thin film transistor pixel structures 3 are respectively arranged adjacent to the display regions of the adjacent thin film transistor pixel structures 3. The array substrate may include at least one common electrode line, and the common electrode line 4 may be located at the intersection of the adjacent adjacent display regions, that is, at the boundary of two adjacent thin film transistor pixel structures, the two adjacent films. The display areas of the transistor pixel structure are disposed adjacent to each other. Moreover, as shown in FIG. 4, the common electrode line of the embodiment of the present invention is simultaneously located at the display area of the two rows of pixel units at the boundary. In order to connect the common electrode line 4 and the common electrode 37 in parallel to reduce the resistance of the common electrode 37, the common electrode line 4 is connected to the common electrode 37 through at least two via holes 8 to achieve the effect of parallel connection (the common electrode line 4 is different) In the existing common electrode line that provides a signal for the common electrode).

In order to further reduce the resistance of the common electrode 37, a plurality of via holes 8 for connecting the common electrode line 4 and the common electrode 37 may be disposed on the array substrate. For example, each common electrode line 4 can be connected to the common electrode 37 through N via holes 8 on the array substrate, where 2≤N≤A, A is the total number of columns of the multi-column thin film transistor pixel structure divided by the data lines. . As shown in Fig. 4, the common electrode line 4 passing through 3 pixels per line can be connected to the common electrode 37 through the two via holes 8. Preferably, the N via holes 8 can be periodically arranged at intervals of the same number of pixel columns, so that the resistance of the common electrode 37 in each pixel unit tends to be uniform, and the uniformity of the display screen is ensured to some extent.

Meanwhile, a plurality of common electrode lines 4 connected to the common electrode 37 may be disposed on the array substrate, since the common electrode line 4 affects the pixel aperture ratio of the entire substrate (pixels provided with the common electrode line 4 and not provided with a common The aperture ratio of the pixels of the electrode line 4 is different). In order to ensure the uniformity of the aperture ratio of the entire array substrate, in the multi-line thin film transistor pixel structure 3 divided by the gate line 1, the common electrode lines 4 may be periodically arranged with M rows of pixel units, wherein M represents a gate. The number of rows of the multi-line thin film transistor pixel structure 3 divided by line 1, M is greater than 0 and less than the total number of rows. Preferably, in the multi-line thin film transistor pixel structure 3 divided by the gate line 1, a common electrode line 4 may be disposed at the boundary of each of the adjacent adjacent display regions, such that the pixel aperture ratio of the entire substrate is The uniformity is good, and the electric resistance of the common electrode 37 is smaller. Optionally, the two display areas of the two rows of thin film transistor pixel structures 3 adjacent to each other in the display area may have only one public The common electrode line 4, that is, the two rows of thin film transistor pixel structures 3 arranged adjacent to each other in the display area can share a common electrode line 4, so that the aperture ratio of the pixels is less affected.

The two regions "adjacently arranged" in the embodiments of the present invention mean that the other regions are not spaced apart from each other except for the gate lines or except for the gate lines and the common electrode lines. For example, the thin film transistor regions of two adjacent rows of pixel cells are adjacently arranged, meaning that only the gate lines are spaced apart in the middle of the thin film transistor regions of the adjacent two rows of pixel cells, or only the gate lines and the common electrode lines are spaced apart, and other components such as pixel electrodes are not spaced. The display areas of the adjacent thin film transistor pixel structures are adjacent to each other, which means that the display areas of the adjacent thin film transistor pixel structures are only spaced apart from the gate lines, or only the gate lines and the common electrode lines are spaced apart, and the thin film transistors are not spaced. And other components.

The thin film transistor pixel structure 3 in this embodiment is similar to the thin film transistor pixel structure 3 in the first embodiment, and the description thereof will not be repeated here.

The method for fabricating the array substrate of the present embodiment is substantially the same as the method for fabricating the array substrate of the first embodiment. The difference is: forming a gate electrode 31 on a glass substrate by a series of patterning processes such as exposure, development, etching, and stripping. When the pattern of the gate line 1 and the pattern of the common electrode line 4 are such that the gate regions of the thin film transistors of the adjacent two rows of thin film transistor pixel structures in the multi-line thin film transistor pixel structure (ie, pixel unit) divided by the gate line 1 are adjacent Arranging, the display regions of the two rows of thin film transistor pixel structures arranged adjacent to the gate region are respectively adjacent to the upper and lower adjacent rows (that is, a row above the pixel structure of the two rows of thin film transistors arranged adjacent to the gate region) The display areas of the thin film transistor pixel structures in the next row) are adjacently arranged. A common electrode line 4 can be formed between two rows of thin film transistor pixel structures arranged adjacent to each other in the display area. The steps of fabricating the gate 31, the pattern of the gate line 1 and the respective layers above the common electrode line 4 may be similar to those of the first embodiment, and the description thereof will not be repeated here.

As shown in Fig. 5(a), the aperture ratio of a pixel is affected by several factors: the width of the common electrode line 4 indicated by a; the black matrix indicated by b for preventing light leakage above the gate line (Black Matrix) The width of BM ); the width of the gate line indicated by c; and the width of BM indicated by d for preventing light leakage under the gate line. As shown in Fig. 5(b), since two pixels are arranged in opposite ways by TFTs, two pixels only need a width of d to prevent light leakage under the gate lines, so each pixel can save d/2 BM. The width is increased by about 3% with respect to the pixel aperture ratio of the array substrate of the first embodiment. In addition, the width 2a of the common electrode line 4 can also be further reduced. At the same time, the present invention takes the opposite part of the TFT between the upper and lower pixels, effectively utilizes the excess space, and the spacer is disposed at this position, without adding an extra BM area to prevent the spacer from being offset. The formation is poor, thereby increasing the aperture ratio. Moreover, current ADS products have a narrow width of a single pixel BM due to the limitation of the aperture ratio, so that after the spacer is placed, it is easy to form an orientation dead zone in the non-BM region due to possible positional displacement of the spacer. This is the root cause of the contrast reduction and various afterimages, which seriously affects the yield. In the way of taking the TFT opposite, the BM of the two pixels is combined in one place, and the spacer has a large space, so that the σ mouth σ is ensured without lowering the aperture ratio.

Further, in a pixel structure in which a barrier layer (generally a resin material) has via holes, since the via holes are deep, a large amount of liquid crystal is accommodated in the via holes. These liquid crystals differ greatly in liquid crystal thickness from the normal display area. As shown in Fig. 6, the distance h2 from the via hole to the top of the liquid crystal layer 9 may be larger than the thickness hi of the liquid crystal cell, which causes a difference in liquid crystal alignment, resulting in severe light leakage. Moreover, the via is covered with an electrode, and the electrode here is not parallel to the substrate, but is disposed on the sidewall of the via to form a large angle of inclination α with the substrate, which affects the orientation of the surrounding liquid crystal. In addition, the via area has a strong interference with the electric field in the normal display area, which seriously affects the normal display. If additional ΒΜ is used, the opening ratio is lowered, and the quality is still hidden. If the TFT opposite design is used, the via areas of the upper and lower pixels can be placed together and spaced apart from the normal display area by the width of the gate lines and the width of the turns, thereby avoiding the normal display of the via areas. The impact of the area can increase the aperture ratio and reduce the risk of bad.

The ADS type array substrate according to the present embodiment can be applied to an R-ADS type array substrate, thereby realizing retinal display to bring about a better user experience.

Third embodiment

The embodiment provides a display device including the array substrate according to the first or second embodiment, and the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, LCD monitors, digital photo frames, mobile phones, tablets, etc. (1) An array substrate comprising a plurality of gate lines formed on a substrate, a plurality of data lines, and a plurality of thin film transistor pixel structures formed between the gate lines and the data lines, the thin film transistor The pixel structure includes a thin film transistor and a display region, and a common electrode is disposed in the display region, wherein the array substrate further includes at least one common electrode line connected to the common electrode. The array substrate according to (1), wherein the at least one common electrode line is located in a display region of the thin film transistor pixel structure, or the thin film transistor is adjacent to two rows The junction of the pixel structure.

(3) The array substrate according to (1), wherein each of the thin film transistor pixel structures of each row is correspondingly provided with one of the common electrode lines.

The array substrate according to any one of (1), wherein the at least one common electrode line is connected to the common electrode through N via holes on the array substrate, wherein

2 < N < A, A is the total number of columns of the plurality of thin film transistor pixel structures divided by the data lines.

(5) The array substrate according to (4), wherein the number of pixel rows having the same interval of the N via holes or the number of pixel rows having the same interval are periodically arranged.

The array substrate according to any one of (1) to (5), wherein a thin film transistor region of a pixel structure of two adjacent thin film transistors in a multi-line thin film transistor pixel structure divided by the gate line In the adjacent arrangement, the display areas of the adjacent two rows of thin film transistor pixel structures are respectively arranged adjacent to the display areas of the thin film transistor pixel structures of adjacent rows.

(7) The array substrate according to (6), wherein each of the thin film transistor pixel structures in the multi-line thin film transistor pixel structure is provided with one of the common electrode lines.

(8) The array substrate according to (6), wherein the two rows of thin film transistor pixel structures arranged adjacent to each other are provided with only one of the common electrode lines, and the common electrode lines are adjacent to the display area. The junction of the two-line thin film transistor pixel structure.

The array substrate according to any one of (1), wherein the pixel electrode in the pixel transistor pixel structure is a strip electrode, the common electrode is a block electrode, and the pixel A passivation layer is disposed between the electrode and the common electrode.

The array substrate according to any one of (1), wherein the common electrode is a bulk electrode covering the entire array substrate.

The array substrate according to any one of (1), wherein the pixel electrode is connected to a drain electrode of the thin film transistor through a via hole, and the common electrode is in the via hole An isolation hole having a diameter larger than the through hole is formed around.

The array substrate according to any one of (1), wherein the common electrode line is in the same layer as the gate line and is parallel to the gate line.

The array substrate according to any one of (1) to (12) wherein the array substrate is an array substrate using retinal display technology.

(14) A method for fabricating an array substrate, comprising the steps of: SI: forming at least one common electrode line pattern on the substrate while forming a gate line pattern and a gate pattern of the thin film transistor on the substrate;

S2: after forming the gate line pattern, the gate pattern, and the common electrode line pattern, forming a thin film transistor, a common electrode pattern over the thin film transistor, a pixel electrode pattern, and a connection for the common An electrode line pattern and a first via of the common electrode pattern.

The manufacturing method according to (14), wherein the step S2 comprises: forming a thin film transistor on the substrate after the step S1 is completed;

Forming a barrier layer on the substrate after forming the thin film transistor, and respectively connecting a region corresponding to the common electrode line pattern on the barrier layer and a connection region of a drain electrode and the pixel electrode of the thin film transistor Forming the first via hole and the second via hole for connecting the drain electrode and the pixel electrode;

Depositing a first conductive film and forming an isolation hole on the first conductive film around the second via hole by a patterning process to form a common electrode pattern;

Forming an insulating film on the substrate on which the common electrode pattern is formed to form a passivation layer, and forming a pass through the passivation layer by a patterning process on a region of the passivation layer corresponding to the second via hole a hole having a diameter smaller than a diameter of the isolation hole, the sleeve hole and the second via forming a through hole connecting the pixel electrode and the drain electrode;

A second conductive film is deposited and the second conductive film is patterned to form a strip-shaped pixel electrode, and the pixel electrode is connected to the drain electrode through the via.

The manufacturing method according to (14) or (15), wherein the at least one common electrode line pattern is located in a display area of the thin film transistor pixel structure, or at a boundary of two adjacent thin film transistor pixel structures .

(17) The manufacturing method according to (14) or (15), wherein each of the thin film transistor pixel structures is correspondingly provided with one of the common electrode line patterns.

(18) The manufacturing method according to (14) or (15), wherein in the step S1, when forming the gate line pattern and the gate pattern of the thin film transistor, the pixel structure of the plurality of lines of thin film transistors divided by the gate lines is formed The gate regions of the adjacent two rows of thin film transistor pixel structures are adjacently arranged, and the respective display regions of the two rows of thin film transistor pixel structures adjacent to the gate region are respectively connected to the thin film transistor pixel structures in the upper and lower adjacent rows The display areas are arranged adjacent to each other.

The manufacturing method according to any one of (18), wherein the public electricity is formed In the case of a polar line pattern, two rows of thin film transistor pixel structures arranged adjacent to the display area form only one common electrode line, and the common electrode line forms two rows of thin film transistor pixel structures arranged adjacent to the display area Junction.

(20) A display device comprising the array substrate according to any one of (1) to (13).

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

An array substrate comprising a plurality of gate lines formed on a substrate, a plurality of data lines, and a plurality of thin film transistor pixel structures formed between the gate lines and the data lines, the thin film transistor pixel structure A thin film transistor and a display region are disposed, and a common electrode is disposed in the display region, wherein the array substrate further includes at least one common electrode line connected to the common electrode.

The array substrate according to claim 1, wherein said at least one common electrode line is located in a display region of said thin film transistor pixel structure or at a boundary of said thin film transistor pixel structures adjacent to two rows.

The array substrate according to claim 1, wherein each of said thin film transistor pixel structures is provided with one of said common electrode lines.

The array substrate according to any one of claims 1 to 3, wherein the at least one common electrode line is connected to the common electrode through N via holes on the array substrate, wherein 2 ≤ N

<A, A is the total number of columns of the plurality of thin film transistor pixel structures divided by the data lines.

The array substrate according to claim 4, wherein the number of pixel rows having the same interval of N via holes or the number of pixel rows having the same interval are periodically arranged.

The array substrate according to any one of claims 1 to 5, wherein a thin film transistor region of a pixel structure of two adjacent thin film transistors in a multi-line thin film transistor pixel structure divided by the gate line is adjacently arranged. The display regions of the adjacent two rows of thin film transistor pixel structures are respectively arranged adjacent to the display regions of the thin film transistor pixel structures of adjacent rows.

The array substrate according to claim 6, wherein each of the thin film transistor pixel structures in the multi-line thin film transistor pixel structure is provided with one of the common electrode lines.

The array substrate according to claim 6, wherein the two rows of thin film transistor pixel structures arranged adjacent to each other in the display area are provided with only one of the common electrode lines, and the common electrode lines are located adjacent to the display area. The junction of the pixel structure of the thin film transistor.

The array substrate according to any one of claims 1 to 8, wherein the pixel electrode in the thin film transistor pixel structure is a strip electrode, the common electrode is a bulk electrode, the pixel electrode and the A passivation layer is disposed between the common electrodes.

The array substrate according to any one of claims 1 to 9, wherein the common electrode is a bulk electrode covering the entire array substrate.

The array substrate according to any one of claims 1 to 10, wherein the pixel electrode is connected to a drain electrode of the thin film transistor through a through hole, and the common electrode has a diameter formed around the through hole. An isolation hole larger than the through hole.

The array substrate according to any one of claims 1 to 11, wherein the common electrode line and the gate line are in the same layer and are parallel to the gate line.

The array substrate according to any one of claims 1 to 12, wherein the array substrate is an array substrate using retinal display technology.

14. A method of fabricating an array substrate, comprising the steps of:

The manufacturing method of claim 14, wherein the step S2 comprises: forming a thin film transistor on the substrate after the step S1 is completed;

16. The fabrication method according to claim 14 or 15, wherein the at least one common electrode line pattern is located in a display area of the thin film transistor pixel structure or at a boundary of two adjacent thin film transistor pixel structures.

The fabrication method according to claim 14 or 15, wherein each of the thin film transistor pixel structures is correspondingly provided with one of the common electrode line patterns.

The manufacturing method according to claim 14 or 15, wherein in the step S1, when the gate line pattern and the gate pattern of the thin film transistor are formed, the phase of the multi-line thin film transistor pixel structure divided by the gate line is made The gate regions of the adjacent two rows of thin film transistor pixel structures are adjacently arranged, and the display regions of the two rows of thin film transistor pixel structures adjacent to the gate region and the display regions of the thin film transistor pixel structures in the upper and lower adjacent rows respectively Arranged adjacently.

The manufacturing method according to any one of claims 18 to 28, wherein, when the common electrode line pattern is formed, two rows of thin film transistor pixel structures arranged adjacent to the display area form only one common electrode line. And the common electrode line is formed at a boundary of two rows of thin film transistor pixel structures arranged adjacent to the display region.

A display device comprising the array substrate according to any one of claims 1-13.