CN102929056B - A kind of array base palte and manufacture method, display device - Google Patents
A kind of array base palte and manufacture method, display device Download PDFInfo
- Publication number
- CN102929056B CN102929056B CN201210448685.7A CN201210448685A CN102929056B CN 102929056 B CN102929056 B CN 102929056B CN 201210448685 A CN201210448685 A CN 201210448685A CN 102929056 B CN102929056 B CN 102929056B
- Authority
- CN
- China
- Prior art keywords
- public electrode
- metal level
- electrode wire
- base palte
- array base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Embodiments providing a kind of array base palte and manufacture method, display device, relate to Display Technique field, the public electrode line resistance solved in prior art on LCD device array substrates is big, the problem of display quality of liquid crystal display device difference.A kind of array base palte, including: transparency carrier, the grid metal level being arranged on described transparency carrier, source and drain metal level；Wherein, described grid metal level includes: grid line and grid, and described source and drain metal level includes: data wire, source electrode and drain electrode；Also include: public electrode wire metal level and insulating barrier；Described insulating barrier is between described public electrode wire metal level and described grid metal level, or between described public electrode wire metal level and described source and drain metal level；Described public electrode wire metal level includes: a plurality of public electrode wire arranged in a crossed manner.The present invention is applicable to array base palte and the design of display device and manufacture.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and manufacture method, display dress
Put.
Background technology
At present at TFT-LCD (Thin Film Transistor-Liquid Crystal Display, thin film transistor (TFT)
Liquid crystal display) display field, along with the continuous renewal of technology, display panels is towards maximization
Develop rapidly.
Existing display panels, including array base palte, color membrane substrates and be arranged on array base palte and coloured silk
Liquid crystal between film substrate.As it is shown in figure 1, be applied to TN (Twist Nematic, twisted-nematic) type liquid
Array base palte in crystal display includes: grid line 1, data wire 2, thin film transistor (TFT) 3, public electrode wire 4
And pixel electrode 5；Wherein, thin film transistor (TFT) 3 includes grid 31, source electrode 32 and drain electrode 33, grid
31 are connected with grid line 1, and source electrode 32 is connected with data wire 2, and drain electrode 33 is connected with pixel electrode 5, public
Electrode wires 4 and the public electrode electrical connection being arranged on color membrane substrates.
Above-mentioned public electrode wire 4 is divided into two kinds according to the direction of arrangement, and a kind of is the first horizontal common electrical
Polar curve 41 and the second longitudinal public electrode wire 42.Public electrode wire 4 generally sets with layer with above-mentioned grid line 1
Put, and with grid line 1 without electrically connecting；In order to ensure that public electrode wire 4 does not contacts with grid line 1, horizontal
One public electrode wire 41 is parallel with grid line 1, and the second public electrode wire 42 of longitudinal direction is due to can not be with grid line 1
Contact, therefore be to be interrupted.In order to realize the conducting of the second longitudinal public electrode wire 42, need to pass through via
Connected by connecting line 6.Further for the step reduced in processing technology, usual connecting line 6 and pixel electricity
Pole 5 is arranged with layer, and the material of such connecting line 6, as the material of pixel electrode, is ITO (Indium tin
Oxide, tin indium oxide).
But, owing to ITO resistance is relatively big, add via technique and there is the worst factor, thus,
The resistance value being easy to make public electrode wire overall increases, and easily causes that display picture is the greenest, flicker and residual
The harmful effect of the aspects such as picture, the display quality finally making display panels is poor.Particularly with bigger
The display panels of size, the resistance of public electrode wire increases, and can have a strong impact on the aobvious of display panels
Show quality.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method, display device, it is possible to reduce battle array
The resistance of public electrode wire on row substrate, thus improve the display quality of the display applying this array base palte.
For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that
Embodiments provide a kind of array base palte, including: transparency carrier, it is arranged on described transparent base
Grid metal level on plate, source and drain metal level；Wherein, described grid metal level includes: grid line and grid, described
Source and drain metal level includes: data wire, source electrode and drain electrode；Also include: public electrode wire metal level and insulating barrier；
Described insulating barrier is between described public electrode wire metal level and described grid metal level, or is positioned at described public affairs
Between common-battery polar curve metal level and described source and drain metal level；Described public electrode wire metal level includes: a plurality of friendship
The public electrode wire that fork is arranged.
Optionally, described public electrode wire metal level includes: a plurality of the first public electrode wire being parallel to each other,
And a plurality of the second public electrode wire being parallel to each other；Wherein, described first public electrode wire and described second
Public electrode wire intersects.
Optionally, two article that the most adjacent distance between two the first public electrode wires is equal and the most adjacent
Distance between two public electrode wires is equal.
Optionally, described first public electrode wire is parallel with described grid line, described second public electrode wire and institute
State data wire parallel.
Optionally, described array base palte also includes: transparent with what described public electrode wire metal level was disposed adjacent
Conductive layer, described transparency conducting layer includes: the pattern of public electrode；Described public electrode and described common electrical
Polar curve directly contacts.
Optionally, there is overlapping region in described public electrode and described public electrode wire.
Optionally, described transparency conducting layer also includes: the pattern of pixel electrode, described pixel electrode and described
Drain electrode is electrically connected by via.
Embodiments provide a kind of display device, including: the array base palte that the embodiment of the present invention provides.
Embodiments provide the manufacture method of a kind of array base palte, including: arrange on the transparent substrate
The step of grid metal level, and the step of source and drain metal level is set on the transparent substrate, also include: transparent
The step of public electrode wire metal level is set on substrate；Wherein, described public electrode wire metal level includes: many
The public electrode wire that bar is arranged in a crossed manner；
The described step arranging public electrode wire metal level on the transparent substrate is arranged on the transparent substrate with described
Between the step of grid metal level, or, the described step that public electrode wire metal level is set on the transparent substrate
And between the described step arranging source and drain metal level on the transparent substrate, described manufacture method also includes: thoroughly
The step of insulating barrier is set on bright substrate.
Optionally, before or after the described step that public electrode wire metal level is set on the transparent substrate, also
Including: the step of the transparency conducting layer being disposed adjacent with described public electrode wire metal level is set on the transparent substrate
Suddenly, described transparency conducting layer includes: the pattern of public electrode；Described public electrode and described public electrode wire
Directly contact.
Optionally, described transparency conducting layer also includes: the pattern of pixel electrode.
A kind of array base palte of embodiment of the present invention offer and manufacture method, display device, at array base palte
In, public electrode wire is arranged on public electrode wire metal level, in other words, is that public electrode wire is arranged
On single one layer, and do not arrange with layer with grid line or data wire；So, public electrode wire is no need for leading to
Via and be arranged on the connecting line of interlayer and be attached such that it is able to reduce public electrode on array base palte
The resistance of line, and then improve the display quality of the display applying this array base palte.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example or description of the prior art, the required accompanying drawing used is briefly described, it should be apparent that, describe below
In accompanying drawing be only some embodiments of the present invention, for those of ordinary skill in the art, do not paying
On the premise of going out creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the plan structure schematic diagram of the array base palte of a kind of TN type liquid crystal display in prior art；
Fig. 2 provides the plan structure of array base palte in a kind of ADS type liquid crystal display to show for the embodiment of the present invention
It is intended to；
The plan structure of array base palte in a kind of IPS type liquid crystal display that Fig. 3 provides for the embodiment of the present invention
Schematic diagram；
In a kind of TN type liquid crystal display that Fig. 4 provides for the embodiment of the present invention, the plan structure of array base palte is shown
It is intended to；
Fig. 5-Fig. 8 is the plan structure schematic diagram during manufacture array base palte shown in Fig. 2；
Fig. 9 is the plan structure schematic diagram of public electrode wire on the array base palte shown in Fig. 4；
Figure 10 is the a-a` cross-sectional schematic of a kind of array base palte shown in Fig. 2；
The method schematic diagram of a kind of manufacturing array substrate that Figure 11 provides for the embodiment of the present invention.
Reference:
1-grid line；2-data wire；3-thin film transistor (TFT)；4-public electrode wire；5-pixel electrode；6-connecting line；
7-public electrode；8-transparency carrier；9-insulating barrier；10-gate insulation layer；11-active layer；12-protective layer；31-
Grid；32-source electrode；33-drains；41-the first public electrode wire；42-the second public electrode wire.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, be fully described by, it is clear that described embodiment be only a part of embodiment of the present invention rather than
Whole embodiments.
In the embodiment of the present invention " on ", D score be as the criterion with sequencing during manufacturing array substrate, example
As, refer to relatively at the pattern of rear formation at upper pattern, under pattern refer to the figure that is relatively previously formed
Case.
The embodiment of the present invention provide array base palte go for organic light-emitting display device (OLED,
Organic Light Emitting Display), it is also possible to it is applicable to liquid crystal indicator.Wherein, liquid
Crystal device utilizes electric field to pass through LCD Controlling translucidus to show image.According to the electric field side driving liquid crystal
To, liquid crystal indicator is roughly divided into vertical electric field driving driving with horizontal component of electric field.Vertical electric field drives
Ejector half liquid crystal indicator is public electrode positioned opposite to each other and pixel electrode on upper and lower base plate, in described public affairs
Forming vertical electric field between common electrode and pixel electrode to drive liquid crystal, such as TN, (TwistNematic turns round
Qu Xianglie) type, VA (Vertical Alignment, multi-domain vertical alignment) type liquid crystal indicator.Level
Electric field drive liquid crystal indicator arranges public electrode and pixel electrode on infrabasal plate, in described common electrical
The electric field of level is formed to drive liquid crystal, such as ADS (Advanced-Super between pole and pixel electrode
Dimensional Switching, senior super dimension field switch) type, IPS (In Plane Switch, transverse electric field
Effect) type liquid crystal indicator.
In order to reduce the resistance of public electrode wire, with reference to Fig. 2-Fig. 4 either figure, the embodiment of the present invention provides
A kind of array base palte, including: transparency carrier, the grid metal level being arranged on described transparency carrier, source and drain
Metal level；Wherein, described grid metal level includes: grid line 1 and grid 31, and described source and drain metal level includes:
Data wire 2, source electrode 32 and drain electrode 33；Also include: public electrode wire metal level and insulating barrier；Described public
Electrode wires metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.
In embodiments of the present invention, above-mentioned grid metal level, source and drain metal level, public electrode wire metal level and absolutely
Edge layer, is single layer.The implication of " layer " may refer to utilize a certain material to utilize deposition on substrate
The thin film produced etc. technique；Insulating barrier as escribed above can be to deposit SiNx (nitrogen on the transparent substrate
SiClx) obtained by.The implication of " layer " can also refer to utilize a certain material to utilize deposition etc. on substrate
Technique produces thin film, and the Rotating fields comprising multiple pattern formed by patterning processes；Such as,
Above-mentioned grid metal level may refer to deposit on the transparent substrate molybdenum, prepares metallic film, and by a structure
Figure technique forms the Rotating fields comprising grid line, grid；For another example, above-mentioned source and drain metal level may refer to thoroughly
Deposit molybdenum on bright substrate, prepare metallic film, and comprise data wire, source electrode by a patterning processes formation
Rotating fields with drain electrode；And for example, above-mentioned public electrode wire metal level can be to deposit gold on the transparent substrate
Belong to material, prepare metallic film, and form, by a patterning processes, the Rotating fields comprising public electrode wire；
And for example, above-mentioned insulating barrier can according to actual needs, and deposition SiNx making insulation is thin the most on the transparent substrate
Film, is removing part by patterning processes on insulation film, forms via at ad-hoc location, prepares insulation
Layer.It is to say, in embodiments of the present invention, different layers is that (material is identical or not by different thin film
With) formed.
Above-mentioned source electrode, drain and gate are three electrodes of thin film transistor (TFT), according to the position relationship of electrode
Thin film transistor (TFT) is divided into two classes.One class grid is positioned at below source electrode and drain electrode, this kind of referred to as bottom gate
Type thin film transistor (TFT)；One class grid is positioned at above source electrode and drain electrode, and this kind of referred to as top gate type thin film is brilliant
Body pipe.
Owing to public electrode wire is in order to public electrode input voltage, so public electrode wire needs with public
Electrode electrically connects.And public electrode wire is not typically connected with other conductive patterns, such as public electrode wire is neither
Can electrically connect with the pattern on grid metal level, can not electrically connect with the pattern on the metal level of source, so needing
Insulating barrier is set to avoid connecting of public electrode wire and other conductive patterns by mistake.Hereinafter, by combination film crystal
The two types of pipe is specifically described the position of insulating barrier.
For being provided with the array base palte of bottom gate thin film transistor, if public electrode wire metal
Layer is arranged on below grid metal level, then this insulating barrier needs to be arranged on public electrode wire metal level and grid metal
Between Ceng；If public electrode wire metal level is arranged on above source and drain metal level, then insulating barrier needs to be arranged on
Between public electrode wire metal level and source and drain metal level.
Secondly, for being provided with the array base palte of top gate type thin film crystal, if public electrode wire metal level
Be arranged on below source and drain metal level, then this insulating barrier needs to be arranged on public electrode wire metal level and source and drain gold
Belong between layer；If public electrode wire metal level is arranged on above grid metal level, then insulating barrier needs to be arranged on
Between public electrode wire metal level and grid metal level.Described electrical connection, for by directly contact, wire, mistake
The modes such as hole realize the conducting of circuit.
The array base palte that the embodiment of the present invention provides, is arranged on public electrode wire on public electrode wire metal level,
In other words, it is public electrode wire to be arranged on single one layer, and does not arranges with layer with grid line or data wire；
So, public electrode wire is no need for by via and is arranged on the connecting line of interlayer and is attached, it is thus possible to
Enough reduce the resistance of public electrode wire on array base palte, and then improve the display device applying this array base palte
Display quality.
It addition, the insulating barrier on above-mentioned array base palte makes public electrode wire not electrically connect with other conductive patterns,
Thus ensure that the display comprising above-mentioned array base palte can normally work.Furthermore, due to grid line and public
Electrode wires is arranged on the different layers, so can shorten the distance of grid line and public electrode wire as required, from
And can suitably increase pixel aperture ratio.
Preferably, such as Fig. 2-4 either figure, described public electrode wire metal level includes: a plurality of be parallel to each other
First public electrode wire 41, and a plurality of the second public electrode wire 42 being parallel to each other；Wherein, described first
Public electrode wire 41 intersects with described second public electrode wire 42.
Further, described first public electrode wire 41 is parallel with described grid line 42, described second common electrical
Polar curve 42 is parallel with described data wire.Public electrode wire the first public electrode wire 41 and second so formed
Public electrode wire 42 is orthogonal, as shown in Figure 6.The most whole public electrode wire is an entirety, is not required to
Will be through via and be arranged on the connecting line of interlayer and be attached, it is possible to reduce public electrode on array base palte
The resistance of line, and then improve the display quality of the display applying this array base palte.
Further, two that the most adjacent distance between two the first public electrode wires is equal and the most adjacent
Distance between the second public electrode wire is equal.The public electrode wire so arranged, due to the most adjacent two articles the
Between one public electrode wire the most equal with the distance between two the most adjacent the second public electrode wires, then the public affairs that formed
The cancellated sizing grid of common-battery polar curve is identical, and public electrode wire has preferable homogeneity, can be very
The skew avoiding common electric voltage of big degree, thus improve the display of this array base palte of application further
Display quality.
Below, the array base palte for above-mentioned offer is applied to different types of display dress by the embodiment of the present invention
Structure when putting is described in detail.
Embodiments provide a kind of array base palte being applied to TN type display device, as shown in Figure 4,
Described array base palte includes: transparency carrier, the grid metal level that is arranged on described transparency carrier, source and drain metal
Layer；Wherein, described grid metal level includes: grid line 1 and grid 31, and described source and drain metal level includes: data
Line 2, source electrode 32 and drain electrode 33；Also include: the transparency conducting layer comprising pixel electrode pattern, and public
Electrode wires metal level and insulating barrier.
Described public electrode metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.Wherein, public electrode
Line 4 is referred to the description above, is not added with at this repeating.It addition, the equally reference of the position of insulating barrier
The description above, is not added with at this repeating.
Certainly, for the array base palte of TN type display device, in order to increase the aperture opening ratio of pixel, it is preferred that
A lateral edges of the first public electrode wire arranges second public electrode wire on the transparent substrate, and first is public
Electrode wires and the second public electrode wire are arranged in a crossed manner, and the second public electrode wire passes through conducting resinl and is arranged on coloured silk
Public electrode electrical connection on film substrate.But so the resistance of public electrode wire is uneven, in order to obtain uniformly
The public electrode wire of resistance, it is further preferred that its public electrode wire 4 can also be as it is shown in figure 9, thoroughly
On bright substrate, the both sides of the edge of the first public electrode wire are respectively provided with second public electrode wire, and the second public affairs
Common-battery polar curve is electrically connected with the public electrode being arranged on color membrane substrates by conducting resinl.
Optionally, public electrode wire metal level is positioned at array base palte bottom, and this insulating barrier to cover this public
Electrode wires metal level.So change to whole manufacturing process is smaller, but does not limits
It is set to this kind of implementation.
The electrical connection of above-mentioned each pattern is: grid line 1 electrically connects by the way of directly contacting with grid 31,
Data wire 2 electrically connects by the way of directly contacting with source electrode 32, and drain electrode 33 can be led to pixel electrode 5
Via electrically connects.Further, since the public electrode of TN type display device is arranged on color membrane substrates, so
Public electrode wire 4 on above-mentioned array base palte can be electrically connected by conducting resinl and public electrode.
For being applied to the array base palte of ADS type or IPS type display device, as shown in Figure 2 and Figure 3,
Array base palte needs arrange public electrode 7 and pixel electrode 5.Such array base palte also includes:
The transparency conducting layer being disposed adjacent with described public electrode wire metal level, described transparency conducting layer includes: public
The pattern of electrode 7；Preferably, described public electrode 7 directly contacts with described public electrode wire 4.So,
The conductive structure that need not to re-use other just can be directly realized by the electricity of public electrode 7 and public electrode wire 4
Connecting, because need not other conductive structure, therefore the step in array base palte processing procedure can be reduced.
Wherein, directly contact can be that two patterns are adjacent and contact, it is also possible to refer to two patterns exist part or
All overlap and contacts.In embodiments of the present invention, it is preferably, sectional view as shown in Figure 10, described public affairs
There is overlapping region in common electrode 7 and described public electrode wire 4.So public electrode 7 and public electrode wire 4
Can preferably contact, it is achieved the circuit turn-on between public electrode 7 and public electrode wire 4.
Concrete, embodiments provide a kind of array base palte being applied to ADS type display device, as
Shown in Fig. 2, described array base palte includes: transparency carrier, the grid metal level that is arranged on described transparency carrier,
Source and drain metal level；Wherein, described grid metal level includes: grid line 1 and grid 31, described source and drain metal level bag
Include: data wire 2, source electrode 32 and drain electrode 33；Also include: public electrode wire metal level and insulating barrier；Described
Public electrode wire metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.It addition, also include: two-layer is saturating
Bright conductive layer；Wherein a transparency conducting layer comprises the pattern of public electrode 7, and this transparency conducting layer and public
Electrode wires metal level is disposed adjacent；Another transparency conducting layer comprises the pattern of pixel electrode 5.
As shown in Figure 6, described public electrode metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.Its
In, public electrode wire 4 is referred to the description above, is not added with at this repeating.It addition, the position of insulating barrier
Equally with reference to the description above, it is not added with at this repeating.
Optionally, the transparency conducting layer and the public electrode wire metal level that comprise public electrode 7 pattern are in battle array
The two-layer of row substrate bottom, and this insulating barrier covers this two-layer.So change ratio to whole manufacturing process
Less.Further, as shown in Figure 10, the transparency conducting layer comprising public electrode 7 pattern is positioned at array base
The bottom of plate, public electrode wire metal level is positioned on this transparency conducting layer, and insulating barrier covers this two-layer.But
It is not limited to this kind of implementation in embodiments of the present invention.
The electrical connection of above-mentioned each pattern is: grid line 1 electrically connects by the way of directly contacting with grid 31,
Data wire 2 electrically connects by the way of directly contacting with source electrode 32, and drain electrode 33 can be led to pixel electrode 5
Via electrically connects, and public electrode wire 4 electrically connects in the way of directly contacting with public electrode 7.
For the array base palte of ADS type liquid crystal indicator, it is by being arranged on the public affairs on described array base palte
Common electrode 7 and pixel electrode 5 form multi-dimensional electric field, make liquid crystal molecule can produce rotation, it is achieved display
Function.And multi-dimensional electric field to be formed, electrode above in two electrodes is formed multiple slit, is positioned at
The electrode of lower section can be plate shaped or be formed with multiple slit.If the electrode of top is electrically connected with drain electrode 33
Connect, then this electrode is pixel electrode；Now, the electrode of lower section needs to electrically connect with public electrode wire 4, should
Electrode is public electrode.On the contrary, electrode above can make public electrode, now, is positioned at lower section
Electrode is as pixel electrode.
Example, as in figure 2 it is shown, be formed multiple narrow on pixel electrode 5 above in the present embodiment
Seam, is positioned at the public electrode 7 of lower section for plate shaped.In the case of circuit turn-on, pixel electrode 5 is with public
Common electrode 7 can form multi-dimensional electric field.
Concrete, embodiments provide a kind of array base palte being applied to IPS type display device, as
Shown in Fig. 3, described array base palte includes: transparency carrier, the grid metal level that is arranged on described transparency carrier,
Source and drain metal level；Wherein, described grid metal level includes: grid line 1 and grid 31, described source and drain metal level bag
Include: data wire 2, source electrode 32 and drain electrode 33；Also include: public electrode wire metal level and insulating barrier；Described
Public electrode wire metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.It addition, also include: one is transparent
Conductive layer, described transparency conducting layer includes: the pattern of public electrode 7 and the pattern of pixel electrode 5.
As it is shown on figure 3, described public electrode metal level includes: a plurality of public electrode wire 4 arranged in a crossed manner.Its
In, public electrode wire 4 is referred to the description above, is not added with at this repeating.It addition, the position of insulating barrier
Equally with reference to the description above, it is not added with at this repeating.
Optionally, public electrode 7 pattern and the transparency conducting layer of pixel electrode 5 pattern and public electrode are comprised
Line metal level is in the two-layer of array base palte bottom, and this insulating barrier covers this two-layer.So to whole
The change of manufacturing process is smaller.Further, this transparency conducting layer is positioned at the bottom of array base palte, public
Common-battery polar curve metal level is positioned on this transparency conducting layer, and insulating barrier covers this two-layer.But in the embodiment of the present invention
In be not limited to this kind of implementation.
The electrical connection of above-mentioned each pattern is: grid line 1 electrically connects by the way of directly contacting with grid 31,
Data wire 2 electrically connects by the way of directly contacting with source electrode 32, and drain electrode 33 can be led to pixel electrode 5
Via electrically connects, and public electrode wire 4 electrically connects in the way of directly contacting with public electrode 7.
Different from the displaying principle of ADS type liquid crystal indicator, IPS type liquid crystal indicator is to pass through array
Public electrode 7 on substrate and pixel electrode 5 form the electric field driven liquid crystal of level, thus realize showing merit
Energy.And the electric field of level to be formed, public electrode 7 and pixel electrode 5 need to be arranged on same layer, such as Fig. 3
Shown in, described pixel electrode 5 and described public electrode 7 include multiple electrical connection strip electrode, shape respectively
Becoming pectinate texture as shown in Figure 3, the strip electrode of pixel electrode 5 is flat with the strip electrode of public electrode 7
Row alternately arranged and between have gap with ensure adjacent bar electrode do not contact.Wherein electrically connect with drain electrode 33
Electrode is pixel electrode；Now, the electrode relative with this electrode needs to electrically connect with public electrode wire 4, for
Public electrode.
It should be noted that all accompanying drawings of the embodiment of the present invention show emphatically portion related to the present invention
Point, other parts are not shown.
It addition, the array base palte that the present invention provides can also be applied to VA type display device, and OLED
In, those skilled in the art pass through the description of various embodiments of the present invention and combine prior art, it is possible to clearly
Understand the structure of the array base palte being applied to both display devices, thus the most detailed
State.
Below, the embodiment of the present invention additionally provides a kind of manufacture method manufacturing above-mentioned array base palte, needs
Bright, the Rotating fields of above-mentioned array base palte is completed by following steps, therefore in the following embodiments to each
The concrete pattern of layer and circuit connection are not described in detail.
Embodiments provide the manufacture method of a kind of array base palte, including: arrange on the transparent substrate
The step (S101) of grid metal level, and the step (S102) of source and drain metal level is set on the transparent substrate；
Also include: the step (S103) of public electrode wire metal level is set on the transparent substrate；Wherein, described public
Electrode wires metal level includes: a plurality of public electrode wire arranged in a crossed manner.
For any one liquid crystal indicator, public electrode wire is public electrode input voltage, so public
Common-battery polar curve needs to electrically connect with public electrode, and is not connected with other conductive patterns, then described manufacturer
Method also includes: arrange the step (S104) of insulating barrier on the transparent substrate.
It addition, no matter for which type of array base palte, in addition it is also necessary to step S101 and step S102 it
Between, it is provided with active layer on the transparent substrate.Further, so that be not required between the conductive pattern of electrical connection not lead
Logical, may also need on the transparent substrate arrange other insulating barriers.Those skilled in the art can be in conjunction with existing
The manufacturing step that technology clearly also needs to, does not elaborates.
The sequencing of aforementioned four step, can be decided according to the actual requirements, different sequencing manufactures
The structure of the array base palte gone out can difference.
Concrete, as shown in figure 11, for being provided with the array base palte of bottom gate thin film crystal, described
Manufacture method may comprise steps of successively: step S103, step S104, step S101, step S102.
Carrying out the array base palte of above step formation successively, public electrode wire metal level is positioned at the orlop of array base palte,
Insulating barrier is positioned at the last layer of public electrode wire metal level, and grid metal level is positioned at the last layer of insulating barrier, source
Leakage metal level is positioned at the upper strata of grid metal level.Described last layer can be adjacent two-layer, located above one
Layer referred to as last layer；Described upper strata can be to be additionally provided with other layers between two-layer pattern, is positioned at other layers
One layer above is referred to as upper strata.
So, insulating barrier between public electrode wire metal level and grid metal level, then public electrode wire and grid
Pole will not form electrical connection, thus ensures that the display comprising above-mentioned array base palte can normally work.
Optionally, for being provided with the array base palte of bottom gate thin film crystal, described manufacture method is successively
May comprise steps of: step S101, step S102, step S104, step S103.Carry out successively
On the array base palte that above step is formed, grid metal level is positioned at the orlop of array base palte, source and drain metal level position
In the upper strata of grid metal level, insulating barrier is positioned at the last layer of source and drain metal level, and public electrode wire metal level is positioned at
The last layer of insulating barrier.So, insulating barrier is between source and drain metal level and public electrode wire metal level, then
Source electrode, drain electrode and data wire will not be formed with public electrode wire and electrically connect, thus ensures to comprise above-mentioned array
The display of substrate can normally work.
Optionally, for being provided with the array base palte of top gate type thin film crystal, described manufacture method is successively
May comprise steps of: step S103, step S104, step S102, step S101.Carry out successively
The array base palte that above step is formed, public electrode wire metal level is positioned at the orlop of array base palte, insulating barrier
It is positioned at the last layer of public electrode wire metal level, and source and drain metal level is positioned at the last layer of insulating barrier, grid metal
Layer is positioned at the upper strata of source and drain metal level.So, insulating barrier be positioned at public electrode wire metal level and grid metal level it
Between, then public electrode wire and grid will not form electrical connection, thus ensure the display comprising above-mentioned array base palte
Device can normally work.
Optionally, for being provided with the array base palte of top gate type thin film crystal, described manufacture method is successively
May comprise steps of: step S101, step S102, step S103, step S104.Carry out successively
The array base palte that above step is formed, grid metal level is positioned at the orlop of array base palte, and source and drain metal level is positioned at
The upper strata of grid metal level, and insulating barrier is positioned at the last layer of source and drain metal level, public electrode wire metal level is positioned at
The last layer of insulating barrier.So, insulating barrier is between source and drain metal level and public electrode wire metal level, then
Source electrode, drain electrode and data wire will not be formed with public electrode wire and electrically connect, thus ensures to comprise above-mentioned array
The display of substrate can normally work.
Above-mentioned manufacture method can be applicable to the liquid crystal indicator of any one type, further, the present invention
Embodiment is also directed to the setting of pixel electrode or public electrode in different type arrays substrates and carries out specifically
Bright.
If the array base palte manufactured in TN type display device, in addition it is also necessary to arrange a layer and comprise pixel electrode pattern
Transparency conducting layer.Example, after completing aforementioned four step, layer protective layer can be set (also
It is the Rotating fields playing insulating effect), and on this protective layer, it is communicated with the via drained, then setting comprises
The transparency conducting layer of pixel electrode pattern so that pixel electrode is connected with drain electrode.
If the array base palte manufactured in ADS type display device, in addition it is also necessary to two-layer transparency conducting layer is set, its
In one layer include pixel electrode pattern, another layer includes public electrode pattern.To make public electrode
Directly contact with public electrode wire, optionally, the described public electrode wire metal level of arranging on the transparent substrate
Before or after step (S103), also include: arrange and described public electrode wire metal on the transparent substrate
The step of the transparency conducting layer that layer is disposed adjacent, this transparency conducting layer includes: the pattern of public electrode.Enter one
Step, example, complete above-mentioned in steps after, arrange on layer protective layer, and this protective layer
It is communicated with the via of drain electrode, then the transparency conducting layer comprising pixel electrode pattern is set so that pixel electrode
It is connected with drain electrode.
If the array base palte manufactured in IPS type display device, in addition it is also necessary to arrange a layer and both included common electrical
Pole pattern includes again the transparency conducting layer of pixel electrode pattern.Optionally, described arrange on the transparent substrate
Before or after the step (S103) of public electrode wire metal level, also include: on the transparent substrate arrange with
The step of the transparency conducting layer that described public electrode wire metal level is disposed adjacent, this transparency conducting layer includes: public
The pattern of common electrode and the pattern of pixel electrode, now, pixel electrode can be by arranging the mistake on insulating barrier
Hole makes pixel electrode electrically connect with drain electrode.
Below, as a example by ADS type liquid crystal indicator in detail, the manufacture method of the array base palte of described device is described in detail,
Wherein, the thin film transistor (TFT) of described array base palte is bottom gate type and public electrode metal level is arranged on grid metal level
Below.
Concrete, the method manufacturing this array base palte comprises the following steps:
Step 1, as shown in Fig. 5, Figure 10, transparency carrier 8 arranges one and comprises public electrode 7 pattern
Transparency conducting layer.
Example, deposit transparent conductive material, such as tin indium oxide ITO on the transparent substrate, form transparent leading
Conductive film, by a patterning processes according to pixel distribution, forms transparency conducting layer, this transparency conducting layer bag
Containing public electrode 7 pattern arranged in the form of an array in Fig. 4.
Step 2, as shown in Fig. 6, Figure 10, transparency carrier 8 is arranged and comprises the public affairs of public electrode wire 4
Common-battery polar curve metal level.
Example, make a metallic film on the transparent substrate, at least form Fig. 6 by a patterning processes
In public electrode wire 4, and public electrode wire 4 comprises horizontal first public electrode wire 41 and longitudinal the
Two public electrode wires 42.For public electrode 7 and the good contact of public electrode wire 4, there is overlap in both
Region, it is preferred that the first public electrode wire 41 and the second public electrode wire 42 all exist with public electrode 7
Overlapping region.
Step 3, as shown in Figure 10, arranges insulating barrier 9 to cover above-mentioned transparent lead on transparency carrier 8
Electric layer and public electrode wire metal level.
Step 4, as shown in Fig. 7, Figure 10, transparency carrier 8 arranges grid metal level.
Described grid metal level includes: grid line 3 and the pattern of grid 31, and wherein grid 31 can be grid line 3
A part.
Example, insulating barrier 9 makes metallic film, and by a patterning processes, forms grid metal
Layer.
Step 5, as shown in Figure 10, arranges gate insulation layer 10 on transparency carrier 8.
Step 6, as shown in Figure 10, is provided with active layer 11 on transparency carrier 8.
Example, on the transparency carrier 8 being formed with grid metal level, make semiconductive thin film, and by one
Secondary patterning processes is formed above active layer 11 at grid.
Step 7, source and drain metal level is set as shown in Fig. 8, Figure 10 on transparency carrier 8.
Described source and drain metal level includes: data wire 2, source electrode 32 and the pattern of drain electrode 33, wherein, and source electrode
32 are connected with data wire 2.
Example, on the transparency carrier 8 being formed with active layer 11, make source and drain metallic film, and pass through
One time patterning processes forms source and drain metal level.
Step 8, as shown in Figure 10, arranges protective layer 12 on transparency carrier 8.
Example, transparency carrier 8 makes insulation film, and by patterning processes, removes and be positioned at drain electrode
On part, formed and be provided with the protective layer 12 of via.
Step 9, as shown in Fig. 2, Figure 10, arrange on the transparent substrate and include the pattern of pixel electrode 5
Transparency conducting layer.
Example, transparency carrier 8 makes transparent conductive film, and by a patterning processes, is formed
The pattern of pixel electrode 5, this pixel electrode 5 is connected with described drain electrode 33 by via.
The step of above-mentioned making array base palte the most not only limits to the description above, for example, it is also possible to first carry out
Step S102 carries out step S101 again, as long as realizing the conducting of public electrode and public electrode wire.
The manufacture method of a kind of array base palte that the embodiment of the present invention provides, described manufacture method includes: arrange
The step of public electrode wire metal level, such public electrode wire is individually for one layer, and not with grid line or data wire
Arrange with layer；Public electrode wire is no need for by via and is arranged on the connecting line of interlayer and is attached, from
And the resistance of public electrode wire on array base palte can be reduced, and then improve the display applying this array base palte
The display quality of device.It addition, by mistake connecting in order to avoid public electrode wire and other conductive patterns, thus protect
Having demonstrate,proved the display comprising above-mentioned array base palte can normally work, described manufacture method also includes: arrange absolutely
The step of edge layer.Furthermore, owing to grid line and public electrode wire step at twice is respectively provided with, so can root
According to needing shortening grid line and the distance of public electrode wire, such that it is able to suitably increase pixel aperture ratio.
The embodiment of the present invention additionally provides a kind of display device, including: any one of embodiment of the present invention offer
Array base palte, the manufacture method that described array base palte can be provided by the embodiment of the present invention obtains.Described display
Device can be liquid crystal display, LCD TV, digital camera, mobile phone, panel computer etc. any have aobvious
Show product or the parts of function.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art, in the technical scope that the invention discloses, can readily occur in
Change or replacement, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention
Should be as the criterion with described scope of the claims.
Claims (8)
1. an array base palte, including: transparency carrier, the grid metal level being arranged on described transparency carrier, source and drain metal level；Wherein, described grid metal level includes: grid line and grid, and described source and drain metal level includes: data wire, source electrode and drain electrode；It is characterized in that, also include: public electrode wire metal level and insulating barrier；Described insulating barrier is between described public electrode wire metal level and described grid metal level, or between described public electrode wire metal level and described source and drain metal level；
Described public electrode wire metal level includes: a plurality of public electrode wire arranged in a crossed manner；
Described array base palte also includes: the transparency conducting layer being disposed adjacent with described public electrode wire metal level, and described transparency conducting layer includes: the pattern of public electrode；
Described public electrode directly contacts with described public electrode wire；
There is overlapping region in described public electrode and described public electrode wire；
Described transparency conducting layer and described public electrode wire metal level are in the two-layer of described transparency carrier bottom, and described insulating barrier covers described transparency conducting layer and described public electrode wire metal level.
Array base palte the most according to claim 1, it is characterised in that described public electrode wire metal level includes: a plurality of the first public electrode wire being parallel to each other, and a plurality of the second public electrode wire being parallel to each other；Wherein, described first public electrode wire intersects with described second public electrode wire.
Array base palte the most according to claim 2, it is characterised in that the distance between two the second public electrode wires that the most adjacent distance between two the first public electrode wires is equal and the most adjacent is equal.
Array base palte the most according to claim 2, it is characterised in that described first public electrode wire is parallel with described grid line, described second public electrode wire is parallel with described data wire.
5., according to the array base palte described in any one of claim 1-4, it is characterised in that described transparency conducting layer also includes: the pattern of pixel electrode, described pixel electrode and described drain electrode are electrically connected by via.
6. a display device, it is characterised in that including: the array base palte described in any one of claim 1-5.
7. a manufacture method for array base palte, including: the step of grid metal level is set on the transparent substrate, and the step of source and drain metal level is set on the transparent substrate, it is characterised in that also include: the step of public electrode wire metal level is set on the transparent substrate；Wherein, described public electrode wire metal level includes: a plurality of public electrode wire arranged in a crossed manner；
Between the described step that public electrode wire metal level is set on the transparent substrate and the described step that grid metal level is set on the transparent substrate, or, between the described step arranging public electrode wire metal level on the transparent substrate and the described step arranging source and drain metal level on the transparent substrate, described manufacture method also includes: arrange the step of insulating barrier on the transparent substrate；
Before or after the described step that public electrode wire metal level is set on the transparent substrate, also include:
Arranging the step of the transparency conducting layer being disposed adjacent with described public electrode wire metal level on the transparent substrate, described transparency conducting layer includes: the pattern of public electrode；Described public electrode directly contacts with described public electrode wire；
There is overlapping region in described public electrode and described public electrode wire；
Described transparency conducting layer and described public electrode wire metal level are in the two-layer of described transparency carrier bottom, and described insulating barrier covers described transparency conducting layer and described public electrode wire metal level.
Manufacture method the most according to claim 7, it is characterised in that described transparency conducting layer also includes: the pattern of pixel electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210448685.7A CN102929056B (en) | 2012-11-09 | 2012-11-09 | A kind of array base palte and manufacture method, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210448685.7A CN102929056B (en) | 2012-11-09 | 2012-11-09 | A kind of array base palte and manufacture method, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102929056A CN102929056A (en) | 2013-02-13 |
| CN102929056B true CN102929056B (en) | 2016-11-16 |
Family
ID=47643890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210448685.7A Active CN102929056B (en) | 2012-11-09 | 2012-11-09 | A kind of array base palte and manufacture method, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102929056B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104298020A (en) * | 2014-10-20 | 2015-01-21 | 京东方科技集团股份有限公司 | Array substrate used in ADS (adaptive damping system) display device |
| CN106292100B (en) * | 2015-05-28 | 2019-12-17 | 鸿富锦精密工业（深圳）有限公司 | Array substrate and liquid crystal display panel with same |
| CN104898335B (en) * | 2015-07-09 | 2018-10-19 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof and display device |
| CN105093750B (en) * | 2015-08-14 | 2018-11-23 | 深圳市华星光电技术有限公司 | Tft array substrate structure and preparation method thereof |
| CN107942528B (en) * | 2018-01-02 | 2021-01-26 | 京东方科技集团股份有限公司 | Naked eye 3D display device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308294A (en) * | 2007-05-17 | 2008-11-19 | 乐金显示有限公司 | In-plane switching mode liquid crystal display device and method for fabricating the same |
| CN102023438A (en) * | 2009-09-18 | 2011-04-20 | 上海天马微电子有限公司 | Liquid crystal display device, manufacturing method thereof and defect repairing method |
| CN102629570A (en) * | 2011-05-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate of FFS type thin-film transistor liquid crystal display and method for manufacturing the same |
| CN102651371A (en) * | 2012-04-06 | 2012-08-29 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method and display device thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8035765B2 (en) * | 2006-11-13 | 2011-10-11 | Hannstar Display Corp. | TFT array substrate, LCD panel and liquid crystal display |
| CN101373301B (en) * | 2007-08-24 | 2010-08-18 | 北京京东方光电科技有限公司 | FFS type TFT-LCD array substrate structure and manufacturing method thereof |
-
2012
- 2012-11-09 CN CN201210448685.7A patent/CN102929056B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308294A (en) * | 2007-05-17 | 2008-11-19 | 乐金显示有限公司 | In-plane switching mode liquid crystal display device and method for fabricating the same |
| CN102023438A (en) * | 2009-09-18 | 2011-04-20 | 上海天马微电子有限公司 | Liquid crystal display device, manufacturing method thereof and defect repairing method |
| CN102629570A (en) * | 2011-05-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate of FFS type thin-film transistor liquid crystal display and method for manufacturing the same |
| CN102651371A (en) * | 2012-04-06 | 2012-08-29 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method and display device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102929056A (en) | 2013-02-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10852865B2 (en) | In-cell touch type display device | |
| CN101995707B (en) | Fringe field switching (FFS) liquid crystal display (LCD) panel, manufacturing method thereof and LCD | |
| US9958720B2 (en) | Display device | |
| CN204595382U (en) | Array base palte and display panels and device and repaired array base palte | |
| CN104813386B (en) | TFT substrate | |
| CN101833200B (en) | Horizontal electric field type liquid crystal display device and manufacturing method thereof | |
| CN102243401B (en) | Liquid crystal display device | |
| US20120127414A1 (en) | Liquid Crystal Display Device and Method for Manufacturing the Same | |
| CN100362414C (en) | Plane switching mode liquid crystal display device and fabrication method thereof | |
| US8599348B2 (en) | High light transmittance in-plane switching liquid crystal display device and method for manufacturing the same | |
| CN104898892A (en) | Touch display panel, manufacturing method thereof and touch display device | |
| CN101414070B (en) | Touch control electrode layer and display panel | |
| US20200117036A1 (en) | Liquid crystal display device and method of manufacturing the same | |
| CN102902119B (en) | Liquid crystal display panel | |
| CN104680957B (en) | Display device and its manufacture and method of testing | |
| CN102169259A (en) | Thin film transistor array substrate and liquid crystal display device | |
| CN102929056B (en) | A kind of array base palte and manufacture method, display device | |
| CN100543524C (en) | Array base palte and manufacture method thereof, display panel and liquid crystal indicator | |
| CN103645589A (en) | Display device, array substrate and manufacturing method of array substrate | |
| CN104007589A (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN102253553A (en) | Liquid crystal display device | |
| CN104570525B (en) | Liquid crystal disply device and its preparation method | |
| CN105093606A (en) | An array substrate, a liquid crystal display panel and a liquid crystal display device | |
| CN103869567A (en) | Array substrate and display device | |
| CN101149549B (en) | Liquid crystal display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |