CN202633310U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN202633310U CN202633310U CN 201220143323 CN201220143323U CN202633310U CN 202633310 U CN202633310 U CN 202633310U CN 201220143323 CN201220143323 CN 201220143323 CN 201220143323 U CN201220143323 U CN 201220143323U CN 202633310 U CN202633310 U CN 202633310U
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Abstract
The utility model discloses an array substrate and a display device, which relate to the display technical field. The array substrate comprises a plurality of grid lines and data lines formed on a substrate, and a plurality of film transistor pixel structures formed between the grid lines and the data lines. Each film transistor pixel structure comprises a film transistor and a display area. Each display area is provided with a common electrode. The array substrate further comprises at least one common electrode line which is connected with the common electrodes. The display device is provided with the above array substrate. The array substrate prevents display frames from generating a crosstalk phenomenon.
Description
Technical field
The utility model relates to the Display Technique field, particularly a kind of array base palte and display unit.
Background technology
A senior ultra dimension switch technology (ADvanced Super Dimension Switch; Be called for short ADS) be the wide visual angle of a kind of plane electric fields core technology; Its core technology characteristic is: the electric field that electric field that is produced through gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field; Make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior ultra dimension switch technology (ADS) can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, no water of compaction ripple advantages such as (push Mura).
R-ADS technology (full name Retina display-ADvanced Super Dimension Switch wherein; Be that retina shows-a senior ultra dimension switch technology); Be that the ADS technical application is shown the new technology among (Retina Display) to retina; Its core technology is characterized as: among the ADS technical application is shown to retina, make ADS display device (like array base palte or liquid crystal panel) possess very-high solution density, realize that promptly picture element density reaches more than the 300PPI.Utilize the display screen of R-ADS technology, will make human eye can't tell independent pixel, make image no longer include granular sensation, shows more true to naturely, can let the beholder have kind to see the sensation of paper products; Simultaneously, possess the above-mentioned advantage of ADS in addition, thereby have broad application prospects.
Along with the ADS technology, especially the R-ADS The Application of Technology is also increasingly high to the requirement of display effect.But; The bad key factor that influences product quality that also becomes in the middle of producing; Especially flicker (flicker), crosstalk (crosstalk) bad and shadow etc., a lot of products all can run in process of production; Never have effective means and control these bad generations, become a great problem in the technological design.
The fluctuation of the storage capacitance of ADS product is to produce one of major reason of flicker always.Because the pixel electrode of more existing ADS products is the separate bulk of each pixel, public electrode is done slivering (slit) shape, because the layout process deviation between the layer causes the fluctuation of two electrode overlapping areas.As shown in Figure 1, wherein (a) (b) shows layout process deviation between the layer, the pixel electrode 200 of the bulk in (b) with respect to interior have strip hole 100 ' public electrode 100 squint left, thereby caused the fluctuation of storage capacitance and caused flicker.And the design adopts pixel electrode last, and public electrode is following, and pixel electrode is done into strips; And public electrode is linked to be an integral body, so the skew of pixel electrode can not cause the fluctuation of storage capacitance, thereby effectively reduces the generation of flicker; Shown in (c) among Fig. 1; Pixel electrode 200 is a strip, 200 ' be the strip hole, public electrode 100 is block.
The public electrode of above-mentioned ADS product forms integral body; But because the bigger influence of resistance; Can cause the source to leak (SD) holding wire and can't in time be dissolved the coupling effect of public electrode, cause the change in voltage of public electrode, the pressure reduction of the driving in the pixel will produce difference; Make display frame produce the crosstalk phenomenon, influenced display effect.And the R-ADS that uses technique scheme is technological, has the problem of crosstalk equally.
The utility model content
The technical problem that (one) will solve
The technical problem that the utility model will solve is: how to avoid the Crosstalk phenomenon that occurs in the ADS display frame.
(2) technical scheme
For solving the problems of the technologies described above; The utility model provides a kind of array base palte; Comprise some grid lines, data wire that is formed on the substrate and the some thin film transistor pixel structures that between said grid line and data wire, form; Said thin film transistor pixel structure comprises thin-film transistor and viewing area, and said viewing area is provided with public electrode, and said array base palte also comprises: at least one public electrode wire that is connected with said public electrode.
Wherein, said at least one public electrode wire is positioned at the viewing area of thin film transistor pixel structure, perhaps is positioned at the intersection of the adjacent thin film transistor pixel structure of two row.
Wherein, the equal correspondence of every capable thin film transistor pixel structure is provided with a said public electrode wire.
Wherein, said at least one public electrode wire is connected with said public electrode through N via hole that is positioned on the array base palte, and wherein, 2≤N≤A, A are the total columns by the multiple row thin film transistor pixel structure of data wire division.
Further, said N cross hole count at interval the same pixel columns or at interval the same pixel line number be periodic arrangement.
Wherein, The adjacent arrangement of TFT regions of adjacent two row thin film transistor pixel structures in the multirow thin film transistor pixel structure by the grid line division, said adjacent two row adjacent with the viewing area that the is adjacent capable thin film transistor pixel structure respectively arrangements in thin film transistor pixel structure viewing area separately.
Wherein, the every capable thin film transistor pixel structure of said multirow thin film transistor pixel structure is equipped with a said public electrode wire.
Wherein, the territory, two line display ranges of two row thin film transistor pixel structures of the adjacent arrangement in viewing area only is provided with a said public electrode wire, and said public electrode wire is positioned at the intersection of two row thin film transistor pixel structures of the adjacent arrangement in said viewing area.
Wherein, pixel electrode is a strip shaped electric poles in the said thin film transistor pixel structure, and said public electrode is a block type electrode, is separated with passivation layer between between said pixel electrode and the public electrode.
Wherein, said public electrode is for covering the block type electrode of whole array base palte.
Wherein, said pixel electrode is connected through through hole with the drain electrode of said thin-film transistor, around said through hole, is formed with the clearance hole of diameter greater than said through hole on the said public electrode.
Wherein, said public electrode wire and said grid line are positioned at same one deck, and parallel with grid line.
Wherein, said array base palte is the array base palte that has adopted the retina Display Technique.
The utility model also provides a kind of manufacture method of array base palte, may further comprise the steps:
S1: on substrate, form in the gate patterns of grid line figure and thin-film transistor, on substrate, form at least one public electrode line graph;
S2: after forming said grid line figure, gate patterns and public electrode line graph, form common pattern of electrodes, the pixel electrode figure on comprising thin-film transistor and being positioned at said thin-film transistor and be connected first via hole of said public electrode line graph and common pattern of electrodes.
Wherein, said step S2 specifically comprises:
Form thin-film transistor on the substrate after step S1;
Form the barrier layer successively on the substrate after forming thin-film transistor, and the zone of corresponding said public electrode line graph and the drain electrode of thin-film transistor form said first via hole and second via hole that is used to be connected drain electrode and said pixel electrode with the downward respectively etching of the join domain of said pixel electrode on said barrier layer;
The depositing electrically conductive film, and the composition technology of passing through on every side of second via hole forms clearance hole on said conductive film, to form common pattern of electrodes;
On the substrate that forms common pattern of electrodes, form insulation film and form passivation layer; And the zone passage composition technology of corresponding said second via hole forms the trepanning that passes said passivation layer on said passivation layer; The diameter of said trepanning is less than the diameter of said clearance hole, and said trepanning constitutes the through hole that is connected pixel electrode and drain electrode with said second via hole;
The depositing electrically conductive film forms the strip pixel electrode through composition technology, and pixel electrode connects drain electrode through said through hole.
Wherein, When forming the gate patterns of said grid line figure and thin-film transistor among the said step S1; Make the adjacent arrangement of area of grid of adjacent two row thin film transistor pixel structures in the multirow thin film transistor pixel structure of dividing by grid line, separately adjacent with the viewing area that the is adjacent capable thin film transistor pixel structure respectively arrangement in viewing area in the said adjacent two row thin film transistor pixel structures.
Wherein, When making said public electrode line graph; Two of adjacent arrangement row thin film transistor pixel structures are only made a said public electrode wire in the viewing area, and said public electrode wire is produced on the intersection of two row thin film transistor pixel structures of said adjacent arrangement.
The utility model also provides a kind of display unit, comprises above-mentioned each described array base palte.
(3) beneficial effect
Be provided with the public electrode wire that is connected with public electrode in the thin film transistor pixel structure of the array base palte of the utility model; Thereby greatly reduced common electrode resistance; Thereby in time the coupling effect of (SD) holding wire to public electrode leaked in the elimination source; The change in voltage that therefore can not cause public electrode, and the pressure reduction of the driving in the pixel can not produce difference, thus avoided display frame to produce the crosstalk phenomenon.
Description of drawings
Fig. 1 be in the array base palte of the prior art pixel electrode and public electrode sketch map is set;
Fig. 2 is the floor map of a kind of array base-plate structure of the utility model embodiment 1;
Fig. 3 is the schematic cross-section of the array base-plate structure among the embodiment 1;
Fig. 4 is a kind of array base-plate structure sketch map of the utility model embodiment 2;
Fig. 5 is the principle schematic that influences the array base palte pixel aperture ratio;
Fig. 6 is the principle schematic that the array base palte of embodiment 2 increases aperture opening ratio;
Fig. 7 is another principle schematic that the array base palte of embodiment 2 increases aperture opening ratio.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the embodiment of the utility model is described in further detail.Following examples are used to explain the utility model, but are not used for limiting the scope of the utility model.
The ADS type array base palte of present embodiment; As shown in Figure 2; Comprise: the some thin film transistor pixel structures 3 between grid line 1, data wire 2 and grid line 1 and the data wire 2 (each thin film transistor pixel structure is corresponding to a pixel cell); Each thin film transistor pixel structure 3 comprises thin-film transistor and viewing area; Wherein, thin-film transistor comprises grid, gate insulation layer, active layer, source electrode and drain electrode (Fig. 2 is not shown), and the viewing area refers to the zone that is used to show (corresponding to the zone at pixel electrode place) outside the thin-film transistor; Comprise pixel electrode 39 and the public electrode (Fig. 2 is not shown) that is positioned at pixel electrode 39 belows, public electrode is to be linked to be whole block public electrode on whole array base palte.This array base palte also comprises at least one public electrode wire 4 that be connected with the public electrode of thin film transistor pixel structure 3.Public electrode wire 4 runs through a plurality of pixel cells; This public electrode wire 4 can be positioned at the optional position of thin film transistor pixel structure; Particularly; Can be positioned at the viewing area (refer to be positioned at the viewing area of pixel cell but be not positioned at two row or the intersections of row adjacent unit pixel) of the pixel cell (being thin film transistor pixel structure) of delegation or row, the intersection that also can be positioned at two row (or row) adjacent unit pixel (being thin film transistor pixel structure) (comprises three kinds of situation: the viewing area that, only is positioned at the wherein one-row pixels unit of intersection; Two, be positioned at the viewing area of two row pixel cells of intersection simultaneously; Three, be positioned at intersection, but do not fall into the viewing area of any delegation of adjacent two row pixel cells), also can be positioned at other suitable positions, do not exceed with shown in Figure 2.Public electrode wire 4 is positioned at the intersection of the adjacent thin film transistor pixel structure 3 of two row among Fig. 2.
Fig. 3 be present embodiment array base-plate structure along A ' among Fig. 2-A to schematic cross-section.Comprise successively from the bottom up: grid 31, gate insulation layer 32, active layer 33, source-drain electrode 34 (comprising source electrode and drain electrode), first passivation layer 35, barrier layer 36, public electrode 37, second passivation layer 38, pixel electrode 39.In the present embodiment, public electrode wire 4 is positioned at same one deck (promptly being positioned at same one deck with grid line 1) with the grid 31 of thin-film transistor TFT, and parallel with grid line 1.Pixel electrode 39 is a strip shaped electric poles, and the through hole through passing second passivation layer 38, barrier layer 36 and first passivation layer 35 is connected with the drain electrode in the source-drain electrode 34, have on the pixel electrode 39 of strip strip hole 39 '.Wherein, this through hole comprises: pass second passivation layer 38 trepanning 5, pass the via hole 6 (also can be referred to as second via hole) of the barrier layer 36 and first passivation layer 35.Public electrode 37 is the monoblock electrode of covered substrate; For fear of contacting with pixel electrode 39; On public electrode 37 trepanning 5 around be formed with the clearance hole 7 of diameter greater than trepanning 5; Promptly, around this through hole, be formed with the clearance hole of diameter on the public electrode greater than through hole (being specially the cover bore portion of through hole) at the lead to the hole site that connects pixel electrode and drain electrode.Public electrode wire 4 is connected with public electrode 37 through the via hole 8 (also can be referred to as first via hole) that passes barrier layer 36, first passivation layer 35 and gate insulation layer 32.For public electrode wire 4 and public electrode 37 are connected in parallel to reduce the resistance of public electrode 37; Public electrode wire 4 is connected with public electrode 37 through 2 via holes 8 at least, the effect (it is the public electrode wire that public electrode provides signal that public electrode wire 4 is different from existing) that is connected in parallel with arrival.
In the present embodiment, the structure of array base palte for the usefulness of example, is not the restriction to the array base-plate structure of the utility model embodiment just.Such as, during practical application, can not comprise barrier layer 36, perhaps, public electrode 37 can barrier layer 36 and first passivation layer 35 between (at this moment, the barrier layer 36 and second passivation layer 38 can be structure as a whole); For another example, public electrode 37 can not be to be linked to be whole block public electrode yet, but in each pixel cell, independently becomes piece; Again for another example, public electrode also can be positioned at the top of pixel electrode; Again for another example, public electrode wire also can be provided with and makes with layer with grid line, but through other layer (such as the data wire metal level) or the metal level making that increases newly, or the like.The practical structures that is array base palte can change with reference to prior art according to actual needs.Certainly, the barrier layer 36 that is provided with exemplary in the present embodiment makes public electrode 37 be positioned at the top on barrier layer 36 simultaneously, can make array base palte have higher aperture opening ratio.The rete (as: barrier layer etc.) that via hole 6 among the utility model embodiment, via hole 8 etc. are passed can correspondingly be adjusted (promptly can pass more or less rete according to actual needs) when array base-plate structure changes.
Only need make at least one public electrode wire 4 that be connected with public electrode 37 when making above-mentioned array base palte gets final product.Simple for production process, the same one deck at grid line in the present embodiment manufacture method is made public electrode wire 4.
The utility model embodiment also provides a kind of ADS type manufacturing method of array base plate, according to the array base palte that this method is made, has at least one public electrode wire that be connected with public electrode.For describing conveniently, be that example describes with the ADS type array base palte of making structure shown in Figure 3 below, concrete steps are following:
On glass substrate through exposure, development, etching, peel off etc. and also to form public electrode wire 4 when a series of composition technologies form grids 31, grid line 1 figure, public electrode wire 4 also is parallel to grid line 1.Public electrode wire 4 can be positioned at the viewing area of one-row pixels unit, also can be positioned at the intersection of two row adjacent unit pixel.For the less aperture opening ratio that influences, preferably public electrode wire 4 is arranged at the intersection of two row adjacent unit pixel.
After forming the figure of grid 31, grid line 1 and public electrode wire 4, form TFT (gate insulation layer 32 except that grid 31, active layer 33, source-drain electrode 34, first passivation layer 35) and be positioned at the barrier layer 36 on the TFT through composition technology.And on barrier layer 36 figure of drain region and the public electrode wire 4 of corresponding source-drain electrode 34 the zone downwards etching form the via hole 8 that passes the via hole 6 of barrier layer 36, first passivation layer 35 and pass barrier layer 36, first passivation layer 35 and gate insulation layer 32,2 via holes 8 of etching at least.
The depositing electrically conductive film, and the drain electrode join domain of respective pixel electrode 39 and source-drain electrode 34 forms clearance hole 7 through composition technology on conductive film, to form the figure of public electrode 37;
The deposition insulation film forms second passivation layer 38 on the substrate of the figure that forms public electrode 37, and the trepanning 5 of second passivation layer 38 is passed in the zone passage composition technology formation that the drain electrode of respective pixel electrode 39 and source-drain electrode 34 is connected on second passivation layer 38.The diameter of trepanning 5 is more than or equal to via hole 6, and less than the diameter of clearance hole 7.
The depositing electrically conductive film forms strip pixel electrode 39 through composition technology, and pixel electrode is connected the drain electrode of source-drain electrode 34 with via hole 6 through trepanning 5.
Present embodiment has increased public electrode wire 4 on array base palte; And be connected with public electrode 37 through at least 2 via holes 8; Two resistance about making; Be that public electrode 37 carries out parallel connection with public electrode wire 4, thereby reduced the resistance of public electrode 37 largely, prevented that cross talk etc. is because the resistance of public electrode 37 increases the bad generation that causes.
More than, only be a kind of manufacture method of the utility model embodiment, when the concrete structure of array base palte changed, this manufacture method can be adjusted according to actual conditions.Such as, during practical application, can not make barrier layer 36, perhaps, public electrode 37 can barrier layer 36 and first passivation layer 35 between (at this moment, the barrier layer 36 and second passivation layer 38 can be structure as a whole); For another example, public electrode 37 can not be to be linked to be whole block public electrode yet, but in each pixel cell, independently becomes piece; Again for another example, public electrode also can be positioned at the top of pixel electrode; Again for another example, public electrode wire also can be provided with and makes with layer with grid line, but through other layer (such as the data wire metal level) or the metal level making that increases newly, or the like.Do not limit at this.
In order further to reduce the resistance of public electrode 37, a plurality of via holes 8 that public electrode wire 4 is connected with public electrode 37 that are used for can be set on array base palte.For example every public electrode wire 4 is connected with public electrode 37 through N via hole 8 that is positioned on the array base palte; 2≤N≤A; A is the total columns by the multiple row thin film transistor pixel structure of data wire division; In Fig. 2, the public electrode wire 4 that passes 3 pixels of every row is connected with public electrode 37 through two via holes 8.Preferably; N via hole 8 interval same pixel columns (or interval same pixel line number; When public electrode wire vertically is provided with on array base palte when parallel with data wire) be periodically arrangement; Can make public electrode 37 reach unanimity at the resistance of each pixel cell this moment, guarantees the uniformity of display frame to a certain extent.
Can on array base palte, be provided with simultaneously many and be connected public electrode wire 4 with public electrode 37, each bar public electrode wire 4 is corresponding to delegation's thin film transistor pixel structure.Because public electrode wire 4 can exert an influence to the pixel aperture ratio of whole base plate (being provided with the pixel of public electrode wire 4 and not being provided with the aperture ratio of pixels of public electrode wire 4 different); Homogeneity for the aperture opening ratio that guarantees whole array base palte; In the multirow thin film transistor pixel structure of dividing by grid line 13; Can make public electrode wire 4 at interval M (line number of the multirow thin film transistor pixel structure 3 that M representes to be divided by grid line 1, M greater than 0 less than total line number) row thin film transistor pixel structure be periodically and arrange.Preferably; Corresponding every capable thin film transistor pixel structure all is provided with a public electrode wire 4 (public electrode wire 4 can be positioned at the viewing area of this row pixel cell in the multirow thin film transistor pixel structure of being divided by grid line 13; Also can be positioned at the intersection of this row pixel cell and adjacent lines pixel cell); Make that like this homogeneity of pixel aperture ratio of whole base plate is better, and the resistance of public electrode 37 is lower.
ADS type array base palte in the present embodiment can be applied to R-ADS type array base palte, realizes that retina shows, brings better user experience.
Owing to increased some public electrode wires 4 in the array base-plate structure of embodiment 1; If use traditional ADS mode; Public electrode wire 4 need have certain distance with grid line 1, can cause it to block normal light-emitting zone like this, and the influence of pairs of openings rate is bigger; In order to improve aperture opening ratio, the array base palte of present embodiment adopts the opposed mode of TFT to be provided with.(sectional view and Fig. 3 of its each thin film transistor pixel structure are similar) as shown in Figure 4; By the adjacent arrangement of TFT regions of adjacent two row thin film transistor pixel structures 3 in some thin film transistor pixel structures 3 of grid line 1 division (being adjacent two row pixel cells), adjacent two row adjacent with the viewing area that the is adjacent capable thin film transistor pixel structure 3 respectively arrangements in thin film transistor pixel structure 3 viewing area separately.Wherein, This array base palte comprises at least one public electrode wire; Public electrode wire 4 is positioned at the intersection of the viewing area of above-mentioned adjacent arrangement, promptly is positioned at the intersection of the adjacent thin film transistor pixel structure of two row, the adjacent setting in viewing area of the thin film transistor pixel structure that this two row is adjacent.And as shown in Figure 4, the public electrode wire of the utility model embodiment is positioned at the viewing area of two row pixel cells of intersection simultaneously.For public electrode wire 4 and public electrode 37 are connected in parallel to reduce the resistance of public electrode 37; Public electrode wire 4 is connected with public electrode 37 through 2 via holes 8 at least, the effect (it is the public electrode wire that public electrode provides signal that public electrode wire 4 is different from existing) that is connected in parallel with arrival.
In order further to reduce the resistance of public electrode 37, a plurality of via holes 8 that public electrode wire 4 is connected with public electrode 37 that are used for can be set on array base palte.For example every public electrode wire 4 is connected with public electrode 37 through N via hole 8 that is positioned on the array base palte; Total columns of the multiple row thin film transistor pixel structure of 2≤N≤divide by data wire; In Fig. 4, the public electrode wire 4 that passes 3 pixels of every row is connected with public electrode 37 through two via holes 8.Preferably, N via hole 8 periodically arrangement of same pixel columns one-tenth at interval, can make public electrode 37 reach unanimity at the resistance of each pixel cell this moment, guarantees the uniformity of display frame to a certain extent.
Can on array base palte, be provided with simultaneously many and be connected public electrode wire 4 with public electrode 37; Because public electrode wire 4 can exert an influence to the pixel aperture ratio of whole base plate (being provided with the pixel of public electrode wire 4 and not being provided with the aperture ratio of pixels of public electrode wire 4 different); Homogeneity for the aperture opening ratio that guarantees whole array base palte; In the multirow thin film transistor pixel structure of dividing by grid line 13; Can make public electrode wire 4 at interval M (line number of the multirow thin film transistor pixel structure 3 that M representes to be divided by grid line 1, M greater than 0 less than total line number) row pixel cell be periodically and arrange.Preferably; In the multirow thin film transistor pixel structure of dividing by grid line 13; Intersection in the viewing area of each above-mentioned adjacent arrangement all is provided with a public electrode wire 4, make that like this homogeneity of pixel aperture ratio of whole base plate is better, and the resistance of public electrode 37 is littler.Two viewing areas of two row thin film transistor pixel structures 3 of the adjacent arrangement in viewing area only are provided with a public electrode wire 4; The two row thin film transistor pixel structures 3 that are the adjacent arrangement in viewing area can a shared public electrode wire 4, and are less to the aperture ratio of pixels influence like this.
Two zones " adjacent arrangement " among each embodiment of the utility model refer in the middle of these two zones except grid line, perhaps except grid line and public electrode wire, and interval miscellaneous part no longer; Such as the adjacent arrangement of TFT regions of adjacent two row pixel cells, only refer in the middle of the TFT regions of adjacent two row pixel cells at interval grid line, perhaps only grid line and public electrode wire at interval, not miscellaneous part such as spaced pixels electrode; The adjacent setting in viewing area of the adjacent thin film transistor pixel structure of two row, the viewing area that is meant the thin film transistor pixel structure that two row are adjacent be grid line at interval only, perhaps only grid line and public electrode wire at interval, not miscellaneous part such as interval film transistor.
Thin film transistor pixel structure 3 in the present embodiment is similar with the thin film transistor pixel structure 3 among the embodiment 1, repeats no more here.
The manufacture method of the array base palte of the manufacture method of the array base palte of present embodiment and embodiment 1 is basic identical; Different is on glass substrate through exposure, development, etching, the adjacent arrangement of area of grid that makes the thin-film transistor of adjacent two row thin film transistor pixel structures in the multirow thin film transistor pixel structure of being divided by grid line 1 (pixel cell) when a series of composition technologies form the figure of grid 31, grid line 1 figure and public electrode wires 4 such as peel off, separately adjacent with the viewing area that the is adjacent capable thin film transistor pixel structure respectively arrangement in viewing area in the adjacent two row thin film transistor pixel structures.And can between the adjacent viewing area of two whenever adjacent row thin film transistor pixel structures, make a public electrode wire 4.The making step and the embodiment 1 of grid 31, grid line 1 figure and public electrode wire 4 upper layers level structures are similar, repeat no more here.
As shown in Figure 5; Pixel aperture ratio can receive following factor affecting: a to represent that the width of public electrode wire 4, b represent black matrix (Black Matrix, width BM) that prevents that gate line top light leak from using; C representes the grid line width, and d representes to prevent the width of the BM that grid line below light leak is used.As shown in Figure 6, adopt the opposed mode of TFT to arrange, two pixels only need the width of a d to prevent grid line below light leak, and each pixel has been saved the BM width of d/2, improve about 3% with respect to the pixel aperture ratio of the array base palte of embodiment 1.The 2a width of public electrode wire 4 also has the space that reduces in addition.Simultaneously the utility model will be up and down TFT between two pixels partly take relative mode; Effectively utilized redundant space; And chock insulator matter is arranged on this position, and need not to increase extra BM area, to prevent that the chock insulator matter skew from causing bad, thereby increased aperture opening ratio.And the ADS product so single pixel B M width is narrower, is placed after the chock insulator matter because aperture opening ratio limits so at present; Because the possible offset of chock insulator matter forms the orientation blind area in non-BM zone easily, this causes the basic reason of contrast decline and various ghosts just; Have a strong impact on yield, and take the relative mode of TFT, the BM of two pixels is combined in a place; Chock insulator matter has been placed with very big space, under the situation that does not reduce aperture opening ratio, has guaranteed product quality.
And, in the dot structure of the via hole that has barrier layer (being generally resin material), because via hole is very dark; Include more liquid crystal; These liquid crystal differ greatly with the thickness of liquid crystal of normal viewing area, and are as shown in Figure 7, via hole to the distance from top h2 of liquid crystal layer 9 greater than the thick h1 of liquid crystal cell; Cause liquid crystal aligning difference, formed serious light leak; Simultaneously, be coated with electrode on the via hole, the electrode here also is not parallel to glass, but is layered on the hole wall angle of gradient α that forms wide-angle with glass, can influence peripheral liquid crystal aligning; And via area has very strong interference to the electric field of normal viewing area, has had a strong impact on normal demonstration, if use extra BM to block, and the one, reduced aperture opening ratio, the 2nd, still can cause the hidden danger of quality.And the relative design of employing TFT; The via area of two pixels is up and down put together; With the distance that normal viewing area has had the width of grid line and BM to produce, avoid its influence to normal viewing area, improve aperture opening ratio and reduced and produced bad risk.
ADS type array base palte in the present embodiment can be applied to R-ADS type array base palte, realizes that retina shows, to bring better user experience.
The display unit of array base palte in a kind of embodiment of comprising 1 or 2 is provided in the present embodiment, and this display unit can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, LCD, DPF, mobile phone, panel computer.
Above execution mode only is used to explain the utility model; And be not the restriction to the utility model; The those of ordinary skill in relevant technologies field under the situation of spirit that does not break away from the utility model and scope, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to the category of the utility model, and the scope of patent protection of the utility model should be defined by the claims.
Claims (14)
1. array base palte; Comprise some grid lines, data wire that is formed on the substrate and the some thin film transistor pixel structures that between said grid line and data wire, form; Said thin film transistor pixel structure comprises thin-film transistor and viewing area; Said viewing area is provided with public electrode, it is characterized in that, said array base palte also comprises: at least one public electrode wire that is connected with said public electrode.
2. array base palte as claimed in claim 1 is characterized in that said at least one public electrode wire is positioned at the viewing area of thin film transistor pixel structure, perhaps is positioned at the intersection of the adjacent thin film transistor pixel structure of two row.
3. array base palte as claimed in claim 1 is characterized in that, the equal correspondence of every capable thin film transistor pixel structure is provided with a said public electrode wire.
4. array base palte as claimed in claim 1; It is characterized in that said at least one public electrode wire is connected with said public electrode through N via hole that is positioned on the array base palte, wherein; 2≤N≤A, A are the total columns by the multiple row thin film transistor pixel structure of data wire division.
5. array base palte as claimed in claim 4 is characterized in that, said N cross hole count at interval the same pixel columns or at interval the same pixel line number be periodic arrangement.
6. array base palte as claimed in claim 1; It is characterized in that; The adjacent arrangement of TFT regions of adjacent two row thin film transistor pixel structures in the multirow thin film transistor pixel structure by the grid line division, said adjacent two row adjacent with the viewing area that the is adjacent capable thin film transistor pixel structure respectively arrangements in thin film transistor pixel structure viewing area separately.
7. array base palte as claimed in claim 6 is characterized in that, the every capable thin film transistor pixel structure of said multirow thin film transistor pixel structure is equipped with a said public electrode wire.
8. array base palte as claimed in claim 6; It is characterized in that; The territory, two line display ranges of two row thin film transistor pixel structures of the adjacent arrangement in viewing area only is provided with a said public electrode wire, and said public electrode wire is positioned at the intersection of two row thin film transistor pixel structures of the adjacent arrangement in said viewing area.
9. like each described array base palte in the claim 1～8, it is characterized in that pixel electrode is a strip shaped electric poles in the said thin film transistor pixel structure, said public electrode is a block type electrode, is separated with passivation layer between between said pixel electrode and the public electrode.
10. array base palte as claimed in claim 9 is characterized in that, said public electrode is for covering the block type electrode of whole array base palte.
11. array base palte as claimed in claim 10 is characterized in that, said pixel electrode is connected through through hole with the drain electrode of said thin-film transistor, around said through hole, is formed with the clearance hole of diameter greater than said through hole on the said public electrode.
12. array base palte as claimed in claim 9 is characterized in that, said public electrode wire and said grid line are positioned at same one deck, and parallel with grid line.
13., it is characterized in that said array base palte is the array base palte that has adopted the retina Display Technique like each described array base palte in the claim 1～8.
14. a display unit is characterized in that, comprises like each described array base palte in the claim 1～13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220143323 CN202633310U (en) | 2012-04-06 | 2012-04-06 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220143323 CN202633310U (en) | 2012-04-06 | 2012-04-06 | Array substrate and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013149467A1 (en) * | 2012-04-06 | 2013-10-10 | 北京京东方光电科技有限公司 | Array substrate, and manufacturing method thereof and display device |
| TWI548921B (en) * | 2015-02-12 | 2016-09-11 | 群創光電股份有限公司 | Display panel |
| CN111200914A (en) * | 2018-11-20 | 2020-05-26 | 群创光电股份有限公司 | Electronic device and splicing electronic system with same |
-
2012
- 2012-04-06 CN CN 201220143323 patent/CN202633310U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013149467A1 (en) * | 2012-04-06 | 2013-10-10 | 北京京东方光电科技有限公司 | Array substrate, and manufacturing method thereof and display device |
| TWI548921B (en) * | 2015-02-12 | 2016-09-11 | 群創光電股份有限公司 | Display panel |
| CN111200914A (en) * | 2018-11-20 | 2020-05-26 | 群创光电股份有限公司 | Electronic device and splicing electronic system with same |
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