CN103926768A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN103926768A CN103926768A CN201310589624.7A CN201310589624A CN103926768A CN 103926768 A CN103926768 A CN 103926768A CN 201310589624 A CN201310589624 A CN 201310589624A CN 103926768 A CN103926768 A CN 103926768A
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Abstract
The invention discloses an array substrate with an aim to solve the problem about horizontal cross grains in the process of image displaying. The array substrate comprises a substrate, grid lines and a sub-pixel unit array, wherein the grid lines and the sub-pixel unit array are formed on the substrate. Each sub-pixel unit comprises a TFT (thin film transistor) and a public electrode, every two adjacent rows of sub-pixel units constitute a sub-pixel unit group, and two grid lines are arranged between the two rows of sub-pixel units of the sub-pixel unit group; gate electrodes of the TFTs of the last row of sub-pixel units in the sub-pixel unit group and gate electrodes of the TFTs of the next row of sub-pixel units are arranged between the two grid lines and staggered, the gate electrodes of the TFTs are arranged on the same sides of respective sub-pixel units, and the two rows of sub-pixel units of the sub-pixel unit groups are staggered by the width smaller than one sub-pixel unit along the direction of the grid lines. The invention further discloses a display panel and a display device.
Description
Technical field
The present invention relates to demonstration field, relate in particular to a kind of array base palte and the display panel that comprises this array base palte and display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) comprises array base palte, color membrane substrates and the liquid crystal layer between the two.In order to obtain better display effect, the target that each producer of the target that high aperture is is pursued.
Referring to Fig. 1, it is a kind of array base palte of high aperture.Comprise grid line arranged in a crossed manner 101 and data line 102, public electrode wire 103 and enclose by data line 102 and grid line 101 the sub-pix unit (Fig. 1 only illustrates two the sub-pix unit up and down in adjacent two row sub-pix unit) forming, each sub-pix unit comprises a TFT104 and a pixel electrode 105; Adjacent two row grid lines 101 are between adjacent two row sub-pix unit, and the grid that is positioned at the TFT of same row in these adjacent two row sub-pix unit interlocks in opposite directions, and two row sub-pix unit are separated by between adjacent two row public electrode wires 103.
But array base palte as shown in Figure 1, each pixel complete matching, while showing, there is horizontal band phenomenon in image.
Summary of the invention
The object of this invention is to provide a kind of array base palte, display panel and display device, to solve the problem that has horizontal band in image display process.
The object of the invention is to be achieved through the following technical solutions:
The embodiment of the present invention provides a kind of array base palte, comprise substrate, be formed at grid line and sub-pix cell array on substrate, each sub-pix unit comprises TFT and public electrode, take sub-pix unit described in every two adjacent row is a sub-pix unit group, between sub-pix unit, two grid lines is set described in two row of described sub-pix unit group; The gate electrode of the gate electrode of the described TFT of the lastrow sub-pix unit in described sub-pix unit group and the described TFT of next line sub-pix unit is all between described two grid lines and be crisscross arranged, and described in each, gate electrode of TFT is all positioned at the homonymy of described sub-pix unit separately.
Described in two row of described sub-pix unit group, sub-pix unit staggers each other and is less than the width of a sub-pix unit along described grid line direction.
Embodiment of the present invention beneficial effect is as follows: described in each, the gate electrode of TFT is all positioned at the homonymy of described sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thus the horizontal band while reducing image demonstration.
The embodiment of the present invention provides a kind of display panel, comprises the color membrane substrates and the array base palte that are oppositely arranged, the array base palte that described array base palte provides for above-described embodiment.
Embodiment of the present invention beneficial effect is as follows: the array base palte that display panel adopts, by making the gate electrode of the TFT of sub-pix unit all be positioned at the homonymy of sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thereby reduce the horizontal band of display panel when showing image; Further, the overlapping region of the public electrode wire arranging on array base palte and data line has opening, thereby reduces the two overlapping formed stray capacitance, improves the display effect of display panel.
The embodiment of the present invention provides a kind of display device, comprises the described display panel that above-described embodiment provides.
Embodiment of the present invention beneficial effect is as follows: the array base palte that display panel adopts, by making the gate electrode of the TFT of sub-pix unit all be positioned at the homonymy of sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thereby reduce the horizontal band of display panel when showing image; Further, the overlapping region of the public electrode wire arranging on array base palte and data line has opening, thereby reduces the two overlapping formed stray capacitance, improves the display effect of display panel.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte described in prior art;
The structural representation of the array base palte that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is that array base palte shown in embodiment of the present invention Fig. 2 is at the schematic cross-section at AA place;
Fig. 4 is that array base palte shown in embodiment of the present invention Fig. 2 is at the schematic cross-section at BB place;
The structural representation of the public electrode wire of the array base palte that Fig. 5 provides for the embodiment of the present invention;
The structural representation of the display panel that Fig. 6 provides for the embodiment of the present invention;
The structural representation of the first display device that Fig. 7 provides for the embodiment of the present invention;
The structural representation of the second display device that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description, the implementation procedure of the embodiment of the present invention is elaborated.It should be noted that same or similar label from start to finish represents same or similar element or has the element of identical or similar functions.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Referring to Fig. 2, the embodiment of the present invention provides a kind of array base palte, comprises substrate 1, is formed at grid line 2 and sub-pix cell array on substrate 1, and each sub-pix unit comprises TFT3.Referring to Fig. 3, show array base palte shown in Fig. 2 at the schematic cross-section at AA place, each sub-pix unit also comprises pixel electrode 8 and public electrode 4, public electrode 4 is comb teeth-shaped structure (conventionally, comprising a plurality of strip shaped electric poles and slit); On substrate 1, be also provided with data line 5 simultaneously.Between data line 5 place layers and public electrode, passivation layer 9 is set.Referring to Fig. 4, show array base palte shown in Fig. 2 at the schematic cross-section at BB place, TFT3 comprises gate electrode 31, source electrode 32 and drain electrode 33; And gate insulation layer 10, active layer 11, gate insulation layer 10 is arranged between gate electrode 31 and active layer 11, active layer 11 is arranged at the exhausted layer 10 of grid and source electrode 32, is arranged between the exhausted layer 10 of grid and drain electrode 33, source electrode 32 and drain electrode 33 arrange with layer, and source electrode 32 directly contacts with pixel electrode 8.It should be noted that, Fig. 3 and Fig. 4 are a kind of structure of common sub-pix unit, and in other embodiments of the invention, sub-pix unit can also adopt other structures, as pixel electrode is positioned on public electrode; Public electrode is cover data line, TFT not, and public electrode also can not cover grid line; TFT can be also top gate structure etc.; No longer repeat to set forth.
As shown in Figure 2, in the present embodiment, sub-pix cell array arrangement mode is as follows: take every two adjacent row sub-pix unit is a sub-pix unit group, between two row sub-pix unit of sub-pix unit group, two grid lines 2 are set, the gate electrode of the TFT3 of every a line sub-pix unit and the corresponding electrical connection of a grid line 2 in two grid lines 2; Preferably, two grid lines 2 are electrically connected to a line sub-pix unit close in two row sub-pix unit respectively.The gate electrode 31 of the gate electrode 31 of the TFT3 of the lastrow sub-pix unit in sub-pix unit group and the TFT3 of next line sub-pix unit is all between two grid lines 2 and be crisscross arranged, specifically the gate electrode 31 of certain TFT3 of the lastrow sub-pix unit in sub-pix unit group is between the gate electrode 31 of two adjacent TFT3 of next line sub-pix unit, and the gate electrode 31 of certain TFT3 of the next line sub-pix unit in sub-pix unit group is between the gate electrode 31 of two adjacent TFT3 of lastrow sub-pix unit.In addition, the gate electrode 31 of each TFT3 is all positioned at the homonymy of sub-pix unit separately, and as shown in Figure 2, the gate electrode 31 of each TFT3 is all positioned at the left side of sub-pix unit separately.
Two row sub-pix unit of sub-pix unit group stagger each other and are less than the width of a sub-pix unit along grid line 2 directions.Based on sub-pix unit arrange and preferably display effect consider, preferably, next line sub-pix unit in sub-pix unit group has the transversal displacement of the width of the gate electrode 31 that is more than or equal to a TFT3 with respect to lastrow sub-pix unit, and transversal displacement is less than or equal to width poor of the width of a sub-pix unit and the gate electrode 31 of a TFT3.
In the above-mentioned sub-pix cell array side of arranging, data line 5 is electrically connected to a row sub-pix unit, and each data line 5 is arranged in the same side (Fig. 2, the data line bit of take is example in the left side of the sub-pix unit being electrically connected to it) of the sub-pix unit being electrically connected to it.
In the embodiment of the present invention, the setting that interlocks of the gate electrode 31 of the TFT3 of adjacent two row sub-pix unit, can guarantee the aperture opening ratio of sub-pix unit; When guaranteeing the aperture opening ratio of sub-pix unit, the sub-pix unit of adjacent lines staggers each other, effectively reduces the horizontal band while showing.
Data line 5 as shown in Figure 2 and public electrode 6.Wherein, data line 5 comprises the first broken line 51, and this first broken line 51 is overlapping with public electrode wire 6.Public electrode wire 6 is arranged between adjacent sub-pix unit group, can with layer, arrange with gate electrode 31 and grid line 2; Public electrode wire 6 via hole 7 by top and public electrode 4(public electrode 4 are as shown in Figure 3) be electrically connected to.
Referring to Fig. 5, show the structural representation of public electrode wire 6, it has opening 61, and this opening 61 is corresponding with the first broken line 51 of data line 5, and its corresponding relation is as shown in Figure 2.The figure of opening 61 can be arbitrary graphic, preferred, and the length that this opening 61 is gone up is in the row direction greater than the length that the first broken line 51 of data line 5 is gone up in the row direction.; opening 61 meets following condition: the vertical projection of the first broken line 51 of data line 5 falls within the vertical projection of this opening 61; thereby make this first broken line 51 of data line 5 and this open area of public electrode wire 6 without overlapping part, reduce data line 5 and the overlapping formed stray capacitance of public electrode wire 6.
As shown in Figure 2, data line 5 also comprises that the second broken line 52, the second broken lines 52 are arranged between two grid lines 2, thereby is electrically connected to the drain electrode 33 of sub-pix unit.
Embodiment of the present invention beneficial effect is as follows: by making the gate electrode of the TFT of sub-pix unit all be positioned at the homonymy of sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thus the horizontal band while reducing image demonstration; Further, the overlapping region of public electrode wire and data line has opening, thereby reduces the two overlapping formed stray capacitance, improves display effect.
Referring to Fig. 6, the embodiment of the present invention provides a kind of display panel, comprises the color membrane substrates 201 and the array base palte 202 that are oppositely arranged, and the array base palte that array base palte 202 provides for above-described embodiment arranges liquid crystal layer 203 between color membrane substrates 201 and array base palte 202.Certainly can also comprise the assembly that other are necessary, as frame 205, sealed plastic box 204 etc., at this, not exemplify one by one.
The display panel that the present embodiment provides, can be used as any parts with the product of Presentation Function such as display panels, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Embodiment of the present invention beneficial effect is as follows: the array base palte that display panel adopts, by making the gate electrode of the TFT of sub-pix unit all be positioned at the homonymy of sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thereby reduce the horizontal band of display panel when showing image; Further, the overlapping region of the public electrode wire arranging on array base palte and data line has opening, thereby reduces the two overlapping formed stray capacitance, improves the display effect of display panel.
The embodiment of the present invention provides a kind of display device, comprises the display panel that above-described embodiment provides.
The display device that the present embodiment provides can be any products with Presentation Function such as display panels, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.For example, display 300 shown in Figure 7, comprises display panel 301; Again for example, mobile phone 400 shown in Figure 8, comprises display panel 401.
Embodiment of the present invention beneficial effect is as follows: the array base palte that display panel adopts, by making the gate electrode of the TFT of sub-pix unit all be positioned at the homonymy of sub-pix unit separately, and the grid of the TFT of the sub-pix unit of adjacent lines forms phase buckle structure, adjacent two row sub-pix unit stagger each other and are less than the width of a sub-pix unit along described grid line direction, thereby reduce the horizontal band of display panel when showing image; Further, the overlapping region of the public electrode wire arranging on array base palte and data line has opening, thereby reduces the two overlapping formed stray capacitance, improves the display effect of display panel.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (10)
1. an array base palte, comprise substrate, be formed at grid line and sub-pix cell array on substrate, each sub-pix unit comprises TFT and public electrode, take sub-pix unit described in every two adjacent row is a sub-pix unit group, between sub-pix unit, two grid lines is set described in two row of described sub-pix unit group; It is characterized in that:
The gate electrode of the gate electrode of the described TFT of the lastrow sub-pix unit in described sub-pix unit group and the described TFT of next line sub-pix unit is all between described two grid lines and be crisscross arranged, and described in each, gate electrode of TFT is all positioned at the homonymy of described sub-pix unit separately;
Described in two row of described sub-pix unit group, sub-pix unit staggers each other and is less than the width of a sub-pix unit along described grid line direction.
2. array base palte as claimed in claim 1, is characterized in that, also comprises data line and public electrode wire;
Described data line comprises the first broken line, and described the first broken line and described public electrode wire are overlapping;
Described public electrode wire is arranged between adjacent described sub-pix unit group, by via hole, is electrically connected to described public electrode, and described public electrode wire has the opening corresponding with described first broken line of described data line.
3. array base palte as claimed in claim 2, is characterized in that, described in one data line and one row described sub-pix unit be electrically connected to, and described in each data line bit in the same side of the described sub-pix unit being electrically connected to it.
4. array base palte as claimed in claim 2, is characterized in that, the length that the described opening of described public electrode wire is gone up is in the row direction greater than the length that described first broken line of described data line is gone up in the row direction.
5. array base palte as claimed in claim 2 or claim 3, is characterized in that, described data line also comprises the second broken line, and described the second broken line is arranged between described two grid lines.
6. array base palte as claimed in claim 1, is characterized in that, in described sub-pix unit group, and the gate electrode of the described TFT of sub-pix unit and the corresponding electrical connection of a described grid line in described two grid lines described in every a line.
7. array base palte as claimed in claim 1, it is characterized in that, described next line sub-pix unit in described sub-pix unit group has the transversal displacement of the width of the gate electrode that is more than or equal to a described TFT with respect to described lastrow sub-pix unit, and described transversal displacement is less than or equal to width poor of the width of described sub-pix unit and the gate electrode of a described TFT.
8. array base palte as claimed in claim 1, is characterized in that, the pixel electrode of described sub-pix unit and the source electrode of described TFT directly contact.
9. a display panel, comprises the color membrane substrates and the array base palte that are oppositely arranged, it is characterized in that, described array base palte is the array base palte described in claim 1 to 8 any one.
10. a display device, is characterized in that, comprises display panel as claimed in claim 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310589624.7A CN103926768B (en) | 2013-11-20 | 2013-11-20 | A kind of array base palte, display floater and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310589624.7A CN103926768B (en) | 2013-11-20 | 2013-11-20 | A kind of array base palte, display floater and display device |
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| CN103926768A true CN103926768A (en) | 2014-07-16 |
| CN103926768B CN103926768B (en) | 2016-09-07 |
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| CN104483788A (en) * | 2014-10-10 | 2015-04-01 | 上海中航光电子有限公司 | Pixel structure and manufacturing method thereof, array substrate, display panel and display device |
| CN106502474A (en) * | 2017-01-12 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of array base palte and display floater |
| CN107085335A (en) * | 2017-04-20 | 2017-08-22 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof |
| CN108269503A (en) * | 2018-03-26 | 2018-07-10 | 上海天马微电子有限公司 | A kind of display panel and display device |
| WO2019071813A1 (en) * | 2017-10-12 | 2019-04-18 | 惠科股份有限公司 | Array substrate and display device with same |
| WO2021196089A1 (en) * | 2020-04-01 | 2021-10-07 | 京东方科技集团股份有限公司 | Array substrate, and display device |
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| CN104483788A (en) * | 2014-10-10 | 2015-04-01 | 上海中航光电子有限公司 | Pixel structure and manufacturing method thereof, array substrate, display panel and display device |
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| CN107085335A (en) * | 2017-04-20 | 2017-08-22 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof |
| WO2019071813A1 (en) * | 2017-10-12 | 2019-04-18 | 惠科股份有限公司 | Array substrate and display device with same |
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| CN108269503A (en) * | 2018-03-26 | 2018-07-10 | 上海天马微电子有限公司 | A kind of display panel and display device |
| WO2021196089A1 (en) * | 2020-04-01 | 2021-10-07 | 京东方科技集团股份有限公司 | Array substrate, and display device |
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| CN103926768B (en) | 2016-09-07 |
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