KR101167202B1 - Mos transistor and cmos inverter, and method for manufacturing the same - Google Patents

Abstract

The present invention provides a MOS transistor and a method of manufacturing the same, which can reduce the height of the device while simplifying the process without an additional process, and using the same, a CMOS inverter and its fabrication capable of reducing the overall size by reducing the formation area of the CMOS inverter To provide a method, the present invention provides a trench formed in a substrate, a device isolation layer formed so as to fill the upper and lower portions of the trench, a common gate electrode formed so as to fill the trench between the device isolation layer, the common gate electrode and A MOS transistor comprising a gate oxide film formed between the inner sidewalls of the trench, a junction region formed in the substrate exposed to one side of the device isolation layer, a trench formed in the substrate, and a first formed in the substrate bordering the trench And a second conductivity type well and upper and lower portions of the trench A device isolation film formed to lip, a common gate electrode formed to fill the trench between the device isolation film, a gate oxide film formed between the common gate electrode and an inner wall of the trench, and the substrate exposed to both sides of the device isolation film Provided is a CMOS inverter including first and second conductivity type junction regions formed therein.

MOS transistors, CMOS inverters, trenches, common gate

Description

MOS transistor and CMOS inverter and its manufacturing method {MOS TRANSISTOR AND CMOS INVERTER, AND METHOD FOR MANUFACTURING THE SAME}

1 is a circuit diagram of a general CMOS inverter.

2 is a plan view of the CMOS inverter shown in FIG.

3 is a plan view of a CMOS inverter according to an embodiment of the present invention;

4 is an orthogonal view taken along the line II ′ of FIG. 3;

5A to 5F are process perspective views illustrating a method of manufacturing the CMOS inverter shown in FIG. 4.

<Explanation of symbols for the main parts of the drawings>

110: substrate

111: trench

112: gate oxide film

113: device isolation layer

114: common gate electrode

115a, 115b: source and drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a MOS transistor, a manufacturing method thereof, a CMOS inverter using the same, and a manufacturing method thereof.

Since the Very Large Scale Integrated Circuit (VLSI) has dramatically increased its density, a standard functional circuit block, which is often used in integrated circuit design, is registered as a standard cell, and a complex using a registered standard cell is used. It is common to design logic circuits to implement layout design of the entire integrated circuit.

A standard cell consists of a combination of logic gates, such as a NAND GATE circuit or a NOR GATE circuit, but the basic cell of the logic gate is an inverter. Among these inverters, CMOS inverters have the advantage of low power consumption, and therefore, CMOS inverters are widely used as basic cells in standard cells.

1 is a circuit diagram of a CMOS inverter consisting of a PMOS transistor (PMOS) and an NMOS transistor (NMOS), in which each gate of the PMOS and NMOS transistors (PMOS, NMOS) receives a common input signal Vin and is connected in common. The output signal Vout inverting the input signal Vin is output to the drain of the PMOS transistor PMOS and the drain of the NMOS transistor NMOS.

The layout of the CMOS inverter shown in FIG. 1 is shown in FIG. FIG. 2 shows a planar structure of a CMOS inverter according to the prior art, wherein a power supply wiring 11 for supplying a power supply voltage VDD is connected to a source of a PMOS transistor (PMOS) via a first contact 12. The ground wiring 13 for supplying the ground voltage VSS is connected to the source of the NMOS transistor NMOS via the second contact 14. The output signal line 15 for outputting the output signal Vout from the CMOS inverter. ) Is connected to the drain of the PMOS transistor (PMOS) via a third contact 16, and is connected to the drain of the NMOS transistor (NMOS) via a fourth contact 17. An input signal (C) is connected to the CMOS inverter. The input signal line 18 for inputting Vin is connected to a gate electrode 19 of a PMOS transistor (PMOS) via a fifth contact 20, and is connected to a gate electrode 21 of an NMOS transistor (NMOS). It is connected via the contact 22.

However, the CMOS inverter according to the related art requires a certain area to independently form the PMOS and NMOS transistors, and further has a trench structure through a shallow trench isolation (STI) process for device isolation between the PMOS and NMOS transistors. As the device isolation film having a structure is formed, the area is increased by that amount, thereby increasing the overall size. In addition, a wiring process for commonly connecting the gate electrodes of the PMOS and NMOS transistors, which should be used as an input terminal to which an input signal is input, is required.

Accordingly, an object of the present invention is to provide a MOS transistor and a method of manufacturing the same, which are designed to solve the above-mentioned problems of the prior art and can reduce the height of a device while simplifying the process without an additional process.

It is also an object of the present invention to provide a CMOS inverter and a method of manufacturing the same, which can reduce the overall size by reducing the formation area of the CMOS inverter while simplifying the process without additional processing.

According to an aspect of the present invention, a trench formed in a substrate, an isolation layer formed to fill upper and lower portions of the trench, a common gate electrode formed so as to fill the trench between the isolation layer, and A MOS transistor includes a gate oxide layer formed between a common gate electrode and an inner sidewall of the trench, and a junction region formed in the substrate exposed to one side of the device isolation layer.

According to another aspect of the present invention, a trench formed in a substrate, first and second conductivity type wells formed in the substrate bordering the trench, and upper and lower portions of the trench are formed to be buried. A common gate electrode formed to fill the trench between the device isolation layer and the device isolation layer, a gate oxide film formed between the common gate electrode and the inner sidewall of the trench, and a second electrode formed in the substrate exposed to both sides of the device isolation layer. A CMOS inverter comprising a first and a second conductivity type junction region is provided.

In addition, the present invention according to another aspect for achieving the above object, forming a trench in the substrate, forming a gate oxide film on the inner wall of the trench, and the device isolation film so that the upper and lower portions of the trench are buried Forming a gate electrode so as to fill the trench between the device isolation layer, and forming a junction region in the substrate exposed to one side of the device isolation layer. do.

In addition, the present invention according to another aspect for achieving the above object, forming a trench in the substrate, forming a gate oxide film on the inner wall of the trench, and the device isolation film so that the upper and lower portions of the trench are buried Forming a common gate electrode so as to fill the trench between the device isolation layer, and forming first and second conductivity type junction regions in the substrate exposed to both sides of the device isolation layer. It provides a method of manufacturing a CMOS inverter comprising.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

FIG. 3 is a plan view of a CMOS inverter according to an exemplary embodiment of the present invention, and FIG. 4 is an orthogonal view taken along the line II ′ of FIG. 3. For convenience of description, FIG. 4 shows contacts 116a to 116d connected to an external signal line (not shown) for inputting / outputting a power supply voltage VDD, a ground voltage VSS, an input signal Vin, and an output signal Vout. Not shown.

3 and 4, a CMOS inverter according to an embodiment of the present invention shares a common gate electrode 114 in which a PMOS and an NMOS transistor are embedded in a substrate 110 in a trench structure, and a source and The drain regions 115a and 115b are separated from each other at the boundary of the device isolation layer 113 and have a structure in which p-channels or n-channels are formed in the extending direction of the common gate electrode 114.

The common gate electrode 114 is embedded in the substrate 110 in a trench structure, and is separated from the substrate 110 through the gate insulating layer 112 formed on the inner surface of the trench. In addition, the device isolation layer 113 may be formed by filling a trench in communication with a trench formed by filling the common gate electrode 114, and forming an p-channel of a PMOS transistor. P-wells for forming n-channels of NMOS transistors are separated from each other. Source and drain regions 115a and 115b of the PMOS and NMOS transistors are formed on the left and right sides of the device isolation layer 113, respectively, and the channel ch of each of the PMOS and NMOS transistors is formed on the inner wall of the trench. 114 is formed in the stretched direction.

As shown in Figure 3 and 4, the CMOS inverter according to the embodiment of the present invention can obtain the following advantages.

First, by using the gate electrodes of the PMOS and NMOS transistors jointly, the number of gate electrodes can be reduced by one compared with the prior art, thereby reducing the size of the overall device.

In addition, the device isolation layer 113 may be formed above and below the common gate electrode to separate the PMOS and NMOS transistors, thereby reducing the size of the device isolation layer as compared with the related art.

In addition, the height of the device may be reduced by filling the common gate electrode 114 in a trench structure.

In addition, since the common gate electrode 114 is formed, a wiring process for connecting the gate electrodes of the PMOS and NMOS transistors, as in the related art, is unnecessary, and thus the process can be simplified.

Hereinafter, a method of manufacturing a CMOS inverter according to an exemplary embodiment of the present invention shown in FIGS. 3 and 4 will be described with reference to FIGS. 5A to 5F. 5A to 5F are cross-sectional views of the process.

First, as shown in FIG. 5A, a trench trench (STI) process is performed to form a trench 111 in the substrate 110. In this case, the trench 111 is formed in a vertically communicated structure, the upper and lower portions define a region in which the device isolation layer is to be formed through a subsequent process, and a region in which the gate electrode is to be formed in the center portion therebetween.

Subsequently, as illustrated in FIG. 5B, an oxidation process is performed to form the gate oxide film 112 along the inner surface of the trench 111. At this time, the gate oxide film 112 is formed of a SiO ₂ film.

Subsequently, as illustrated in FIG. 5C, the gate oxide layer 112 formed on portions other than the region (ie, the channel region) in which the common gate electrode is to be formed is selectively removed by performing a photo process and an etching process. Here, the gate oxide film 112 may not be removed.

Subsequently, as shown in FIG. 5D, an insulating film for an isolation layer, for example, a high density plasma film (HDP) having excellent embedding characteristics, is deposited in the trench 111 so that portions other than the region where the common gate electrode is to be formed are selectively buried. Thereafter, the device isolation layer 113 is formed on the upper and lower sides by planarization by a chemical mechanical poloshing (CMP) process.

Subsequently, as illustrated in FIG. 5E, a conductive film such as a polysilicon film is deposited to fill the trench 111 between the device isolation layers 113, and then planarized by a CMP process to form a common gate electrode 114. At this time, the polysilicon film is formed of an undoped or doped polysilicon film. For example, it is formed using SiH ₄ (undoped) or SiH ₄ and PH ₃ (dope) by LPCVD (Low Pressure Chemical Vapor Deposition) method.

 Subsequently, as illustrated in FIG. 5F, a well ion implantation process is performed in each of the substrates 110 separated from the left and right by the trench 111 as an N-well and a P-well. P-Well).

Subsequently, source and drain regions 115a and 115b are formed in the left and right N-wells and the P-wells P-W, respectively, at the boundary of the device isolation layer 113. For example, the P + source and drain regions 115a are formed in the N-well, and the N + source and drain regions 115b are formed in the P-well.

Next, as shown in FIG. 3, an interlayer dielectric layer (ILD) (not shown) is deposited to cover the completed substrate 110 to the source and drain regions 115a and 115b. In this case, the interlayer insulating film is formed by using any one of insulating films, such as BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), and SOG (Spin On Glass).

Subsequently, the interlayer insulating layer is etched to form contact holes (not shown) to expose the common gate electrode 114, the source and drain regions 115a and 115b, respectively, and then a conductive material is deposited to fill the contact holes. 116a through 116d). In this case, the contact plug 116a connected to the source region 115a of the PMOS transistor is connected to the power supply voltage terminal VDD, and is connected to the drain region 115a of the PMOS transistor and the source region 115b of the NMOS transistor. The plug 116c is connected to an output terminal Vout through which an output signal is output, and the contact plug 116d connected to the common gate electrode 114 is connected to an input terminal Vin through which an input signal is input.

In the above description, only a CMOS inverter and a method of manufacturing the same have been described for convenience of description. However, he can be applied to the MOS transistor and the method of manufacturing the same as an example.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, by using the gate electrodes of the PMOS and NMOS transistors jointly, the number of gate electrodes can be reduced by one compared with the prior art, thereby reducing the size of the overall device.

In addition, the size of the device isolation film can be reduced compared to the prior art by forming a device isolation film on upper and lower portions of the common gate electrode to separate the PMOS and NMOS transistors.

In addition, the height of the device can be reduced by embedding the common gate electrode in a trench structure.

In addition, since the common gate electrode is formed, a wiring process for connecting the gate electrodes of the PMOS and NMOS transistors, as in the conventional art, is unnecessary, thereby simplifying the process.

Claims (9)

Trenches formed in the substrate; An isolation layer formed to fill the upper and lower portions of the trench; A common gate electrode formed to fill the trench between the device isolation layers; A gate oxide layer formed between the common gate electrode and the inner sidewall of the trench; And A junction region formed in the substrate exposed to one side of the device isolation layer; Morse transistor comprising a. The method of claim 1, And a channel region formed along an inner sidewall of the trench. Trenches formed in the substrate; First and second conductivity wells formed in the substrate and formed on the outer side of the trench with the trench as a boundary; An isolation layer formed to fill the upper and lower portions of the trench; A common gate electrode formed to fill the trench between the device isolation layers; A gate oxide layer formed between the common gate electrode and the inner sidewall of the trench; And First and second conductivity type junction regions formed in the substrate exposed to both sides of the device isolation layer; CMOS inverter comprising a. The method of claim 3, wherein And a channel region formed along an inner wall of the trench. The method according to claim 3 or 4, The CMOS inverter of the first and second conductive junction regions, one of the different conductive junction regions separated from each other by the device isolation layer is connected to each other through a contact. Forming a trench in the substrate; Forming a gate oxide film on an inner sidewall of the trench; Forming an isolation layer to fill upper and lower portions of the trench; Forming a gate electrode to fill the trench between the device isolation layers; And Forming a junction region in the substrate exposed to one side of the device isolation layer Method of manufacturing a MOS transistor comprising a. The method of claim 6, And forming a well in the substrate exposed to both sides of the device isolation layer after the gate electrode is formed. Forming a trench in the substrate; Forming a gate oxide film on an inner sidewall of the trench; Forming an isolation layer to fill upper and lower portions of the trench; Forming a common gate electrode to fill the trench between the device isolation layers; And Forming first and second conductivity type junction regions in the substrate exposed to both sides of the device isolation layer. Method of manufacturing a CMOS inverter comprising a. 9. The method of claim 8, And forming first and second conductive wells in the substrate exposed to both sides of the device isolation layer after forming the common gate electrode.

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