CN106129068B - A kind of inverter structure and its display panel - Google Patents
A kind of inverter structure and its display panel Download PDFInfo
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- CN106129068B CN106129068B CN201610594624.XA CN201610594624A CN106129068B CN 106129068 B CN106129068 B CN 106129068B CN 201610594624 A CN201610594624 A CN 201610594624A CN 106129068 B CN106129068 B CN 106129068B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 41
- 229920005591 polysilicon Polymers 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 58
- 239000011229 interlayer Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000000694 effects Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000010348 incorporation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention discloses a kind of inverter structure and its display panel.The inverter structure includes: the first transistor pipe and second transistor, the first transistor includes the first polysilicon layer, first grid, the first source electrode and the first drain electrode, and second transistor includes the second polysilicon layer, second grid, the second source electrode and the second drain electrode.Inverter structure provided by the invention is due to being equipped with the first drain region and the second drain region, second drain region is arranged in same a line and is disposed adjacent with the first drain region, the height and area of inverter structure can be reduced, to reach the height and area that reduce display panel, so as to save the cost.
Description
Technical field
The present invention relates to inverter technology fields, more particularly to a kind of inverter structure and its display panel.
Background technique
Phase inverter is the phasing back 180 degree of input signal, inverter circuit can be mainly used in analog circuit,
Such as audio amplifier circuit, clock oscillator circuit etc..In the route design of liquid crystal display panel, also often to use anti-
Phase device circuit.
Currently, low temperature polycrystalline silicon (LTPS) semiconductor thin-film transistor route design in, the structure of phase inverter be by
NTFT and PTFT are individually designed, therefore the height of phase inverter and area will affect height and the face of entire liquid crystal display panel
Product, to increase cost.
Summary of the invention
The present invention provides a kind of inverter structure and its display panel, to solve the height of phase inverter and face in the prior art
Product influences the technical issues of height and the area of liquid crystal display panel are to increase cost.
To achieve the above object, one technical scheme adopted by the invention is that: a kind of inverter structure is provided, is at least wrapped
It includes:
The first transistor, comprising:
First polysilicon layer, including the first source region, the first drain region and the first channel region, the first channel region
Domain is arranged between the first source region and the first drain region；
First grid is arranged on the first channel region；
First source electrode is arranged on the first source region, connect with the first level；
First drain electrode, is arranged on the first drain region；
Second transistor, comprising:
Second polysilicon layer is disposed adjacent with the first polysilicon layer, including the second source region, the second drain region and
Second channel region, the second drain region are arranged in same a line and are disposed adjacent, the second channel region with the first drain region
It is arranged between the second source region and the second drain region；
Second grid is arranged on the second channel region, is electrically connected with first grid, forms the input terminal of phase inverter；
Second source electrode is arranged on the second source region, connect with second electrical level；
Second drain electrode, is arranged on the second drain region, and is electrically connected with the first drain electrode, forms the output of phase inverter
End.
Wherein, the first drain region and the second drain region are respectively strip structure, and the first drain region and second
Drain region arranges in the same row.
Wherein, the first drain region includes the first main part and the first extension, and the first extension is remote from the first main part
Edge from the first channel region extends to the direction of the second drain region；
Second drain region includes the second main part and the second extension, and the second extension is from the second main part far from second
The edge of channel region extends to the direction of the first drain region；
Wherein, the sum of the length of the first extension and the length of the second extension are less than the length of the first main part or
The length of two main parts.
Wherein, inverter structure is applied at least two phase inverters, and inverter structure further comprises:
Third transistor, comprising:
Second polysilicon layer further comprises third channel region and third drain region, and the setting of third channel region is the
Between two source regions and third drain region；
Third grid is arranged on third channel region；
Third source electrode is the second source electrode；
Third drain electrode, is arranged on third drain region；
4th transistor, comprising:
Third polysilicon layer is disposed adjacent with the second polysilicon layer, including the 4th source region, the 4th drain region and
4th channel region, the 4th drain region are arranged in same a line and are disposed adjacent, the 4th channel region with third drain region
It is arranged between the 4th source region and the 4th drain region；
4th grid is arranged on the 4th channel region, is electrically connected with third grid, is formed at least two phase inverters
The input terminal of another phase inverter；
4th source electrode is arranged on the 4th source region, connect with the first level；
4th drain electrode, is arranged on the 4th drain region, and drains and be electrically connected with third, forms at least two phase inverters
In another phase inverter output end.
Wherein, the first transistor and the 4th transistor are first kind transistor, and second transistor and third transistor
For Second Type transistor, and the type of first kind transistor and Second Type transistor is different.
Wherein, inverter structure further comprises:
First interlayer dielectric layer, setting is between the first polysilicon layer and first grid, the first source electrode and the first drain electrode；
Second interlayer dielectric layer, setting is between the second polysilicon layer and second grid, the second source electrode and the second drain electrode.
Wherein, the first source electrode connects the first source region by least one through-hole, and the first drain electrode is logical by least one
Hole connects the first drain region；Second source electrode connects the second source region by least one through-hole, and the second drain electrode is by least
One through-hole connects the second drain region.
Wherein, the first transistor is P-type TFT, and second transistor is N-type TFT.
Wherein, the first source region is P-doped zone domain, and the first drain region is P-doped zone domain；Second source region
For n-type doping region, the second drain region is n-type doping region.
To achieve the above object, another technical solution used in the present invention is: providing a kind of display panel comprising on
The inverter structure stated.
The beneficial effects of the present invention are: being in contrast to the prior art, inverter structure provided by the invention is due to setting
There are the first drain region and the second drain region, the second drain region and the first drain region are arranged in same a line and adjacent set
It sets, it is possible to reduce the height and area of inverter structure, to reach the height and area for reducing display panel, to save into
This.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it may further obtain according to these attached drawings
Other attached drawings.Wherein:
Fig. 1 is the layout design schematic diagram of the inverter structure of first embodiment of the invention；
Fig. 2 is the circuit diagram of phase inverter in Fig. 1；
Fig. 3 is the layout design schematic diagram of the inverter structure of second embodiment of the invention；
Fig. 4 is the layout design schematic diagram of the inverter structure of third embodiment of the invention；
Fig. 5 is the structural schematic diagram of the display panel of first embodiment of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall within the protection scope of the present invention.
Shown in Figure 1, Fig. 1 is the layout design schematic diagram of the inverter structure of first embodiment of the invention.This reality
Apply GOA (Gate Driver on Array, the driving of the array substrate row) electricity of the revealed phase inverter of example applied to display panel
In the design of road, the phase inverter of afterbody uses the revealed inverter structure of the present embodiment preferably in GOA circuit.
As shown in Figure 1, the revealed inverter structure 10 of the present embodiment includes at least the first transistor 11 and the second crystal
Pipe 12, the corresponding circuit diagram of inverter structure 10 are as shown in Figure 2.
Wherein, the first transistor 11 includes the first polysilicon layer 111, first grid 112, the first source electrode 113 and first
Drain electrode 114, the first polysilicon layer 111 include the first source region 115, the first drain region 116 and the first channel region
117, the first channel region 117 is arranged between the first source region 115 and the first drain region 116.First grid 112 is arranged
On the first channel region 117, the first source electrode 113 is arranged on the first source region 115, and the first drain electrode 114 is arranged first
On drain region 116.First source electrode 113 is connect with the first level, and the first level is preferably high level VGH.
Wherein, second transistor 12 includes the second polysilicon layer 121, second grid 122, the second source electrode 123 and second
Drain electrode 124, the second polysilicon layer 121 include the second source region 125, the second drain region 126 and the second channel region
127, the second channel region 127 is arranged between the second source region 125 and the second drain region 126.Second grid 122 is arranged
On the second channel region 127, the second source electrode 123 is arranged on the second source region 125, and the second drain electrode 124 is arranged second
On drain region 126.Second source electrode 123 is connect with second electrical level, and second electrical level is preferably low level VGL.
Wherein, region and the first source region 115 composed by the first drain region 116 and the second drain region 126 and
Second source region 125 is oppositely arranged respectively.
Second grid 122 and first grid 112 are electrically connected, to form the input terminal IN of inverter structure 10；Second leakage
Pole 124 and the first drain electrode 114 are electrically connected, to form the output end OUT of inverter structure 10.
Second polysilicon layer 121 is disposed adjacent with the first polysilicon layer 111, i.e. the first polysilicon layer 111 and the second polycrystalline
There are certain gaps between silicon layer 121, polysilicon layer can be avoided to produce when multiple phase inverters use the inverter structure 10
It is born from heating (Self-Heating) effect.Second drain region 126 is arranged with the first drain region 116 in same a line and phase
Neighbour's setting, compared to the prior art, the application are leaked the second of the first drain electrode 114 of the first transistor 11 and second transistor 12
Half is dug up in pole 124, and then can reduce the height and area of inverter structure 10.
Wherein, first grid 112 and second grid 122 are prepared using same layer gate metal, the leakage of the first source electrode 113, first
Pole 114, the second source electrode 123 and the second drain electrode 124 are standby using same layer hourglass source electrode made of metal, hourglass source electrode metal and gate metal system
It is standby to can be set in same layer, it also can be set in not same layer.That is the first source electrode 113 and the second source electrode 123 can be with first
Drain electrode 114 and the second drain electrode 124 are arranged in same layer.
Preferably, the first drain region 116 and the second drain region 126 are respectively strip structure, the second drain region
126 are arranged in same a line and are disposed adjacent with the first drain region 116, and arrangement architecture can be divided into left-right situs.
Wherein, the first source electrode 113 connects the first source region 115 by least one through-hole 118, and the first drain electrode 114 is logical
It crosses at least one through-hole 119 and connects the first drain region 116；Second source electrode 123 connects the second source by least one through-hole 128
Polar region domain 125, the second drain electrode 124 connect the second drain region 126 by least one through-hole 129.
The first transistor 11 is first kind transistor, and second transistor 12 is Second Type transistor, and the first kind
Transistor npn npn is different with the type of Second Type transistor.Preferably, the first transistor 11 is P-type TFT, and second is brilliant
Body pipe 12 is N-type TFT.
Specifically, the first source region 115 is P-doped zone domain, the first drain region 116 is P-doped zone domain, p-type
Doped region is incorporation trivalent impurity element, such as boron, gallium；And the second source region 125 is n-type doping region, the second drain region
Domain 126 is n-type doping region, and n-type doping region is incorporation pentavalent impurity element, such as phosphorus, arsenic.
Further, inverter structure 10 include the first interlayer dielectric layer and the second interlayer dielectric layer (not shown), first
Interlayer dielectric layer is arranged between the first polysilicon layer 111 and first grid 112, the first source electrode 113 and the first drain electrode 114,
The setting of second interlayer dielectric layer the second polysilicon layer 121 and second grid 122, the second source electrode 123 and the second drain electrode 124 it
Between.In addition, the first source electrode 113 and the second source electrode 123 can also be arranged in the first interlayer dielectric layer or the second interlayer dielectric layer
Between, i.e. the first interlayer dielectric layer and the second interlayer dielectric layer can be set between the different layers, also can be set in same layer pole
Between, to play isolation and insulating effect.
Referring to Fig. 3, Fig. 3 is the layout design schematic diagram of inverter structure second embodiment provided by the invention.Such as Fig. 3
Shown, the difference of the revealed inverter structure of the present embodiment and the revealed inverter structure 10 of first embodiment exists
It include the first main part 100 and the first extension 101 in: the first drain region 116, the first extension 101 is from the first main part
100 edges far from the first channel region 117 extend to the direction of the second drain region 126.Second drain region 126 includes
Second main part 102 and the second extension 103, the second extension 103 is from the second main part 102 far from the second channel region 127
Edge to the direction of the first drain region 116 extend.
Wherein, the sum of the length of the first extension 101 and the length of the second extension 103 are less than the first main part 100
The length of length or the second main part 102.Preferably, the length of the first extension 101 is less than or equal to the first main part
The half of 100 length, the length of the second extension 103 are less than or equal to the half of the length of the second main part 102.This reality
The inverter structure for applying example not only reduces height and area, it can also be ensured that the first channel region 117 and the second channel region 127
Effective length.
Referring to Fig. 4, Fig. 4 is the layout design schematic diagram of inverter structure 3rd embodiment provided by the invention.This reality
It applies the revealed inverter structure of example to be described on the basis of second embodiment revealed inverter structure, wherein this reality
It applies the revealed inverter structure of example and is applied at least two phase inverters, the present embodiment is described in detail with two phase inverters.
In other embodiments, multiple phase inverters can also be used the inverter structure, such as five by those skilled in the art
A phase inverter uses the inverter structure, and details are not described herein.
As shown in figure 4, the inverter structure further comprises third transistor 13 and the 4th transistor 14.Wherein, third
Transistor 13 includes the second polysilicon layer 121, third grid 131, third source electrode 132 and third drain electrode 133, the second polysilicon
Layer 121 further comprises third channel region 134 and third drain region 135, and third channel region 134 is arranged in the second source
Between polar region domain 125 and third drain region 135.Third grid 131 is arranged on third channel region 134；Third source electrode 132
For the second source electrode 123, i.e. two phase inverters share the second source electrode 123；Third drain electrode 133 is arranged on third drain region 135.
4th transistor 14 includes third polysilicon layer 141, the 4th grid 142, the 4th source electrode 143 and the 4th drain electrode
144, third polysilicon layer 141 includes the 4th source region 145, the 4th drain region 146 and the 4th channel region 147, the
Four channel regions 147 are arranged between the 4th source region 145 and the 4th drain region 146.4th grid 142 is arranged the 4th
On channel region 127, the 4th source electrode 143 is arranged on the 4th source region 145, and the 4th drain electrode 144 is arranged in the 4th drain region
On domain 146.4th source electrode 143 is connect with the first level, and the first level is preferably high level VGH.
Wherein, the 4th grid 142 is electrically connected with third grid 131, forms another reverse phase at least two phase inverters
The input terminal IN1 of device.4th drain electrode 144 is electrically connected with third drain electrode 133, forms another reverse phase at least two phase inverters
The output end OUT1 of device.
Wherein, the 4th drain region 146 is arranged in same a line and is disposed adjacent with third drain region 135.Due to
There are certain gap between one polysilicon layer 111, the second polysilicon layer 121 and third polysilicon layer 141, therefore this implementation
The inverter structure of example not only reduces height and area, and polysilicon layer can also be avoided to generate self-heating effect.
Referring to Fig. 5, Fig. 5 is the structural schematic diagram of one embodiment of display panel provided by the invention.
As shown in figure 5, the display panel 40 includes multiple above-mentioned inverter structures 300, the setting of inverter structure 300 exists
In the route design of 40 peripheral circuit of display panel.
Wherein, inverter structure 300 is inverter structure described in above-described embodiment, and it is no longer repeated herein.
In conclusion inverter structure provided by the invention is due to being equipped with the first drain region and the second drain region, the
Two drain regions are arranged in same a line and are disposed adjacent with the first drain region, it is possible to reduce the height of inverter structure and face
Product, to reach the height and area for reducing display panel, so as to save the cost.Due to the first polysilicon layer, the second polysilicon
There are certain gaps between layer and third polysilicon layer, and polysilicon layer can also be avoided to generate self-heating effect.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (8)
1. a kind of inverter structure, which is characterized in that the inverter structure includes at least:
The first transistor, comprising:
First polysilicon layer, including the first source region, the first drain region and the first channel region, first channel region
Domain is arranged between first source region and first drain region；
First grid is arranged on first channel region；
First source electrode is arranged on first source region, connect with the first level；
First drain electrode, is arranged on first drain region；
Second transistor, comprising:
Second polysilicon layer is disposed adjacent with first polysilicon layer, including the second source region, the second drain region and
Second channel region, second drain region is arranged in same a line and is disposed adjacent with first drain region, described
Second channel region is arranged between second source region and second drain region；
Second grid is arranged on second channel region, is electrically connected with the first grid, forms the phase inverter
Input terminal；
Second source electrode is arranged on second source region, connect with second electrical level；
Second drain electrode, is arranged on second drain region, and is electrically connected with first drain electrode, forms the phase inverter
Output end；
First drain region and second drain region are respectively strip structure, and first drain region and institute
State the arrangement of the second drain region in the same row；
First drain region includes the first main part and the first extension, and first extension is from first main part
Edge far from first channel region extends to the direction of second drain region；
Second drain region includes the second main part and the second extension, and second extension is from second main part
Edge far from second channel region extends to the direction of first drain region；
Wherein, the sum of the length of first extension and the length of second extension are less than the length of first main part
The length of degree or second main part.
2. inverter structure according to claim 1, which is characterized in that it is anti-that the inverter structure is applied at least two
Phase device, the inverter structure further comprises:
Third transistor, comprising:
Second polysilicon layer further comprises third channel region and third drain region, the third channel region setting
Between second source region and the third drain region；
Third grid is arranged on the third channel region；
Third source electrode is second source electrode；
Third drain electrode, is arranged on the third drain region；
4th transistor, comprising:
Third polysilicon layer is disposed adjacent with second polysilicon layer, including the 4th source region, the 4th drain region and
4th channel region, the 4th drain region is arranged in same a line and is disposed adjacent with the third drain region, described
4th channel region is arranged between the 4th source region and the 4th drain region；
4th grid is arranged on the 4th channel region, is electrically connected with the third grid, forms described at least two
The input terminal of another phase inverter in phase inverter；
4th source electrode is arranged on the 4th source region, connect with the first level；
4th drain electrode, is arranged on the 4th drain region, and drains and be electrically connected with the third, forms described at least two
The output end of another phase inverter in a phase inverter.
3. inverter structure according to claim 2, which is characterized in that the first transistor and the 4th transistor
For first kind transistor, and the second transistor and the third transistor are Second Type transistor, and described first
Type of transistor is different with the type of the Second Type transistor.
4. inverter structure according to claim 1, which is characterized in that the inverter structure further comprises:
First interlayer dielectric layer, setting is in first polysilicon layer and the first grid, first source electrode and described the
Between one drain electrode；
Second interlayer dielectric layer, setting is in second polysilicon layer and the second grid, second source electrode and described the
Between two drain electrodes.
5. inverter structure according to claim 2, which is characterized in that first source electrode is connected by least one through-hole
First source region is connect, first drain electrode connects first drain region by least one through-hole；Described second
Source electrode connects second source region by least one through-hole, and second drain electrode passes through described in the connection of at least one through-hole
Second drain region.
6. inverter structure according to claim 1, which is characterized in that the first transistor is P-type TFT,
The second transistor is N-type TFT.
7. inverter structure according to claim 6, which is characterized in that first source region is P-doped zone domain,
First drain region is P-doped zone domain；Second source region is n-type doping region, second drain region
For n-type doping region.
8. a kind of display panel, which is characterized in that the display panel includes the phase inverter as described in claim 1 to 7 is any
Structure.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1536668A (en) * | 2003-05-08 | 2004-10-13 | 友达光电股份有限公司 | Complementary metal oxide semiconductor phase reverser |
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| JP2003086685A (en) * | 2001-09-12 | 2003-03-20 | Toshiba Corp | Semiconductor integrated circuit and its manufacturing method |
| KR100842472B1 (en) * | 2006-12-27 | 2008-07-01 | 동부일렉트로닉스 주식회사 | Structure of a semiconductor device for decreasing chip area and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1536668A (en) * | 2003-05-08 | 2004-10-13 | 友达光电股份有限公司 | Complementary metal oxide semiconductor phase reverser |
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