KR100652424B1 - Cmos inverter cell - Google Patents

Abstract

A CMOS(complementary metal oxide semiconductor) inverter cell is provided to reduce parasitic resistance and parasitic capacitance in a circuit and improve the response speed of an inverter by including a relatively small area in comparison with a conventional inverter cell. A straight gate pattern(301) comes in contact with at least one surface of a cell border line. A first active region pattern(302) has a channel region overlapped with the gate pattern and a source/drain region at both sides of the channel region. A second active region pattern(303) has a channel region overlapping the gate pattern and a source/drain region at both sides of the channel region. A first metal line pattern(304) comes in contact with at least one surface of the cell border line, positioned on the first active region. A second metal line pattern(305) comes in contact with one surface of the cell border line, positioned on the first active region. A third metal line pattern(306) is positioned on an extension line of the second metal line pattern, coming in contact with the other surface of the cell border line. A plurality of contacts(CNT) are formed on the source/drain region. The first metal line pattern commonly connects the drain regions of the first and second active region patterns. The second metal line pattern connects the source region of the first active region pattern with a first power source. The third metal line pattern connects the source region of the second active region pattern with a second power source.

Description

CMOS inverter cell

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is an embodiment of a conventional CMOS inverter cell layout.

Figure 2 is another embodiment of a CMOS inverter cell layout in use in the prior art.

3 shows a first embodiment 300 of a CMOS inverter cell according to the present invention.

4 is a second embodiment 400 of a CMOS inverter cell in accordance with the present invention.

5 is a third embodiment 500 of a CMOS inverter cell in accordance with the present invention.

6 is a fourth embodiment 600 of a CMOS inverter cell in accordance with the present invention.

7 is a fifth embodiment 700 of a CMOS inverter cell in accordance with the present invention.

8 is a sixth embodiment 800 of a CMOS inverter cell according to the present invention.

The present invention relates to a layout of an inverter cell, and more particularly, to a complementary metal oxide silicon (CMOS) inverter cell with reduced cell area and improved response speed.

1 is an embodiment of a conventional CMOS inverter cell layout.

Referring to FIG. 1, in the CMOS inverter cell 100, a P-type MOS transistor is formed on an upper portion of the cell, and an N-type MOS transistor is formed on the lower portion of the cell.

In the case of the P-type MOS transistor, the left side of the active area 10 (diffusion area) becomes a source terminal and the right side becomes a drain terminal centering on the P-type gate PGate1. The first power supply VDD is supplied to the source terminal through the contact CNT, and the output signal OUTPUT is output from the drain terminal located on the right through the contact CNT. The P-type gate PGate1 is connected to the external metal line Line1 through the first contact CNT1.

In the case of the N-type MOS transistor, the left side of the active region 11 becomes a source terminal and the right side becomes a drain terminal centering on the N-type gate NGate1. The second power supply VSS is supplied to the source terminal through the contact CNT, and the output OUTPUT signal is connected from the drain terminal located on the right through the contact CNT. The N-type gate NGate1 is connected to the external metal line Line1 through the contact CNT.

The area AREA1 indicated by a dotted line is a space reserved for the external metal line Line1 for applying signals to the P-type gate PGate1 and the N-type gate NGate1. The area AREA1 is located outside of any area including two active areas 10 and 11 performing the functions of a P-type transistor and an N-type transistor in a horizontal direction. Therefore, it is caused to increase the horizontal length of the cell (Length).

The length of the cell in the vertical direction (Height) is determined by the width of the MOS transistor gate, and assuming that the same gate length is wider, the wider the gate width, the greater the current driving capability.

Figure 2 is another embodiment of a CMOS inverter cell layout in use in the prior art.

Referring to FIG. 2, in the CMOS inverter cell 200, a P-type MOS transistor is formed on the upper part of the cell, and an N-type MOS transistor is formed on the lower part of the cell as in the case of FIG. 1. However, the external metal line Line2, which supplies a signal to the gate from the outside, is not directly connected to the gate PGate2 of the P-type MOS transistor and the gate NGate2 of the N-type MOS transistor through the contact CNT, and thus the via contact. The difference is that they are connected via (Via-CNT) and the intermetallic line (Line3).

In the case of the embodiment shown in FIG. 2, the length in the horizontal direction of the cell increases by the width of the area AREA2 indicated by an ellipse.

The inverter cell layout shown in FIGS. 1 and 2 includes external metal lines Line1 and Line2 through which signals applied to the gates PGate1 and PGate2 of the P-type MOS transistor and the gates NGate1 and NGate2 of the N-type MOS transistor are transferred. The area of the cell is increased by that amount because it needs to secure a certain area occupied by).

Also, it is not easy to reduce the length of the cell in the vertical and / or horizontal directions. For example, in order to reduce the length of the vertical direction of the inverter cell layout, a finger gate structure must be introduced in order to reduce the width of the transistor, which is a horizontal direction. Will increase the length of.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a CMOS inverter cell having a reduced response time in horizontal and vertical directions.

One surface of a CMOS inverter cell according to the present invention for achieving the above technical problem, the gate pattern, the first active region pattern, the second active region pattern, the first metal line pattern, the second metal line inside the cell boundary line A pattern, a third metal line pattern and a plurality of contacts are provided.

The gate pattern is in contact with at least one surface of the cell boundary line and has a straight line shape. The first active region pattern includes a channel region overlapping the gate pattern, a drain region and a source region positioned at both sides of the channel region. The second active region pattern includes a channel region overlapping the gate pattern, a drain region and a source region positioned at both sides of the channel region. The first metal line pattern contacts at least one surface of the cell boundary line and is parallel to the gate pattern and positioned above the first active region. The second metal line pattern is in contact with one surface of the cell boundary line, is parallel to the gate pattern, and is positioned above the first active region. The third metal line pattern is positioned on an extension line of the second metal line pattern, contacts the other surface of the cell boundary line, is parallel to the gate pattern, and is positioned above the second active region. The plurality of contacts are respectively provided on the drain region and the source region.

The first metal line pattern may include the drain region and the second region of the first active region pattern via the contact provided in the drain region of the first active region pattern and the contact provided in the drain region of the second active region pattern. The drain region of the active region pattern is connected in common. The second metal line pattern connects the source region of the first active region pattern and the first power source via the contact provided in the source region of the first active region pattern, and the third metal line pattern is the second power line pattern. The source region of the second active region pattern and the second power source are connected via the contact provided in the source region of the active region pattern.

Another aspect of the CMOS inverter cell according to the present invention for achieving the above technical problem is, the first gate pattern, the second gate pattern, the internal connection pattern, the first active region pattern, the second active region inside the cell boundary line A pattern, a first metal line pattern, a second metal line pattern, a third metal line pattern, and a plurality of contacts are provided.

The first gate pattern and the second gate pattern serve as a reference for distinguishing the channel region, the drain region, and the source region of the gate. The internal connection pattern electrically connects the first gate pattern and the second gate pattern. The first active region pattern includes a channel region overlapping the first gate pattern, a drain region and a source region positioned at both sides of the channel region. The second active region pattern includes a channel region overlapping the second gate pattern, a drain region and a source region positioned at both sides of the channel region. The first metal line pattern is in contact with at least one surface of the cell boundary line, is parallel to the first gate pattern, and is positioned above the first active region pattern. The second metal line pattern is in contact with one surface of the cell boundary line, is parallel to the second gate pattern, and is positioned above the first active region pattern. The third metal line pattern is positioned on an extension line of the second metal line pattern, and contacts the other surface of the cell boundary line and is parallel to the first gate pattern and the second gate pattern, and the second active region pattern. Located at the top of the. The plurality of contacts are provided on the gate pattern, the drain region, and the source region, respectively.

The first metal line pattern may include a drain region and the second active region of the first active region pattern via a contact provided in the drain region of the first active region pattern and a contact provided in the drain region of the second active region pattern. The drain region of the pattern is connected in common. The second metal line pattern connects the source region of the first active region pattern to the first power source via a contact provided in the source region of the first active region pattern, and the third metal line pattern is the second active pattern. The source region of the second active region pattern and the second power source are connected via a contact provided in the source region of the region pattern.

The internal connection pattern connects the first gate pattern and the second gate pattern via a contact provided in the gate pattern.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 shows a first embodiment 300 of a CMOS inverter cell according to the present invention.

Referring to FIG. 3, the CMOS inverter cell 300 includes a gate pattern 301, a first active region pattern 302, a second active region pattern 303, a first metal line pattern 304, and a second metal. A line pattern 305, a third metal line pattern 306, a first power line 307, a second power line 308, a gate connection pattern 309, and a plurality of contacts CNTs are provided.

The gate pattern 301 is in contact with one surface of the cell boundary line 310 and has a straight line shape. The first active region pattern 302 is an active region of a P-type MOS transistor including a channel region overlapping the gate pattern 301, drain regions and source regions positioned at both sides of the channel region. The second active region pattern 303 is an active region of an N-type transistor having a channel region overlapping the gate pattern 301, drain regions and source regions positioned at both sides of the channel region.

The contact CNT is disposed on the drain region and the source region of the first active region pattern 302 and the second active region pattern 303, respectively. One surface of the first metal line pattern 304 contacts one surface of the cell boundary line 310 and proceeds in parallel with the gate pattern 301 to transmit an output signal of the inverter. One surface of the second metal line pattern 305 contacts one surface of the cell boundary line 310 and runs parallel to the gate pattern 301. The third metal line pattern 306 is positioned on an extension line of the second metal line pattern 305, and one surface is in contact with the other surface of the cell boundary line 310 and runs parallel to the gate pattern 301.

The first metal line pattern 304 passes through the contact CNT formed on the drain region of the first active region pattern 302 and the contact CNT formed on the drain region of the second active region pattern 303. The drain region of the first active region pattern 302 and the drain region of the second active region pattern 303 are connected in common. The second metal line pattern 305 connects the source region of the first active region pattern 302 and the first power source VDD via the contact CNT provided in the source region of the first active region pattern 302. . The third metal line pattern 306 connects the source region of the second active region pattern 303 and the second power source VSS through the contact CNT provided in the source region of the second active region pattern 303. .

In order to apply a signal to the gate pattern 301, the gate connection pattern 309 is provided outside the CMOS inverter cell 300. In the case of FIG. 3, the gate connection pattern 309 is provided at the boundary line 310 of the cell on which the N-type MOS transistor is generated.

Here, the first power source VDD may be applied through the first power line 307, and the second power source VSS may be applied through the second power line 308. The gate connection pattern 309 is made of the same material as the gate pattern 301 and is adjacent to the outer side of the cell boundary 310 to serve as a passage for transmitting a signal to the gate pattern 301.

3 illustrates a case in which the gate connection pattern 309 is adjacent to the cell boundary where the N-type MOS transistor is located.

4 is a second embodiment 400 of a CMOS inverter cell in accordance with the present invention.

4, the description of the connection relationship is omitted since the position of the gate connection pattern 409 is the same except that the position of the gate connection pattern 409 is adjacent to the cell boundary where the P-type MOS transistor is located.

5 is a third embodiment 500 of a CMOS inverter cell in accordance with the present invention.

Referring to FIG. 5, except that two gate connection patterns 509 and 510 are disposed at a cell boundary where a P-type MOS transistor is located and a cell boundary where an N-type MOS transistor is located, respectively, FIGS. 3 and FIG. Since the same as 4, the description of the connection relationship is omitted.

3 to 5, the CMOS inverter cell according to the present invention has one gate pattern 301, 401, 501 used as a gate terminal of a P-type transistor and an N-type transistor. In addition, the positions and the numbers of the gate connection patterns 309, 409, 509, and 510 for supplying signals to the gate patterns 301, 401, and 501 are different. Therefore, a designer who wants to use the CMOS inverter cell can transfer data to the gate patterns 301, 401, and 501 through one side of the cell and a side corresponding to the one side. Data can be transferred simultaneously through one side and two corresponding sides.

The most important difference between the inverter cell shown in Figs. 3 and 5 and the conventional inverter cell is that the constant area AREA1, which is occupied by the external metal lines Line1 and Line2 shown in Figs. AREA2) is not necessary.

6 to 8 illustrate another embodiment of a CMOS inverter cell according to the present invention, in which a gate pattern of a P-type MOS transistor and a gate pattern of an N-type MOS transistor, which are separated from each other, are connected to a metal or other similar material. to be.

There may be various reasons for the material of the gate pattern of the P-type MOS transistor and the material of the gate pattern of the N-type MOS transistor, and one of the reasons is that it is possible to control by separating the threshold voltage (Threshold Voltage) will be.

6 is a fourth embodiment 600 of a CMOS inverter cell in accordance with the present invention.

Referring to FIG. 6, the CMOS inverter cell 600 includes a first gate pattern 601, a second gate pattern 602, a first active region pattern 603, a second active region pattern 604, and a first gate pattern 601. The first metal line pattern 605, the second metal line pattern 606, the third metal line pattern 607, the first power line 608, the second power line 609, the connection pattern 610, and a plurality of Has contacts (CNTs)

The first gate pattern 601 and the second gate pattern 602 are generally made of polysilicon. The first gate pattern 601 and the second gate pattern 602 are electrically connected to each other by the internal connection pattern 610 via the contact CNT. Here, the contact CNT positioned between the first gate pattern 601 and the internal connection pattern 610 and the second gate pattern 602 and the internal connection pattern 610 may include a contact disposed in the source and drain regions. It may be formed in the same layer as the CNTs, but may be formed in another layer.

The first active region pattern 603 is an active region of a P-type transistor having a channel region overlapping the first gate pattern 601, a drain region and a source region located at both sides of the channel region. The second active region pattern 604 is an active region of an N-type MOS transistor including a channel region overlapping the second gate pattern 602, a drain region and a source region located at both sides of the channel region. A contact CNT is provided in the source region and the drain region of the first active region pattern 603 and the second active region pattern 604.

The first metal line pattern 605 contacts one surface of the cell boundary line 612 and runs parallel to the first gate pattern 601. The second metal line pattern 606 contacts one surface of the cell boundary line 612 and runs parallel to the second gate pattern 602. The third metal line pattern 607 is positioned on an extension line of the second metal line pattern 606, and is in contact with the other surface of the cell boundary line 612 to form the first gate pattern 601 and the second gate pattern 602. Proceed parallel to). The first metal line pattern 605 is formed through the contact CNT formed in the drain region of the first active region pattern 603 and the contact CNT formed in the drain region of the second active region pattern 604. The drain region of the region pattern 603 and the drain region of the second active region pattern 604 are commonly connected. The second metal line pattern 606 connects the source region of the first active region pattern 603 and the first power source VDD via the contact CNT provided in the source region of the first active region pattern 603. . The third metal line pattern 607 connects the source region of the second active region pattern 604 and the second power source VSS through the contact CNT provided in the source region of the second active region pattern 604. .

The gate connection pattern 611 is provided outside the CMOS inverter cell 600 to apply a signal to the second gate pattern 602. In the case of FIG. 6, the gate connection pattern 611 is provided at the boundary line 612 of the cell on which the N-type MOS transistor is generated.

Here, the first power source VDD may be applied through the first power line 608, and the second power source VSS may be applied through the second power line 609. The connection pattern 610 connects the first gate pattern 601 and the second gate pattern 602, and may be implemented using the same material as the first gate pattern 601 and the second gate pattern 602 or made of metal. It can also be implemented using a metal line.

7 is a fifth embodiment 700 of a CMOS inverter cell in accordance with the present invention.

Referring to FIG. 7, the CMOS inverter cell 700 includes the CMOS inverter cell of FIG. 6 except that the gate connection pattern 711 is located at the cell boundary 712 on the side where the P-type MOS transistor is located. Since it is the same as (600), description of the connection relationship is omitted.

8 is a sixth embodiment 800 of a CMOS inverter cell according to the present invention.

Referring to FIG. 8, except that two gate connection patterns 811 and 812 are disposed at a cell boundary where a P-type transistor is located and a cell boundary where an N-type transistor is located, respectively, FIGS. 6 and FIG. Since it is the same as 7, the description of the connection relationship is omitted.

6 to 8, in the CMOS inverter cell according to the present invention, gate patterns 601, 602, 701, 702, 801, and 802 used as gate terminals of a P-type transistor and an N-type transistor are separated from each other. have. In addition, the semiconductor device further includes internal connection patterns 610, 710, and 810 that connect the separated gate patterns 601, 602, 701, 702, 801, and 802 to each other.

The designer who wants to use the CMOS inverter cell can transfer data to the gate patterns 601, 602, 701, 702, 801, and 802 through one side of the cell and a side corresponding to the one side. Data can be transferred simultaneously through one side and two corresponding sides.

The most important difference between the inverter cell shown in Figs. 6 to 8 and the conventional inverter cell is that the constant area AREA1, which is occupied by the external metal lines Line1 and Line2 shown in Figs. AREA2) is not necessary.

In the CMOS inverter cell according to the present invention shown in Figs. 3 to 8, the area in the male direction is reduced compared to the conventional cell. Therefore, when the driving capability of the inverter implemented in the conventional inverter cell and the driving capability of the inverter implemented in the inverter cell according to the present invention are the same, the area occupied in the layout may be relatively reduced.

In order to implement an inverter having a larger driving capability than that of an inverter implemented in a conventional inverter cell, a finger gate structure may be introduced to a reduced horizontal area. That is, in the case of having the same area as that of the conventional inverter cell, the driving capability of the implemented inverter can be relatively improved. This has the advantage of increasing the designer's choice of inverter cells.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, since the CMOS inverter cell according to the present invention can be implemented in a relatively small area compared to a conventional inverter cell having the same driving capability, the parasitic resistance parasitic capacitance in the circuit is reduced, thereby improving the response speed of the inverter. You can. In addition, even when implementing an inverter cell with increased driving capability compared to a conventional inverter cell, there is an advantage that only the same area as the conventional inverter cell occupies.

Claims (18)

A CMOS inverter cell comprising a plurality of patterns formed inside a cell boundary, A gate pattern having a straight line contacting at least one surface of the cell boundary line; A first active region pattern including a channel region overlapping the gate pattern, a drain region and a source region positioned at both sides of the channel region; A second active region pattern including a channel region overlapping the gate pattern, a drain region and a source region positioned at both sides of the channel region; A first metal line pattern in contact with at least one surface of the cell boundary line and parallel to the gate pattern and positioned above the first active region; A second metal line pattern in contact with one surface of the cell boundary line and parallel to the gate pattern and positioned above the first active region; A third metal line pattern positioned on an extension line of the second metal line pattern, in contact with the other surface of the cell boundary line, parallel to the gate pattern, and positioned on an upper portion of the second active region; And A plurality of contacts respectively provided on the drain region and the source region; The first metal line pattern may include the drain region and the second region of the first active region pattern via the contact provided in the drain region of the first active region pattern and the contact provided in the drain region of the second active region pattern. Connecting the drain region of the active region pattern in common, The second metal line pattern connects the source region of the first active region pattern and the first power source via the contact provided in the source region of the first active region pattern, And the third metal line pattern connects the source region of the second active region pattern and the second power supply via the contact provided in the source region of the second active region pattern. The method of claim 1, wherein the CMOS inverter cell, And a gate connection pattern made of the same material as the material of the gate pattern and in contact with an outer surface of the cell boundary line. And the gate pattern is directly connected to the gate connection pattern. The method of claim 2, wherein the gate connection pattern, And a cell boundary line close to the first active region pattern or a cell boundary line close to the second active region pattern. The method of claim 2, wherein the gate connection pattern, And a cell boundary line close to the first active region pattern and a cell boundary line close to the second active region pattern, respectively, and connected to the gate pattern at the same time. The method of claim 1, wherein the channel region, the drain region and the source region of the first active region pattern, Corresponds to the channel region, drain region, and source region of the P-type MOS transistor, The channel region, the drain region and the source region of the second active region pattern are A CMOS inverter cell corresponding to a channel region, a drain region, and a source region of an N-type MOS transistor. The method of claim 1, wherein the voltage level of the first power source, CMOS inverter cell, characterized in that higher than the voltage level of the second power supply The method of claim 1, wherein the CMOS inverter cell, A first power line pattern overlapping the source region of the first active region pattern and having a voltage level of the first power source; And And a second power line pattern overlapping the source region of the second active region pattern and having the second power supply voltage level. The first power line pattern is connected to each other via a source region of the first active region pattern through a plurality of contacts, and the second power line pattern is connected to a source region of the second active region pattern via a plurality of contacts. Connected, And a voltage level of the first power line pattern is higher than a voltage level of the second power line pattern. The method of claim 7, wherein the traveling directions of the first power line pattern and the second power line pattern are: The CMOS inverter cell of claim 1, wherein the gate pattern and the first metal line pattern and the third metal line pattern cross each other. A CMOS inverter cell comprising a plurality of patterns formed inside a cell boundary, A first gate pattern; A second gate pattern; An internal connection pattern connecting the first gate pattern and the second gate pattern; A first active region pattern including a channel region overlapping the first gate pattern, a drain region and a source region positioned at both sides of the channel region; A second active region pattern including a channel region overlapping the second gate pattern, a drain region and a source region positioned at both sides of the channel region; A first metal line pattern in contact with at least one surface of the cell boundary line and parallel to the first gate pattern and positioned on the first active region pattern; A second metal line pattern in contact with one surface of the cell boundary line and parallel to the second gate pattern and positioned on the first active region pattern; A third metal line positioned on an extension line of the second metal line pattern and in contact with the other surface of the cell boundary line and parallel to the first gate pattern and the second gate pattern and positioned on the second active region pattern; pattern; And A plurality of contacts disposed on the gate pattern, the drain region, and the source region, respectively; The first metal line pattern may include a drain region and the second active region of the first active region pattern via a contact provided in the drain region of the first active region pattern and a contact provided in the drain region of the second active region pattern. Connect the drain region of the pattern in common, The second metal line pattern connects the source region of the first active region pattern and the first power source through a contact provided in the source region of the first active region pattern, The third metal line pattern connects the source region of the second active region pattern and the second power supply via a contact provided in the source region of the second active region pattern, And the internal connection pattern connects the first gate pattern and the second gate pattern via a contact provided in the gate pattern. The method of claim 9, wherein the material of the internal connection pattern, And the same or similar material as that of the first gate pattern and the second gate pattern. The method of claim 10, The gate pattern is made of polycrystalline silicon, The material of the internal connection pattern is a CMOS inverter cell, characterized in that the metal. The method of claim 9, wherein the CMOS inverter cell, A gate connection pattern is formed outside the cell boundary and is made of the same material as that of the gate pattern. And the gate pattern is directly connected to the gate connection pattern. The method of claim 12, wherein the gate connection pattern, And a cell boundary line close to the first active region pattern or a cell boundary line close to the second active region pattern. The method of claim 12, wherein the gate connection pattern, And a cell boundary line close to the first active region pattern and a cell boundary line close to the second active region pattern, respectively, and connected to the gate pattern at the same time. The method of claim 9, wherein the channel region, the drain region and the source region of the first active region pattern, Corresponds to the channel region, drain region, and source region of the P-type MOS transistor, The channel region, the drain region and the source region of the second active region pattern are A CMOS inverter cell corresponding to a channel region, a drain region, and a source region of an N-type MOS transistor. 10. The method of claim 9, wherein the voltage level of the first power source, CMOS inverter cell, characterized in that higher than the voltage level of the second power supply The method of claim 9, wherein the CMOS inverter cell, A first power line pattern overlapping the source region of the first active region pattern and having a voltage level of the first power source; And And a second power line pattern overlapping the source region of the second active area pattern and having a voltage level of the second power source. The first power line pattern is connected to each other via a source region of the first active region pattern through a plurality of contacts, and the second power line pattern is connected to a source region of the second active region pattern via a plurality of contacts. Connected, And a voltage level of the first power line pattern is higher than a voltage level of the second power line pattern. 18. The method of claim 17, wherein the traveling direction of the first power line pattern and the second power line pattern, The CMOS inverter cell of claim 1, wherein the gate pattern and the first metal line pattern and the third metal line pattern cross each other.

Images