CN217904398U - Double-aluminum gate NOR gate - Google Patents

Abstract

The embodiment of the utility model discloses two aluminium bars NOR gate. In one embodiment, the dual aluminum gate nor comprises: the first metal layer, the second metal layer and the insulating layer, the first sub-portion in the first metal layer electrically connects the grid electrode of the first P-type transistor and the grid electrode of the first N-type transistor, the second sub-portion electrically connects the grid electrode of the second P-type transistor and the grid electrode of the second N-type transistor, the third sub-portion in the second metal layer is used as a connecting line for connecting the drain electrode of the second P-type transistor, the drain electrode of the first N-type transistor and the drain electrode of the second N-type transistor, and the fourth sub-portion is used as a first input terminal lead, a second input terminal lead and an output terminal lead. According to the embodiment, through two layers of metal, one layer of metal forms a connecting wire for connecting the grid electrode, and the other layer of metal forms a connecting wire for connecting the drain electrode, an input end lead and an output end lead, the integration level of the device is improved, and the device has a wide application prospect.

Description

Double-aluminum gate NOR gate

Technical Field

The utility model relates to a microelectronics technical field. And more particularly, to a dual aluminum gate nor.

Background

CMOS circuits are currently mainstream integrated circuits due to advantages such as low power consumption and easy large-scale integration, and the nor device therein is widely used as a basic logic unit in complex logic circuits. The specific functions of the nor gate are as follows: when the input signal has a high level signal, the input signal is output as a low level signal; the output is a high level signal only when the input is all low level signals.

In the prior art, an aluminum gate CMOS device usually adopts a single-layer metal wiring manner, that is, a single-layer metal is used as a circuit connection line. The single-layer metal wiring mode has certain limitation, and for example, a single aluminum gate nor gate is taken as an example, aluminum wires cannot be crossly arranged during arrangement, so that the aluminum wires can only adopt a snake-shaped wiring mode and an active area 'jumper' mode. Although the wiring mode can logically realize correct product functions, the area of a source drain region is increased, the length of a signal wire is increased, node parasitic capacitance and resistance are increased finally, the running speed of a product is reduced, and the wiring mode is difficult to adapt to a larger-scale and more complex product.

In addition, in order to ensure that the PN junction in the MOS transistor of the nor gate device is in a reverse bias state at all times, the substrate of the PMOS transistor is generally connected to a power supply (VDD), and the substrate of the NMOS transistor is generally connected to a Ground (GND). According to the general wiring rule, a substrate contact hole is usually etched on the periphery of the substrate of the MOS transistor, and then the substrate is connected with VDD or GND through an aluminum wire. In the single aluminum gate process, when other signal lines need to pass through the periphery of the substrate, the substrate-aluminum line contact holes connected with VDD or GND cannot be formed in the substrate, which may cause insufficient substrate contact, thereby causing MOS transistor leakage.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problems, the utility model adopts the following technical scheme:

the utility model discloses the first aspect provides a two aluminium bars NOR gate, include first P type transistor, second P type transistor, first N type transistor and second N type transistor based on the substrate forms, still include: a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, wherein:

a first metal layer including a first sub-portion electrically connecting the gate of the first P-type transistor with the gate of the first N-type transistor and a second sub-portion electrically connecting the gate of the second P-type transistor with the gate of the second N-type transistor,

and a second metal layer including a third sub-section serving as a connection line connecting the drain of the second P-type transistor, the drain of the first N-type transistor, and the drain of the second N-type transistor, and a fourth sub-section serving as a first input terminal lead, a second input terminal lead, and an output terminal lead.

In some alternative embodiments, the insulating layer has a first via and a second via therein, wherein

The orthographic projection of the drain electrode of the second P-type transistor on the substrate covers the orthographic projection of the first through hole on the substrate, the orthographic projection of the drain electrode of the second N-type transistor on the substrate covers the orthographic projection of the second through hole on the substrate,

the third sub-portion is electrically connected with the drain electrode of the second P-type transistor through the first through hole and is electrically connected with the drain electrode of the second N-type transistor through the second through hole,

an orthographic projection of the second sub-portion on the substrate overlaps an orthographic projection of the third sub-portion on the substrate.

In some alternative embodiments, the portion of the fourth subsection serving as the output terminal lead is electrically connected to the drain of the second P-type transistor through the first via.

In some alternative embodiments, the portion of the fourth subsection that serves as the output terminal lead is disposed between the second P-type transistor and the second N-type transistor.

In some optional embodiments, the insulating layer further comprises a third via and a fourth via, wherein

An orthographic projection of the second sub-portion on the substrate covers an orthographic projection of the third through hole on the substrate, an orthographic projection of the first sub-portion on the substrate covers an orthographic projection of the fourth through hole on the substrate,

a portion of the fourth sub-portion functioning as the first input terminal lead is electrically connected to the second sub-portion through the third through hole, and an orthogonal projection of the portion of the fourth sub-portion functioning as the first input terminal lead on the substrate overlaps with an orthogonal projection of the first sub-portion on the substrate,

the portion of the fourth sub-section serving as the second input terminal lead is electrically connected to the first sub-section through the fourth through hole.

In some alternative embodiments, the portions of the fourth sub-portion that serve as the first input terminal lead and the second output terminal lead are disposed between the first P-type transistor and the first N-type transistor.

In some optional embodiments, the first metal layer further comprises an electrical source and a ground, wherein

The electric source electrode is electrically connected with the source electrode of the first P type transistor, and the ground electrode is electrically connected with the source electrode of the first N type transistor and the source electrode of the second N type transistor.

In some optional embodiments, further comprising:

a plurality of first substrate contact holes formed in the substrate at a side close to the source of the first P-type transistor;

a plurality of second substrate contact holes formed on one side of the substrate close to the drain electrode of the second P-type transistor;

a plurality of third substrate contact holes formed in the substrate at a side close to the source of the first N-type transistor;

a plurality of fourth substrate contact holes formed in the substrate at a side close to the source of the second N-type transistor;

a plurality of fifth substrate contact holes formed between the first substrate contact holes and the second substrate contact holes, the arrangement direction of the fifth substrate contact holes being perpendicular to the arrangement direction of the first substrate contact holes and the second substrate contact holes, respectively; and

a plurality of sixth substrate contact holes formed between the third substrate contact holes and the fourth substrate contact holes, the sixth substrate contact holes being arranged in a direction perpendicular to the arrangement direction of the third substrate contact holes and the fourth substrate contact holes, respectively,

the first metal layer further comprises a first substrate lead and a second substrate lead, wherein

A first substrate lead electrically connects the substrate to a power supply through the first substrate contact hole, the second substrate contact hole and the fifth substrate contact hole,

the second substrate lead electrically connects the substrate to ground through the third substrate contact hole, the fourth substrate contact hole, and the sixth substrate contact hole.

In some optional embodiments, the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The utility model has the advantages as follows:

the utility model discloses to present problem provides a two aluminium bars NOR gate. This two aluminium bars NOR gate adopts double-deck metal wiring, is equipped with two-layer metal wiring electricity and connects required contact hole in the insulating layer between the two-layer metal wiring to make and to lay out separately as required between each layer metal connecting wire, also can take place the overlap, not only effectively shortened signal line length, can avoid active area "wire jumper" moreover, reduce source leakage district area, reduce node parasitic capacitance and resistance, improve the integrated level of device, have extensive application prospect.

On the basis, the output end lead is arranged in the middle area of the layout, so that the layout of the double-aluminum gate NOR gate is more reasonable, the number of substrate contact holes can be increased, the substrate is contacted more fully, and electric leakage is avoided.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 shows a schematic layout of a nor gate in the prior art;

FIG. 2 shows a circuit schematic of a dual aluminum gate NOR gate according to an embodiment of the present application;

fig. 3-5 show schematic layouts of a dual aluminum gate nor gate according to an embodiment of the present application.

Detailed Description

In order to explain the present invention more clearly, the present invention will be further described with reference to the following embodiments and the accompanying drawings. Like parts in the drawings are denoted by the same or similar reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

It should be noted that the ordinal numbers such as "first", "second", and "third" in the present application are not intended to limit the specific sequences, but only to distinguish between the various elements.

In the present invention, the expressions "in 8230", "in 8230a", "in 8230", "in 82308230a" \8230 "", and "in 8230a" \8230a "", and the like, may indicate that one layer is directly formed or provided on the other layer, or that one layer is indirectly formed or provided on the other layer, that is, that other layers are present between the two layers.

In the prior art, an aluminum gate nor device adopts a single aluminum structure, that is, a single aluminum wiring is adopted. As shown in fig. 1, the two transistors shown in the upper half of the figure are PMOS transistors connected in series, and the two transistors shown in the lower half are NMOS transistors connected in parallel. Of the two PMOSs, the source and the substrate of the first PMOS are connected to VDD through an aluminum wire, wherein the substrate is connected to the electric source VDD through a substrate contact hole through an aluminum wire, and the source of the second PMOS and the drain of the first PMOS are electrically connected through a common electrode. Of the two NMOSs, the sources of the first NMOS and the second NMOS and the substrate are connected to the ground GND through aluminum wires, wherein the substrate is connected to the ground GND through a substrate contact hole via the aluminum wires. The drain of the first NMOS and the drain of the second NMOS are electrically connected by a common electrode. The drain electrode of the first NMOS, the drain electrode of the second NMOS and the drain electrode of the second PMOS are electrically connected through an active region jumper wire, and an output end lead is led out; the grid of the first PMOS is electrically connected with the grid of the first NMOS and is led out through an output end lead 1; the grid electrode of the second PMOS and the grid electrode of the second NMOS are electrically connected and are led out through an output end lead 2.

Because the traditional aluminum gate NOR gate adopts single-layer aluminum wiring, namely, the connecting wires comprise the connecting wires for connecting each transistor, the input end leads, the output end leads and the substrate contact holes and the connecting wires for connecting the power supply electrode VDD or the ground electrode GND all adopt the same layer of metal wiring. Referring to fig. 1, in order to avoid short circuit between metals in the same layer, the input terminal leads 1 and 2 and the output terminal lead need to be extended to the periphery of the nor gate, and the increase of the lead length increases the resistance value of the connection line, the area of the occupied active region and the device size; the connecting line between the drain of the second PMOS and the drain of the first/second NMOS needs to adopt the mode of active area 'jumper', the area of the active area is increased, the size of the device is further increased, and the 'jumper' of the active area generates parasitic resistance and parasitic capacitance; meanwhile, because the connection line of the substrate contact hole and the input/output terminal lead led out to the periphery of the nor gate are of the same layer of metal, the substrate contact hole cannot be formed in the region where the input terminal leads 1 and 2 and the output terminal lead pass through, so that the substrate contact is insufficient, and electric leakage is easily caused.

Based on the above problem, the embodiment of the utility model provides a two aluminium bars NOR gate, include two P type transistors (PMOS) and two N type transistors (NMOS) that form based on the substrate, write as first P type transistor, second P type transistor, first N type transistor and second N type transistor respectively, be different from prior art in addition, two aluminium bars NOR gate still includes: a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, wherein:

a first metal layer on the substrate, which includes a first sub-portion electrically connecting the gate of the first P-type transistor with the gate of the first N-type transistor, and a second sub-portion electrically connecting the gate of the second P-type transistor with the gate of the second N-type transistor,

and a second metal layer on the insulating layer, the second metal layer including a third sub-portion and a fourth sub-portion, the third sub-portion serving as a connection line connecting the drain of the second P-type transistor, the drain of the first N-type transistor, and the drain of the second N-type transistor, and the fourth sub-portion serving as a first input terminal lead, a second input terminal lead, and an output terminal lead.

In the embodiment, the gate of the first P-type transistor is electrically connected with the gate of the first N-type transistor through the first metal layer, and the gate of the second P-type transistor is electrically connected with the gate of the second N-type transistor; the second metal layer is used as a connecting wire for connecting the drain electrode of the second P-type transistor, the drain electrode of the first N-type transistor and the drain electrode of the second N-type transistor, and is used as a first input lead wire, a second input lead wire and an output lead wire, and an insulating layer is arranged between the first input lead wire and the second input lead wire, so that all layers of metal connecting wires can be respectively arranged according to the layouts of PMOS and NMOS, the orthographic projections of the two layers of metal wires on the substrate can be overlapped, the length of the signal wire is shortened, meanwhile, the use of active area 'jumper' can be avoided, the area of a source drain area is reduced, node parasitic capacitance and resistance are reduced, the integration level of the device is improved, and the wide application prospect is achieved.

First, the connection relationship of the nor gate is described with reference to a schematic circuit diagram shown in fig. 2. The nor gate includes two PMOS transistors and two NMOS transistors. The two P-type transistors MP1 and MP2 are connected in series, and the two N-type transistors MN1 and MN2 are connected in parallel. The grid electrode G of the second P-type transistor MP2 and the grid electrode G of the second N-type transistor MN2 are electrically connected together and lead out a first input end A, and the grid electrode G of the first P-type transistor MP1 and the grid electrode G of the first N-type transistor MN1 are electrically connected together and lead out a second input end B. The source S of the first P-type transistor MP1 is electrically connected to the power supply VDD, the drain D of the first P-type transistor MP1 is electrically connected to the source S of the second P-type transistor MP2, the drain D of the second P-type transistor MP2 is electrically connected to the drain D of the first N-type transistor MN1 and the drain D of the second N-type transistor MN2 to draw the output terminal out, and the source S of the first N-type transistor MN1 and the source S of the second N-type transistor MN2 are electrically connected to the ground GND.

It should be noted that the nor gate is a series-parallel connection of the four transistors, so that the connection relationship between the transistors cannot be shown simultaneously in a cross-sectional view, and hereinafter, a specific structure and an interlayer relationship of the nor gate will be shown based on a layout, and in order to clearly mark structures of each part, in the drawings, the layout of the dual aluminum gate nor gate according to an embodiment is divided into three diagrams of fig. 3 to 5 to mark different structural regions respectively for description. The specific structure of the dual aluminum gate nor gate according to the embodiment of the present application is described in detail below with reference to fig. 3 to 5.

Referring to fig. 3, the dual al-gate nor gate includes a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2 formed on the basis of a substrate. Specifically, each transistor comprises a source region and a drain region which are formed in a substrate, and a grid which is formed on the surface of the substrate and located between the source/drain regions, wherein the grid is separated from the substrate through a grid dielectric layer; of course, a well region is also formed in the substrate, and the source/drain regions of the P-type transistor or the N-type transistor are located in the well region. Referring to fig. 2, the specific circuit connection relationship of the transistors may be that the first P-type transistor MP1 and the second P-type transistor MP2 are connected in series, and the first N-type transistor MN1 and the second N-type transistor MN2 are connected in parallel. In this application, the material of the substrate may be silicon. The gates of the first P-type transistor MP1, the second P-type transistor MP2, the first N-type transistor MN1, and the second N-type transistor MN2 are made of aluminum.

In the dotted line frame of the upper half of fig. 3, the left transistor is a first P-type transistor MP1, the right transistor is a second P-type transistor MP2, and the drain of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are electrically connected together by sharing them. In the dotted line frame in the lower half of fig. 3, the left transistor is a first N-type transistor MN1, the right transistor is a second N-type transistor MN2, and the drain of the first N-type transistor MN1 and the drain of the second N-type transistor MN2 are electrically connected together by sharing.

As can be understood by those skilled in the art, a through hole may be provided in the insulating medium layer, and an orthogonal projection of the through hole on the substrate overlaps with an orthogonal projection of the drain region of the first P-type transistor MP1 on the substrate and an orthogonal projection of the source region of the second P-type transistor MP2 on the substrate, and an aluminum plug is formed by depositing aluminum in the through hole, so that on one hand, consistency of source and drain regions of the first P-type transistor MP1 and the second P-type transistor MP2 is maintained, and on the other hand, an electrode of the drain of the first P-type transistor MP1 and an electrode of the source of the second P-type transistor MP2 are commonly led out. The common electrode configuration between the drain of the first N-type transistor MN1 and the drain of the second N-type transistor MN2 is the same, and is not described herein. The grid electrode, the source electrode and the drain electrode of each transistor are made of the same material and are formed in the same layer by the same process. That is, the gate, the source, and the drain of each transistor are formed in the same layer by patterning aluminum material.

In the double-aluminum gate NOR gate, the first metal layer and the second metal layer are made of aluminum. The first metal layer and the second metal layer may be formed by a method of patterning after sputtering, which is not described herein in detail.

The first metal layer and the second metal layer are electrically isolated by an insulating layer. The number of layers and materials of the insulating layer is not intended to be limited. The insulating layer may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Specifically, the first metal layer includes a first sub-portion and a second sub-portion; the second metal layer includes a third sub-portion and a fourth sub-portion. Referring to fig. 3, the first sub-part electrically connects the gate of the first P-type transistor MP1 with the gate of the first N-type transistor; the second sub-part electrically connects the grid of the second P-type transistor with the grid of the second N-type transistor; the third subsection serves as a connection Line connecting the drain of the second P-type transistor MP2, the drain of the first N-type transistor MN1, and the drain of the second N-type transistor MN2, and the fourth subsection serves as a first input terminal Line _ a, a second input terminal Line _ B, and an output terminal Line _ out.

In the present embodiment, the first metal layer and the second metal layer separated by the insulating layer are used to simplify the wiring structure by taking advantage of the double-layer metal wiring, and specifically, the first metal layer is connected to the connection Line of the gate, and the second metal layer is used as the connection Line connecting the drain of the second P-type transistor MP2, the drain of the first N-type transistor MN1, and the drain of the second N-type transistor MN2, and as the first input terminal Line _ a, the second input terminal Line _ B, and the output terminal Line _ out, so that the first input terminal Line _ a, the second input terminal Line _ B, and the output terminal Line _ out are disposed between the two P-type transistors and the two N-type transistors, and a jumper Line is formed by the second metal layer and the first metal layer instead of an active region jumper, thereby reducing the device size, and shortening the length of the connection Line, making it more beneficial to device integration, reducing parasitic resistance, reducing node capacitance, and improving the product operation speed.

Specifically, referring to fig. 4, a first through hole TK1 and a second through hole TK2 are provided in the insulating layer, wherein an orthographic projection of the drain of the second P-type transistor MP2 on the substrate covers an orthographic projection of the first through hole TK1 on the substrate, an orthographic projection of the drain of the second N-type transistor MN2 on the substrate covers an orthographic projection of the second through hole TK2 on the substrate, the third sub-portion is electrically connected with the drain of the second P-type transistor MP2 through the first through hole TK1 and with the drain of the second N-type transistor through the second through hole TK2, and an orthographic projection of the second sub-portion on the substrate overlaps with an orthographic projection of the third sub-portion on the substrate. With this arrangement, a metal jumper is formed between the first sub-portion of the first metal layer and the third sub-portion of the second metal layer, the size of an active region in the nor gate is reduced compared to a manner in which a jumper is formed in the active region, and the parasitic resistance is smaller because the resistivity of the metal jumper is smaller than that of the active region.

Alternatively, as shown with continued reference to fig. 4, the portion of the fourth subsection serving as the output terminal Line _ out is electrically connected to the drain of the second P-type transistor MP2 through the first via TK 1. Furthermore, a third through hole TK3 and a fourth through hole TK4 are provided in the insulating layer, wherein an orthographic projection of the second subsection on the substrate covers an orthographic projection of the third through hole TK3 on the substrate, an orthographic projection of the first subsection on the substrate covers an orthographic projection of the fourth through hole TK4 on the substrate, a portion of the fourth subsection serving as the first input terminal lead Line _ a is electrically connected to the second subsection through the third through hole, and an orthographic projection of the portion of the fourth subsection serving as the first input terminal lead Line _ a on the substrate overlaps with an orthographic projection of the first subsection on the substrate, and a portion of the fourth subsection serving as the second input terminal lead Line _ B is electrically connected to the first subsection through the fourth through hole TK 4.

With the above arrangement, by using the second metal layer as the first input terminal Line _ a, the second input terminal Line _ B, and the output terminal Line _ out, it is possible to make the orthographic projection of the first input terminal Line _ a on the substrate overlap with the orthographic projection of the first sub-section of the first metal layer connecting the gate of the first P-type transistor MP1 and the gate of the first N-type transistor MN1 on the substrate, and the output terminal Line _ out is electrically connected to the drain of the second P-type transistor MP2 directly through the first through hole TK1, it is possible to realize that the first input terminal Line _ a, the second input terminal Line _ B, and the output terminal Line _ out are disposed between two sets of transistors, the size of nor gate is reduced, and integration is facilitated.

Alternatively, referring to fig. 5, the first metal layer further includes a power supply electrode VDD electrically connected to the source of the first P-type transistor MP1 and a ground electrode GND electrically connected to the source of the first N-type transistor MN1 and the source of the second N-type transistor MN2.

With continued reference to fig. 5, the dual aluminum gate nor further comprises: a plurality of first substrate contact holes CK1 formed in the substrate and near one side of the source of the first P-type transistor; a plurality of second substrate contact holes CK2 formed in the substrate and adjacent to one side of the drain of the second P-type transistor; a plurality of third substrate contact holes CK3 formed in the substrate and near one side of the source of the first N-type transistor; a plurality of fourth substrate contact holes CK4 formed in the substrate and near a source side of the second N-type transistor; a plurality of fifth substrate contact holes CK5 formed between the first and second substrate contact holes CK1 and CK2, an arrangement direction of the fifth substrate contact holes CK5 being perpendicular to an arrangement direction of the first and second substrate contact holes CK1 and CK2; and a plurality of sixth substrate contact holes CK6 formed between the third and fourth substrate contact holes CK3 and CK4, an arrangement direction of the sixth substrate contact holes CK6 being perpendicular to an arrangement direction of the third and fourth substrate contact holes CK3 and CK 4.

The first metal layer further includes a first substrate lead electrically connecting the substrate with the power supply electrode VDD through the first, second, and fifth substrate contact holes CK1, CK2, and CK5, and a second substrate lead electrically connecting the substrate with the ground electrode GND through the third, fourth, and sixth substrate contact holes CK3, CK4, and CK 6.

With the above arrangement, since the first metal layer and the second metal layer are provided, and particularly the first input terminal lead Line _ a, the second input terminal lead Line _ B, and the output terminal lead Line _ out can be provided in the middle region of the layout, for example, in the layout shown in fig. 3 to 5, the two PMOS transistors are provided above the layout, the two NMOS transistors are provided below the layout, and the input/output terminal leads are provided in the middle region of the layout, that is, the region between the two PMOS transistors and the two NMOS transistors, rather than the input/output terminals provided at the upper and lower ends of the layout as in the prior art (refer to fig. 1), it is possible to provide the fifth substrate contact hole CK5 between the first substrate contact hole CK1 and the second substrate contact hole CK2, and provide the sixth substrate contact hole CK6 between the third substrate contact hole CK3 and the fourth substrate contact hole CK4, which can increase the number of substrate contact holes relative to the prior art, thereby making the substrate contact more sufficient and avoiding the electric leakage.

The utility model discloses to present problem provides a two aluminium bars NOR gate. The double-aluminum-gate NOR gate comprises a first metal layer, a second metal layer and an insulating layer arranged between the first metal layer and the second metal layer, wherein the first metal layer electrically connects a grid electrode of a first P-type transistor with a grid electrode of a first N-type transistor, and the second P-type transistor is electrically connected with a grid electrode of a second N-type transistor; the second metal layer is used as a connecting wire for connecting the drain electrode of the second P-type transistor, the drain electrode of the first N-type transistor and the drain electrode of the second N-type transistor, and is used as a first input end lead, a second input end lead and an output end lead, so that orthographic projections of all layers of metal connecting wires on the substrate can be overlapped, the length of a signal wire is shortened, meanwhile, the use of active area 'wire jumping' can be avoided, the area of a source and drain area is reduced, node parasitic capacitance and resistance are reduced, the integration level of the device is improved, and the device has wide application prospect.

Obviously, the above embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it is obvious for a person skilled in the art to make other variations or changes based on the above description, and all embodiments cannot be exhaustive here, and all obvious variations or changes that belong to the technical solutions of the present invention are still in the scope of protection of the present invention.

Claims (9)

1. A kind of double aluminium gate NOR gate, including the first P type transistor formed on the basis of the substrate, the second P type transistor, the first N type transistor and the second N type transistor, characterized by that, also include: a first metal layer, a second metal layer, and an insulating layer disposed between the first metal layer and the second metal layer, wherein:

a first metal layer including a first sub-portion electrically connecting a gate of the first P-type transistor with a gate of the first N-type transistor and a second sub-portion electrically connecting a gate of the second P-type transistor with a gate of the second N-type transistor,

a second metal layer including a third sub-section serving as a connection line connecting the drain of the second P-type transistor, the drain of the first N-type transistor, and the drain of the second N-type transistor, and a fourth sub-section serving as a first input terminal lead, a second input terminal lead, and an output terminal lead.

2. The dual aluminum gate NOR gate of claim 1 wherein the insulating layer has a first via and a second via disposed therein, wherein

An orthographic projection of a drain electrode of the second P-type transistor on the substrate covers an orthographic projection of the first through hole on the substrate, an orthographic projection of a drain electrode of the second N-type transistor on the substrate covers an orthographic projection of the second through hole on the substrate,

the third sub-portion is electrically connected to the drain of the second P-type transistor through the first via and electrically connected to the drain of the second N-type transistor through the second via,

an orthographic projection of the second sub-portion on a substrate overlaps an orthographic projection of the third sub-portion on the substrate.

3. The dual aluminum gate NOR gate of claim 2 wherein the portion of the fourth sub-section that serves as the output lead is electrically connected to the drain of the second P-type transistor through the first via.

4. The dual aluminum gate NOR gate of claim 3 wherein the portion of the fourth sub-section that serves as the output lead is disposed between the second P-type transistor and the second N-type transistor.

5. The dual aluminum gate NOR gate of claim 1 wherein the insulating layer further comprises a third via and a fourth via, wherein the third via and the fourth via are formed in the insulating layer

An orthographic projection of the second sub-portion on the substrate covers an orthographic projection of the third through hole on the substrate, an orthographic projection of the first sub-portion on the substrate covers an orthographic projection of the fourth through hole on the substrate,

a portion of the fourth sub-portion functioning as a first input terminal lead is electrically connected to the second sub-portion through the third through hole, and an orthogonal projection of the portion of the fourth sub-portion functioning as the first input terminal lead on the substrate overlaps with an orthogonal projection of the first sub-portion on the substrate,

a portion of the fourth sub-portion serving as a second input terminal lead is electrically connected to the first sub-portion through the fourth through hole.

6. The dual aluminum gate NOR gate of claim 5, wherein the portions of the fourth sub-section that serve as the first input terminal lead and the second output terminal lead are disposed between the first P-type transistor and the first N-type transistor.

7. The dual aluminum gate NOR gate of claim 1 wherein the first metal layer further comprises an electrical source and a ground, wherein

The electric source electrode is electrically connected with the source electrode of the first P type transistor, and the ground electrode is electrically connected with the source electrode of the first N type transistor and the source electrode of the second N type transistor.

8. The dual aluminum gate NOR gate of claim 7 further comprising:

a plurality of first substrate contact holes formed in the substrate on a side close to the source of the first P-type transistor;

a plurality of second substrate contact holes formed in the substrate at a side close to the drain of the second P-type transistor;

a plurality of third substrate contact holes formed in the substrate on a side close to the source of the first N-type transistor;

a plurality of fourth substrate contact holes formed in the substrate on a side close to the source of the second N-type transistor;

a plurality of fifth substrate contact holes formed between the first substrate contact holes and the second substrate contact holes, the arrangement direction of the fifth substrate contact holes being perpendicular to the arrangement direction of the first substrate contact holes and the second substrate contact holes, respectively; and

a plurality of sixth substrate contact holes formed between the third substrate contact holes and the fourth substrate contact holes, the sixth substrate contact holes being arranged in a direction perpendicular to the arrangement direction of the third substrate contact holes and the fourth substrate contact holes, respectively,

the first metal layer further comprises a first substrate lead and a second substrate lead, wherein

The first substrate lead electrically connects the substrate with the power supply through the first substrate contact hole, the second substrate contact hole, and the fifth substrate contact hole,

the second substrate lead connects the substrate to the ground through the third substrate contact hole, the fourth substrate contact hole, and the sixth substrate contact hole.

9. The dual aluminum gate NOR gate of claim 1 wherein the insulating layer comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

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