CN112420606B - Preparation method of array substrate and array substrate - Google Patents

Preparation method of array substrate and array substrate Download PDF

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Publication number
CN112420606B
CN112420606B CN202011216501.5A CN202011216501A CN112420606B CN 112420606 B CN112420606 B CN 112420606B CN 202011216501 A CN202011216501 A CN 202011216501A CN 112420606 B CN112420606 B CN 112420606B
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layer
etching
conductive film
array substrate
conductive
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CN112420606A (en
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胡小波
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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Abstract

The application discloses a preparation method of an array substrate and the array substrate, which comprises the following steps: forming a conductive layer above a substrate, wherein the conductive layer comprises a first conductive film, a metal layer and a second conductive film which are sequentially stacked; forming a first etching blocking layer on a central portion of the second conductive film; forming a second etching shielding layer on the pre-etching part of the second conductive film, wherein a gap is formed between the second etching shielding layer and the pre-etching part; etching the pre-etched portion of the conductive layer; and removing the first etching blocking layer and the second etching blocking layer. When the conducting layer is etched, the etching liquid enters the gap, and the etching liquid etches the pre-etched part from the surface and the side face of the second conducting film simultaneously, so that the pre-etched part of the second conducting film can be completely etched, and the edge part of the second conducting film is prevented from extending out of the metal layer to form a cap peak-shaped structure.

Description

Preparation method of array substrate and array substrate
Technical Field
The application relates to the technical field of display, in particular to a preparation method of an array substrate and the array substrate.
Background
With the development of display technology, in order to improve the size, resolution, and refresh rate of the display panel, a material with better conductivity, such as copper, is generally used to replace aluminum as a conductive metal material to form a metal layer on the array substrate.
When the copper film is used as the metal layer on the array substrate, the adhesive force of the metal layer, the substrate, the insulating layer covering the metal layer and other film layers is poor. In order to prevent the metal layer formed of copper from separating from the substrate and the insulating layer, it is proposed in the industry to provide a conductive layer having a multilayer laminated structure, for example, the conductive layer is formed of a first conductive film, a metal layer, and a second conductive film which are laminated in this order, and the first conductive film and the second conductive film have strong adhesion to the substrate and the insulating layer.
However, in the manufacturing process of the array substrate, when the conductive layer including the multilayer laminated structure is formed by etching, due to different etching degrees of the second conductive film and the copper film by the etching solution, an edge portion of the second conductive film protrudes out of the metal layer to form a hat brim structure, which easily causes poor coverage of the insulating layer on the metal layer, thereby increasing the electrostatic risk of the display panel.
Disclosure of Invention
The embodiment of the application provides a preparation method of an array substrate and the array substrate, which are used for solving the technical problem that in the preparation process of the existing array substrate, when a conducting layer comprising a multilayer laminated structure is formed by etching, the edge part of a second conducting film extends out of a metal layer to form a cap-brim-shaped structure, and the cap-brim-shaped structure easily causes poor coverage of the insulating layer on the metal layer, so that the electrostatic risk of a display panel is increased.
In order to solve the problems, the technical scheme provided by the invention is as follows:
in a first aspect, the present application provides a method for manufacturing an array substrate, including the following steps:
s10, forming a conducting layer above a substrate, wherein the conducting layer comprises a first conducting film, a metal layer and a second conducting film which are sequentially stacked;
s20, forming a first etching blocking layer on the central part of the second conductive film;
s30, forming a second etching shielding layer on a pre-etching part of the second conductive film, wherein the pre-etching part is positioned on the side part of the central part, the side surface of the second etching shielding layer is abutted against the side surface of the first etching shielding layer, and a gap is formed between the second etching shielding layer and the pre-etching part;
s40, etching the pre-etched part of the conductive layer, wherein in the etched conductive layer, the orthographic projection of the metal layer on the substrate covers the orthographic projection of the second conductive film on the substrate;
and S50, removing the first etching blocking layer and the second etching blocking layer.
In some embodiments, in the step S30, when the second etching blocking layer is formed, a third etching blocking layer covering the first etching blocking layer is simultaneously formed on the first etching blocking layer.
In some embodiments, after the step S30 and before the step S40, the method for manufacturing an array substrate further includes:
and S60, patterning the second etching blocking layer to expose the edge part of the pre-etched part.
In some embodiments, in step S40, a side surface of the first conductive film, a side surface of the metal layer, and a side surface of the second conductive film are located on the same plane in the first side surface after the conductive layer is etched.
In some embodiments, the material from which the first etch stop layer is made comprises a first etch stop material and an adhesion additive, and the material from which the second etch stop layer is made comprises a second etch stop material.
In some embodiments, the first etch stop material and the second etch stop material are the same material.
In some embodiments, the second etch stop layer has a width of 0.5 to 1.5 micrometers.
In a second aspect, the present application further provides an array substrate, where the array substrate is prepared by the above method for preparing an array substrate, and the array substrate includes:
a substrate base plate;
the conductive layer is arranged above the substrate and comprises a first conductive film, a metal layer and a second conductive film which are sequentially stacked;
wherein an orthographic projection of the metal layer on the substrate covers an orthographic projection of the second conductive film on the substrate.
In some embodiments, the first side surface of the conductive layer is a side surface of the first conductive film, and the side surface of the metal layer and the side surface of the second conductive film are located on the same plane.
In some embodiments, the first edge side comprises a slope sloping downward away from a center of the conductive layer.
The beneficial effects of the invention application are as follows: the first etching shielding layer is utilized to shield the central part of the second conductive film, the second etching shielding layer is formed on the pre-etched part of the second conductive film, when the conductive layer is etched, due to the fact that a gap is formed between the second etching shielding layer and the pre-etched part of the second conductive film, etching liquid can enter the gap, the first etching shielding layer prevents the etching liquid from flowing into the central part, the etching liquid etches the pre-etched part from the surface and the side face of the second conductive film simultaneously, the pre-etched part of the second conductive film can be completely etched, due to the shielding of the second etching shielding layer, the amount of the etching liquid entering the gap is small, the etching liquid on the area, close to the central part, of the pre-etched part is small, the part, corresponding to the first etching shielding layer, of the metal layer is prevented from being etched by the etching liquid, the edge part of the second conductive film extends out of the metal layer to form a hat brim-shaped structure, and the coverage of the insulating layer and the like on the metal layer is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a process for fabricating an array substrate according to the present application;
fig. 2 to 7 are schematic views illustrating a process of manufacturing an array substrate according to an embodiment of the present disclosure;
FIG. 8 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an array substrate according to another embodiment of the present application.
Reference numerals are as follows:
10. an array substrate; 11. a base substrate; 12. a conductive layer; 121. a first conductive film; 122. a metal layer; 123. a second conductive film; 123a, a central portion; 123b, pre-etched portions; 13. a gate electrode 14, an interlayer insulating layer; 15. an active layer 16, a source drain; 17. a planarization layer; 18. a pixel electrode; 20. a first etching barrier layer; 30. a second etching shielding layer; 40. a third etching barrier layer; 50. a void.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. "beneath," "under" and "beneath" a first feature includes the first feature being directly beneath and obliquely beneath the second feature, or simply indicating that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. To simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The invention aims to solve the technical problem that in the preparation process of the existing array substrate, when a conducting layer comprising a multilayer laminated structure is formed by etching, the edge part of a second conducting film extends out of a metal layer to form a cap-brim-shaped structure, and the cap-brim-shaped structure easily causes poor coverage of an insulating layer on the metal layer, so that the electrostatic risk of a display panel is increased.
A method for manufacturing an array substrate, as shown in fig. 1 to 7, includes the following steps:
s10, forming a conductive layer 12 above a substrate 11, wherein the conductive layer 12 includes a first conductive film 121, a metal layer 122, and a second conductive film 123 stacked in sequence;
s20, forming a first etching blocking layer 20 on the central portion 123a of the second conductive film 123;
s30, forming a second etching stop layer 30 on the pre-etched portion 123b of the second conductive film 123, wherein the pre-etched portion 123b is located at a side of the central portion 123a, a side surface of the second etching stop layer 30 abuts against a side surface of the first etching stop layer 20, and a gap 50 is provided between the second etching stop layer 30 and the pre-etched portion 123 b;
s40, etching the pre-etched portion 123b of the conductive layer 12, wherein in the etched conductive layer 12, an orthogonal projection of the metal layer 122 on the substrate 11 covers an orthogonal projection of the second conductive film 123 on the substrate 11;
s50, removing the first etching blocking layer 20 and the second etching blocking layer 30.
It should be noted that, when the first etching blocking layer 20 blocks the central portion 123a of the second conductive film 123, and the second etching blocking layer 30 is formed on the pre-etched portion 123b of the second conductive film 123, when the conductive layer 12 is etched, since the gap 50 is provided between the second etching blocking layer 30 and the pre-etched portion 123b of the second conductive film 123, the etching liquid may enter into the gap 50, the first etching blocking layer 20 blocks the etching liquid from flowing into the central portion 123a, and the etching liquid simultaneously etches the pre-etched portion 123b from both the surface and the side of the second conductive film 123, so that the pre-etched portion 123b of the second conductive film 123 may be completely etched, while due to the blocking of the second etching blocking layer 30, the amount of the etching liquid entering into the gap 50 is small, and the etching liquid on the area on the pre-etched portion 123b closer to the central portion 123a is smaller, so that the portion on the metal layer 122 corresponding to the first etching blocking layer 20 is prevented from being covered by the etching liquid, so that the edge portion of the second conductive film 123 protrudes from the metal layer 122 to form a capping layer 122, and the like.
Referring to fig. 2 to 7, fig. 2 to 7 are schematic views illustrating a manufacturing process of the array substrate 10 according to an embodiment of the present disclosure.
As shown in fig. 2, in step S10, a conductive layer 12 is formed over a substrate 11, wherein the conductive layer 12 includes a first conductive film 121, a metal layer 122, and a second conductive film 123 stacked in sequence.
The forming process of the conductive layer 12 includes: forming a first conductive film 121 over the base substrate 11; forming a metal layer 122 on a surface of the first conductive film 121; a second conductive film 123 is formed on the surface of the metal layer 122, and any side surface of the conductive layer 12 may be a flat surface.
Specifically, the material for preparing the first conductive film 121 and the second conductive film 123 includes one or more of molybdenum, molybdenum titanium, tungsten, tantalum, and the like; the metal layer 122 may be a copper film layer.
As shown in fig. 3, in step S20, the first etching blocking layer 20 is formed on the central portion 123a of the second conductive film 123, the first etching blocking layer 20 has strong adhesion to the second conductive film 123, and there is no gap 50 between the first etching blocking layer 20 and the second conductive film 123, so that the etchant can be prevented from flowing into the surface of the first conductive film 121.
As shown in fig. 4 and 5, fig. 5 is an enlarged schematic view of a in fig. 4, in step S30, a second etching blocking layer 30 is formed on a pre-etched portion 123b of the second conductive film 123, the pre-etched portion 123b is located at a side portion of the central portion 123a, and a gap 50 is provided between the second etching blocking layer 30 and the pre-etched portion 123 b.
Specifically, in the step S30, when the second etching stopper layer 30 is formed, the third etching stopper layer 40 covering the first etching stopper layer 20 is formed on the first etching stopper layer 20 at the same time.
It should be noted that, by using the stack of the third etching blocking layer 40 and the first etching blocking layer 20, the central portion 123a of the second conductive film 123 is better protected from being etched by the etching solution, and meanwhile, the third etching blocking layer 40 and the second etching blocking layer 30 can be integrally formed, so that the etching solution can be prevented from penetrating between the first etching blocking layer 20 and the second etching blocking layer 30.
Specifically, after the step S30 and before the step S40, the method for manufacturing the array substrate 10 further includes:
s60, patterning the second etching blocking layer 30 to expose an edge portion of the pre-etched portion 123 b.
Before the second conductive film 123 is etched, the edge portion of the pre-etched portion 123b is exposed, and the etching solution dropped to the edge portion of the pre-etched portion 123b flows into the gap 50 between the second conductive film 123 and the pre-etched portion 123b, so that sufficient etching solution flows into the gap 50 between the second conductive film 123 and the pre-etched portion 123 b.
Specifically, the preparation material of the first etching blocking layer 20 includes a first etching blocking material and an adhesion additive, and the preparation material of the second etching blocking layer 30 includes a second etching blocking material.
It should be noted that the adhesion of the first etching blocking layer 20 on the second conductive film 123 is enhanced by an adhesion additive, such that no gap 50 exists between the first etching blocking layer 20 and the second conductive film 123, and the adhesion additive may be functionalized alkoxysilane or aqueous acrylic acid.
Further, the first etching shielding material and the second etching shielding material may be the same material, and both the first etching shielding material and the second etching shielding material may be photoresist.
Specifically, the width of the second etching blocking layer 30 is 0.5 to 1.5 micrometers.
In one embodiment, the width of the second etch stop layer 30 is 1 μm.
As shown in fig. 6, in step S40, the pre-etched portion 123b of the conductive layer 12 is etched, and in the etched conductive layer 12, an orthographic projection of the metal layer 122 on the substrate 11 covers an orthographic projection of the second conductive film 123 on the substrate 11, so that an edge of the second conductive film 123 does not protrude out of the metal layer 122 to form a brim-like structure.
In step S40, among the first side surfaces of the conductive layer 12 after etching, the side surface of the first conductive film 121, the side surface of the metal layer 122, and the side surface of the second conductive film 123 are located on the same plane.
In addition, all four side surfaces of the conductive layer 12 may be etched, that is, any one of the side surfaces of the conductive layer 12 after etching is a first side surface, and the side surface of the first conductive film 121, the side surface of the metal layer 122, and the side surface of the second conductive film 123 are located on the same plane.
In one embodiment, the first side surface includes a slope that slopes downwardly away from the center of the conductive layer 12.
Based on the above method for manufacturing the array substrate 10, the present application also provides an array substrate 10, as shown in fig. 8, where the array substrate 10 is manufactured by the method for manufacturing the array substrate 10 according to any of the above embodiments.
The array substrate 10 comprises a substrate 11 and a conductive layer 12 arranged above the substrate 11; the conductive layer 12 includes a first conductive film 121, a metal layer 122, and a second conductive film 123 stacked in this order, and an orthogonal projection of the metal layer 122 on the substrate 11 covers an orthogonal projection of the second conductive film 123 on the substrate 11.
Specifically, of the first side surfaces of the conductive layer 12, the side surface of the first conductive film 121 is flush with the side surface of the metal layer 122 and the side surface of the second conductive film 123.
Note that, each of the four side surfaces of the conductive layer 12 may be a first side surface.
Further, the first side surface includes a slope inclined downward away from the center of the conductive layer 12.
In an embodiment, as shown in fig. 9, the array substrate 10 includes a gate 13 disposed on the substrate 11, an interlayer insulating layer 14 covering the gate 13, an active layer 15 disposed on the interlayer insulating layer 14, a source drain 16 disposed on the interlayer insulating layer 14 and the active layer 15, a flat layer 17 covering the source drain 16, and a pixel electrode 18 disposed on the flat layer 17 and electrically connected to the source drain 16.
The conductive layer 12 may be one or more of the gate 13 and the source/drain 16.
The beneficial effects of the invention are as follows: when the conductive layer 12 is etched, since the gap 50 is provided between the second etching blocking layer 30 and the pre-etched portion 123b of the second conductive film 123, the etching liquid may enter the gap 50, the first etching blocking layer 20 prevents the etching liquid from flowing into the central portion 123a, and the etching liquid simultaneously etches the pre-etched portion 123b from both the surface and the side of the second conductive film 123, the pre-etched portion 123b of the second conductive film 123 may be completely etched, and since the etching liquid is blocked by the second etching blocking layer 30, the amount of the etching liquid entering the gap 50 is small, and the etching liquid on the area of the pre-etched portion 123b closer to the central portion 123a is smaller, so that the portion of the metal layer 122 corresponding to the first etching blocking layer 20 is prevented from being etched by the etching liquid, thereby the edge portion of the second conductive film 123 may be prevented from protruding out of the metal layer 122 to form a capping insulating layer 122, and the like of the metal layer 122.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The principle and the implementation of the present application are explained by applying specific examples, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. The preparation method of the array substrate is characterized by comprising the following steps:
s10, forming a conducting layer above a substrate, wherein the conducting layer comprises a first conducting film, a metal layer and a second conducting film which are sequentially stacked;
s20, forming a first etching blocking layer on the central part of the second conductive film;
s30, forming a second etching shielding layer on a pre-etching part of the second conductive film, wherein the pre-etching part is positioned on the side part of the central part, the side surface of the second etching shielding layer is abutted against the side surface of the first etching shielding layer, and a gap is formed between the second etching shielding layer and the pre-etching part;
s40, etching the pre-etched part of the conductive layer, wherein in the etched conductive layer, the orthographic projection of the metal layer on the substrate covers the orthographic projection of the second conductive film on the substrate, so that the edge of the second conductive film does not extend out of the metal layer to form a cap-brim-shaped structure;
and S50, removing the first etching blocking layer and the second etching blocking layer.
2. The method for manufacturing an array substrate according to claim 1, wherein in the step S30, a third etching stop layer covering the first etching stop layer is formed on the first etching stop layer at the same time as the second etching stop layer is formed.
3. The method for manufacturing an array substrate according to claim 1, wherein after the step S30 and before the step S40, the method further comprises:
and S60, patterning the second etching blocking layer to expose the edge part of the pre-etched part.
4. The method of claim 1, wherein in the step S40, of the first side surfaces of the etched conductive layers, the side surfaces of the first conductive film, the side surfaces of the metal layer and the second conductive film are located on the same plane.
5. The method of claim 1, wherein the first etching mask layer is made of a material including a first etching mask material and an adhesion additive, and the second etching mask layer is made of a material including a second etching mask material.
6. The method of claim 5, wherein the first etching mask material and the second etching mask material are the same material.
7. The method for manufacturing an array substrate of claim 1, wherein the width of the second etching blocking layer is 0.5 to 1.5 μm.
8. An array substrate manufactured by the method of manufacturing an array substrate according to any one of claims 1 to 7, the array substrate comprising:
a substrate base plate;
the conductive layer is arranged above the substrate and comprises a first conductive film, a metal layer and a second conductive film which are sequentially stacked;
wherein an orthographic projection of the metal layer on the substrate covers an orthographic projection of the second conductive film on the substrate.
9. The array substrate of claim 8, wherein, of the first side surfaces of the conductive layers, the side surface of the first conductive film is in the same plane as the side surface of the metal layer and the side surface of the second conductive film.
10. The array substrate of claim 9, wherein the first edge side comprises a slope sloping downward away from a center of the conductive layer.
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