JP2010212308A - Wiring structure, liquid crystal display having the same, and wiring manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a highly reliable wiring circuit which hardly causes wire breaking even if wiring is made finer and more complicated. <P>SOLUTION: A wring structure 1 includes a semiconductor layer 10 arranged on a substrate 9 carrying gate electrodes 17, 17b, and 17c, a second interlayer dielectric 13 arranged above the substrate 9 carrying the gate electrodes 17, 17b, and 17c and the semiconductor layer 10, and wiring 18 arranged on the second interlayer dielectric 13. The semiconductor layer 10 and the wiring 18 are electrically connected in a contact hole 15 formed on the second interlayer dielectric 13, which is made of a photosensitive resin material. The contact hole 15 is filled with conductive fine grains 16 with which the semiconductor layer 10 is electrically connected to the wiring 18. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring structure in which a contact hole is provided in an insulating film covering a substrate on which a plurality of wirings are arranged, a liquid crystal display device including the wiring structure, and a wiring manufacturing method.

  In the electrode wiring board constituting the liquid crystal display panel, conduction between the wirings formed through the insulating layer is performed through a contact hole formed in the insulating layer.

  By the way, in recent years, various developments have been made on liquid crystal display devices in order to cope with higher functionality and lower power consumption, and accordingly, higher density of wiring and development of wiring structures are progressing. . For this reason, since the wiring formed on an electrode wiring board is thin and increases, an unevenness | corrugation will arise on the surface of this electrode wiring board. Various problems occur due to the unevenness. For example, if a wiring is formed at a step portion, disconnection is likely to occur, causing a problem that the reliability as a circuit is remarkably lowered.

  Thus, several techniques have been proposed as techniques for suppressing the disconnection of the wiring due to the unevenness generated on the surface of the electrode wiring board as described above.

  For example, Patent Document 1 describes a method for manufacturing a semiconductor device in which ITO is formed by spin coating on an insulating film in which contact holes and steps are formed. According to Patent Document 1, since ITO is thickly stacked on the contact portion and the step portion, the contact portion and the step portion can be flattened. Thereby, the disconnection of the wiring resulting from the unevenness | corrugation which arises in a contact part or a level | step difference part can be reduced.

  Patent Document 2 discloses that in order to improve step coverage, a metal wiring is formed in a through hole formed in an interlayer insulating film, and the through hole is filled with a conductive coating material. . As a result, the level difference caused by the through hole can be reduced, the unevenness on the surface of the interlayer insulating film due to the through hole can be reduced, and the disconnection of the wiring due to the unevenness can be reduced.

  In the method for manufacturing a wiring substrate for liquid crystal display disclosed in Patent Document 3, the surface of an interlayer insulating layer made of an insulating material such as an acrylic resin is subjected to water repellent processing. Then, a recess is formed around the contact hole provided in the interlayer insulating layer. Then, a technique for forming a conductive material on the recess and the side and bottom portions of the contact hole by filling the contact hole with a coating-type conductive material such as ITO (indium tin oxide) is disclosed. Yes.

  Patent Document 4 discloses a method of forming a contact hole in an interlayer insulating film made of an organic insulating film, filling the contact hole with conductive fine particles, and then forming a wiring in the contact hole.

  Patent Document 5 discloses a liquid crystal display device in which a through hole is formed in a protective insulating film made of photosensitive SOG, and a pixel electrode and a covering of a wiring terminal are formed by the through hole.

JP-A-1-241150 (published September 26, 1989) Japanese Patent Laid-Open No. 61-32443 (released on February 15, 1986) JP 2004-53957 A (published February 19, 2004) JP 2005-39261 A (published February 19, 2004) JP 2003-98548 A (published on February 19, 2004)

  The semiconductor device of Patent Document 1 will be described with reference to FIG.

  FIG. 5 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

  As shown in FIG. 5, the ITO 107 is formed so as to flatten the step of the base of the ITO 107. However, for example, the ITO 107 is thickened at a deep base step like the region D shown in FIG. For this reason, when the ITO 107 is patterned, if the ITO 107 is etched in order to remove the ITO 107 in unnecessary regions, the ITO 107 may not be removed in the thick region, and may remain. Further, if the etching time is extended so as not to leave a thick ITO 107 film, it is necessary to increase the resist for forming the wiring 108 formed on the upper layer of the ITO 107. If the resist is thickened, the wiring 108 cannot be formed thin in the photolithography process. When the wiring 108 becomes thick, there arises a problem that the circuit area increases. That is, the technique disclosed in Patent Document 1 cannot achieve high definition of the circuit.

  Further, although the technique of Patent Document 2 can reduce the unevenness of the surface of the interlayer insulating film due to the through hole and reduce the disconnection of the wiring due to the unevenness, the wiring formed on the substrate is particularly effective. The flattening of the unevenness generated on the insulating film is not considered. For this reason, in the technique of Patent Document 2, since the wiring may be disconnected due to the unevenness caused by the wiring of the interlayer insulating film, the reliability of the circuit is lowered.

  In the technique of Patent Document 3, contact hole coverage is not considered. In addition, when the contact hole has a tapered shape, there is a problem that, when the ITO film formed in the contact hole is disconnected, conduction cannot be obtained.

  In the material used for the interlayer insulating film of Patent Document 4, the surface of the interlayer insulating film can be uneven due to the wiring disposed under the interlayer insulating film. If irregularities are formed on the surface of the interlayer insulating film, it may cause a defect such as a short circuit between wirings arranged on the interlayer insulating film.

  In Patent Document 5, coverage is not taken into consideration, and there is a problem that coverage in a through hole is deteriorated.

  As described above, in any of the above-mentioned patent documents, since the surface of the interlayer insulating film is more or less uneven, when the wiring is made high definition, the wiring becomes thin and the step portion This causes the problem of easy disconnection.

  Moreover, due to the irregularities on the surface of the interlayer insulating film, a short circuit occurs between the wirings formed on the surface of the interlayer insulating film, resulting in a problem that the reliability of the circuit is lowered.

  Here, the problem that a short circuit occurs between the wirings arranged on the surface of the interlayer insulating film due to the formation of the concavo-convex shape on the surface of the interlayer insulating film forming the contact hole will be described with reference to FIGS. explain.

  FIG. 6 is a plan view showing a configuration of a conventional wiring structure. FIG. 7 is a sectional view taken along line B-B ′ shown in FIG. 6. FIG. 8 is a cross-sectional view showing a state in the middle of manufacturing the wiring structure shown in FIGS.

  An island-shaped semiconductor layer 110 is disposed on the substrate 109 of the wiring structure 100. A plurality of gate electrodes 117a, 117b, and 117c are disposed on the substrate 109 through a gate insulating film (not shown). The distance between the gate electrodes 117a and 117b (arrow e in FIGS. 6 and 7) is narrower than the distance between the gate electrodes 117b and 117c (arrow f in FIGS. 6 and 7).

  An interlayer insulating film 113 is formed on the gate insulating film, the semiconductor layer 110, and the gate electrodes 117a, 117b, and 117c. A contact hole 115 is formed in the interlayer insulating film 113 on the semiconductor layer 110. A wiring 118 is formed so as to cover the contact hole 115. The wiring 118 and the semiconductor layer 110 are connected at the bottom of the contact hole 115.

  Here, a step is formed in the region E which is the surface region of the interlayer insulating film 113 corresponding to between the gate electrodes 117a and 117b and the region F which is the surface region of the interlayer insulating film 113 corresponding to between the gate electrodes 117b and 117c. Has been. The step in the region E is a step due to the gate electrodes 117a and 117b, and the step in the region F is a step due to the gate electrodes 117b and 117c.

  Since the distance between the gate electrodes 117a and 117b is narrower than the distance between the gate electrodes 117b and 117c, the step in the region E is formed deeper than the step in the region F. For this reason, an etching residue is likely to occur in the step of the region E when the wiring 118 is patterned.

  8A and 8B, in order to pattern the wiring 118, a conductive film 118a is stacked over the interlayer insulating film 113 including the contact hole 115, and a mask is formed on the conductive film 118a in a region where the wiring 118 is to be formed. A resist 119 is formed.

Here, the conductive film 118a has unevenness on the surface along the unevenness of the lower interlayer insulating film 113. For this reason, a level | step difference can also be made in the area | region laminated | stacked on the area | regions E and F of the interlayer insulation film 113 of the electrically conductive film 118a. And since the level | step difference of the area | region E is formed deeper than the level | step difference of the area | region F,
The film thickness of the conductive film 118a stacked on the region E (arrow G in FIG. 8) is different from the film thickness of the conductive film 118a stacked on the area F (arrow H in FIG. 8) and other conductive films 118a. It is thicker than the area.

  Therefore, when an unnecessary portion of the conductive film 118a is removed by etching to form the wiring 118, the conductive film 118b remains as an etching residue in the region E as shown in FIGS. The conductive film 118b is short-circuited between the wirings 128 shown in FIG. 6, which causes a reduction in circuit reliability.

  In view of the above, the object of the present invention is to flatten the wiring formation surface in the interlayer insulating film and the contact hole portion, thereby realizing a highly reliable wiring circuit in which disconnection hardly occurs even if the wiring is made high definition. A wiring structure, a liquid crystal display device including the wiring structure, and a wiring manufacturing method are provided.

  In order to solve the above problems, a wiring structure according to the present invention is arranged on a first electrode arranged on a substrate on which a plurality of wirings are arranged, and on a substrate on which the wiring and the first electrode are arranged. A wiring comprising an insulating layer and a second electrode disposed on the insulating layer, wherein the first electrode and the second electrode are electrically connected in a contact hole formed in the insulating layer The insulating layer is made of a photosensitive resin material, and the contact hole is filled with conductive fine particles. The conductive fine particles allow the first electrode, the second electrode, Are electrically connected.

  In order to solve the above-described problem, the wiring manufacturing method of the present invention includes a first electrode wiring step in which a first electrode is disposed on a substrate on which a plurality of wirings are disposed, and an upper layer of the first electrode. A contact hole forming step of applying a solution in which a photosensitive resin material is dispersed, laminating an insulating film made of the photosensitive resin material, and then forming a contact hole for exposing the first electrode to the insulating film And forming a conductive fine particle in the contact hole, and forming a second electrode that covers the contact hole and is electrically connected to the conductive fine particle filled in the contact hole. And a second electrode forming step.

  Here, in general, the photosensitive resin material is used in a liquid state.

  Therefore, according to the above configuration, since the insulating layer is made of a photosensitive resin material, when the insulating layer is formed of the photosensitive resin material, the unevenness caused by the plurality of wirings and the first electrode formed on the substrate Filled with photosensitive resin material. Thereby, the insulating film can be flattened by completely filling the unevenness on the substrate.

  In addition, since the conductive fine particles are filled in the contact holes, it is possible to flatten the wiring formation surface in the contact hole formation portion.

  Accordingly, by flattening the contact hole formation portion and the wiring formation surface in the insulating film, it is possible to eliminate the disconnection caused by the unevenness of the wiring formation surface. As a result, it is possible to provide a highly reliable circuit in which the wiring is difficult to be disconnected even when the wiring is refined.

  Further, by flattening the contact hole forming portion and the wiring formation surface in the insulating film, the film thickness of the contact hole forming portion and the wiring film to be the second electrode formed on the insulating film can be made constant. Therefore, when etching the wiring film and patterning the second electrode, there is no etching residue caused by the unevenness of the wiring film.

  As described above, since no etching residue occurs, it is possible to avoid a short circuit of the wiring caused by the etching residue, so that the reliability of the wiring can be improved.

  Further, since no etching residue occurs, the etching time for etching the wiring film can be shortened, so that the film thickness of the resist material can be reduced, and as a result, formation of a fine pattern is facilitated.

  If a fine pattern can be easily formed, it is possible to increase the definition of the wiring, so that the wiring can be thinned. As a result, the circuit area can be reduced.

  From the above, according to the wiring structure and the wiring manufacturing method having the above-described configuration, it is possible to realize a highly reliable wiring circuit in which disconnection hardly occurs even if the wiring is highly refined.

  In the wiring structure of the present invention, it is preferable that the distances between the plurality of wirings arranged on the substrate are different, and the film thickness of the insulating layer stacked between the plurality of wirings is equal.

  With the above structure, even when a plurality of wirings with various distances are arranged on the substrate, unevenness due to the plurality of wirings is not formed on the surface of the insulating film. For this reason, even if a wiring is formed on the insulating film, it is possible to suppress the occurrence of defects in the formed wiring. For this reason, a highly reliable wiring structure can be configured.

  In the wiring structure of the present invention, it is preferable that the bottom portion of the contact hole and the area of the opening portion of the contact hole are equal.

  With the above configuration, the area where the contact hole is formed can be reduced as compared with the case where the side surface of the contact hole is tapered. For this reason, it can suppress that a circuit becomes large.

  The liquid crystal display device of the present invention preferably includes a liquid crystal display panel including a TFT element substrate having the wiring structure and a counter substrate disposed to face the TFT element substrate.

  With the above configuration, the circuit area of the TFT element substrate can be reduced, so that the frame of the liquid crystal display panel can be reduced. For this reason, in addition to the effect which the above-mentioned reliability improves, size reduction of a liquid crystal display device can be performed.

  The wiring structure of the present invention includes a first electrode disposed on a substrate on which a plurality of wirings are disposed, an insulating layer disposed on the substrate on which the wiring and the first electrode are disposed, and the insulating layer on the insulating layer. A wiring structure in which the first electrode and the second electrode are electrically connected within a contact hole formed in the insulating layer, wherein the insulating layer includes: The contact hole is filled with conductive fine particles, and the first electrode and the second electrode are electrically connected by the conductive fine particles.

  Further, the wiring manufacturing method of the present invention includes a first electrode wiring step in which a first electrode is disposed on a substrate on which a plurality of wirings are disposed, and a solution in which a photosensitive resin material is dispersed in the upper layer of the first electrode. And laminating an insulating film made of the photosensitive resin material, and then forming a contact hole for exposing the first electrode in the insulating film, and conducting the conductive material in the contact hole. A conductive fine particle forming step for filling the conductive fine particles, and a second electrode forming step for forming a second electrode that covers the contact hole and is electrically connected to the conductive fine particles filled in the contact hole. .

  As a result, there is an effect that it is possible to realize a highly reliable wiring circuit in which disconnection hardly occurs even if the wiring is highly refined.

FIG. 3 is a sectional view taken along line A-A ′ shown in FIG. 2. It is a top view showing the mode of the wiring structure concerning one embodiment of the present invention. (A) is sectional drawing showing a mode that the patterning of the several gate electrode and the 1st interlayer insulation film were laminated | stacked, (b) laminated | stacked the 2nd interlayer insulation film in (a), and was a 2nd interlayer insulation film It is sectional drawing showing a mode that the contact hole was formed in. (C) is sectional drawing showing a mode that the barrier metal and electroconductive fine particle were laminated | stacked on (b), (d) represents a mode that the unnecessary part was removed among the electroconductive fine particles of (c). (E) is sectional drawing showing a mode that the electrically conductive fine particle was laminated | stacked on the barrier metal of (d), and electroconductive fine particles, and also a resist was patterned on the electrically conductive film, (f) is the electrically conductive film of (e). It is sectional drawing showing a mode that the wiring was patterned by etching. It is sectional drawing showing the mode of the wiring structure which concerns on one Embodiment of this invention. It is sectional drawing showing the mode of the conventional semiconductor device. It is a top view showing the mode of the conventional wiring structure. FIG. 7 is a cross-sectional view taken along line B-B ′ shown in FIG. 6. FIG. 8 is a cross-sectional view illustrating a manufacturing process of the wiring structure illustrated in FIGS. 6 and 7.

  Hereinafter, embodiments of the present invention will be described in detail.

  FIG. 2 is a plan view showing the configuration of the wiring structure 1 (wiring structure) according to the embodiment of the present invention. FIG. 1 is a cross-sectional view taken along line A-A ′ shown in FIG. 2.

  The wiring structure 1 can be used for a wiring substrate in which electrical connection between electrodes and electrodes is achieved by contact holes. For example, the wiring structure 1 can be applied to a wiring substrate used in a semiconductor device or a liquid crystal display device.

  In the present embodiment, a case where the wiring structure 1 according to one embodiment of the present invention is applied to a semiconductor substrate such as a TFT substrate will be described.

  On the substrate 9 of the wiring structure 1, an island-shaped semiconductor layer 10 (first electrode) serving as an active layer is disposed. A gate insulating film 11 is stacked on the substrate 9 and the semiconductor layer 10. Further, a plurality of gate electrodes 17 a, 17 b, and 17 c (wiring) are arranged on the substrate 9 through the gate insulating film 11. The distance between the gate electrodes 17a and 17b (arrow p in FIGS. 1 and 2) is narrower than the distance between the gate electrodes 17b and 17c (arrow q in FIGS. 1 and 2).

  On the gate electrodes 17a, 17b, and 17c and the gate insulating film 11, a first interlayer insulating film 12 having a single layer or a stacked structure of an insulating film containing silicon (for example, SiO2, SiN, SiNO) is stacked. . A second interlayer insulating film 13 (insulating layer) made of a photosensitive resin material is laminated on the first interlayer insulating film 12. Examples of the photosensitive resin material used for the second interlayer insulating film 13 include a photosensitive transparent acrylic resin (a mixture of an acrylic resin and a naphthoquinone photosensitive agent).

  An opening is formed in the gate insulating film 11, the first interlayer insulating film 12, and the second interlayer insulating film 13 on the semiconductor layer 10. This opening is a contact hole 15.

  A barrier metal 14 is formed on the surface of the second interlayer insulating film 13 so as to cover the peripheral portion of the contact hole 15, the side surface inside the contact hole 15, and the bottom. That is, the barrier metal 14 is in contact with the semiconductor layer 10 at the bottom surface of the contact hole 15. Then, conductive fine particles 16 are formed on the barrier metal 14 and in the contact holes 15. Further, a wiring 18 (second electrode) is formed on the barrier metal 14 and the conductive fine particles 16.

  The wiring 18 is electrically connected to the semiconductor layer 10 through the conductive fine particles 16 and the barrier metal 14 inside the contact hole 15. A plurality of wirings 28 are formed on the second interlayer insulating film 13 in the same process as the wirings 18. Each of the plurality of wirings 28 is arranged so as to intersect with each of the gate electrodes 17a, 17b, and 17c when the wiring structure 1 is viewed in plan.

  On the surface of the first interlayer insulating film 12, the gate electrodes 17a, 17b and 17c covered by the first interlayer insulating film 12, the gate insulating film 11, the semiconductor layer 10 formed under the gate insulating film 11, and the like An uneven shape is formed along the uneven shape of the base.

  Here, the second interlayer insulating film 13 formed on the first interlayer insulating film 12 is made of a photosensitive resin material, and the photosensitive resin material is generally used in a liquid state.

  For this reason, the second interlayer insulating film 13 can be patterned by photolithography. For this reason, when the second interlayer insulating film 13 is formed with this photosensitive resin material, the irregularities caused by the gate electrodes 17a, 17b, and 17c formed on the substrate 9 are filled with the photosensitive resin material dispersed in the solution. . Thereby, the second interlayer insulating film 13 can be planarized by completely filling the unevenness on the substrate 9.

  That is, the film thickness of the second interlayer insulating film 13 (arrow P in FIG. 1) formed in a region where the distance between the wirings is narrow, such as between the gate electrodes 17a and 17b, and between the gate electrodes 17b and 17c. The film thickness (arrow Q in FIG. 1) of the second interlayer insulating film 13 formed in a region where the distance between the wirings is relatively wide is substantially equal.

  In addition, since the liquid conductive material 16 is filled in the contact hole 15, the wiring 18 formed in the contact hole 15 forming portion can be flattened.

  Therefore, by flattening the wiring 18 formed in the second interlayer insulating film 13 and the contact hole 16, disconnection of the wiring 18 and the wiring 28 can be prevented, so that the wirings 18 and 28 can be made thinner. For this reason, it is possible to provide a highly reliable circuit that is difficult to be disconnected even if the wirings 18 and 28 have high definition.

  Further, by planarizing the second interlayer insulating film 13 and the wiring 18, the film thickness of the second interlayer insulating film 13 and the wiring 18 can be made constant. For this reason, when the conductive film to be the wiring 18 is patterned, no etching residue due to the unevenness of the second interlayer insulating film 13 is generated.

  As described above, the etching residue of the conductive film to be the wiring 18 does not occur on the second interlayer insulating film 13, so that it is possible to avoid the wiring 28 from being short-circuited due to the etching residue. For this reason, the reliability of the wirings 18 and 28 can be improved.

  Further, since no etching residue is generated on the second interlayer insulating film 13, the etching time for patterning the wiring 18 by etching can be shortened. For this reason, the film thickness of the resist material for patterning the wiring 18 can be reduced, and as a result, a fine pattern can be easily formed.

  If a fine pattern can be easily formed, it is possible to increase the definition of the wiring formed on the wirings 18 and 28, so that the wirings 18 and 28 can be thinned. As a result, the circuit area can be reduced.

  As described above, according to the wiring structure 1, it is possible to realize a highly reliable wiring circuit in which disconnection hardly occurs even if the wiring 18.28 has a high definition.

  Further, since the second interlayer insulating film 13 is made of a photosensitive resin material and the film thickness can be easily adjusted, the parasitic capacitance between the gate electrodes 17a, 17b, and 17c and the wiring 18 is easily reduced. be able to. When the parasitic capacitance between the gate electrodes 17a, 17b, and 17c and the wiring 18 is large, by increasing the film thickness of the second interlayer insulating film 13, the gate electrodes 17a, 17b, and 17c and the wiring 18 The parasitic capacitance between them can be reduced. Thus, according to the wiring structure 1, a more reliable wiring circuit can be formed.

  In addition, for example, a contact hole is formed in an interlayer insulating film having a wiring structure made only of an interlayer insulating film made of a general material other than a photosensitive resin material, such as a single layer of SiO or SiN, or a laminated structure of SiO and SiN. Compared with the case of forming, according to the wiring structure 1, the second interlayer insulating film 13 formed on the first interlayer insulating film 12 is made of a photosensitive resin material, and the contact hole 15 is formed by a photolithography process. Therefore, the process can be simplified.

  That is, as an interlayer insulating film other than the photosensitive resin material, as compared with a wiring structure including only an interlayer insulating film of a general material such as a single layer of SiO or SiN or a laminated structure of SiO and SiN. In the wiring structure 1, since the second interlayer insulating film 13 made of a photosensitive resin material is formed on the first interlayer insulating film 12, the thickness of the first interlayer insulating film 12 can be reduced. . As described above, since the first interlayer insulating film 12 is thin, the etching time for removing the first interlayer insulating film 12 formed in the contact hole 15 is shortened when the contact hole 15 is formed. can do.

  Further, as described above, the wiring provided with only an interlayer insulating film made of a general material such as a single layer of SiO or SiN, or a laminated structure of SiO and SiN other than the photosensitive resin material as the interlayer insulating film When a contact hole is formed in an interlayer insulating film having a structure, an interlayer insulating film is formed, and a resist for masking the interlayer insulating film is patterned on the formed interlayer insulating film (resist application, exposure, development) Then, after the unnecessary portion of the interlayer insulating film is removed by etching using the patterned resist as a mask, a step of removing the resist used as the mask of the interlayer insulating film is required.

  On the other hand, in the wiring structure 1, a second interlayer insulating film 13 made of a photosensitive resin material is formed on the first interlayer insulating film 12, and the second interlayer insulating film 13 patterned in the photolithography process is used as a mask. A contact hole 15 is formed by etching an unnecessary portion of the first interlayer insulating film 12. Then, the second interlayer insulating film 13 used as a mask when the first interlayer insulating film 13 is etched is not removed and remains as a part of the interlayer insulating film.

  Thus, according to the structure of the wiring structure 1, since the second interlayer insulating film 13 made of a photosensitive resin material is laminated on the first interlayer insulating film 12, the second interlayer insulating film 13 It can be used as a mask for etching the first interlayer insulating film 12. Then, the second interlayer insulating film 13 used as a mask for the first interlayer insulating film 12 is left as it is as an interlayer insulating film. For this reason, it is not necessary to remove the resist serving as a mask for the first interlayer insulating film 12. That is, according to the wiring structure 1, there is no need to remove the resist that serves as a mask for the first interlayer insulating film 12.

  Here, when a wiring for conducting in the contact hole is formed by, for example, a sputtering method without providing conductive fine particles in the contact hole, the contact hole is formed at the bottom portion in order to improve the coverage of the wiring. It is necessary to make the shape whose inner diameter is widened toward the opening, that is, a tapered shape.

  Thereby, the coverage of the wiring formed in the contact hole can be improved. However, by making the side surface inside the contact hole tapered, the area of the opening of the contact hole is increased and the circuit area is increased. For this reason, it is not suitable for a wiring structure that requires a small circuit area, such as a so-called narrow frame as required in a liquid crystal display device.

  On the other hand, according to the wiring structure 1, the inside of the contact hole 15 is filled with conductive fine particles 16. Since the wiring 18 is electrically connected to the semiconductor layer 10 through the conductive fine particles 16, the coverage of the wiring 18 is prevented from being deteriorated even if the side surface of the contact hole 15 is not tapered. be able to. That is, the contact hole 15 can have a shape in which the area of the opening on the surface of the second interlayer insulating film 13 is substantially equal to the area of the bottom. For this reason, it is not necessary to increase the area of the opening of the contact hole 15 in order to improve the coverage of the wiring 18. As described above, by providing the conductive fine particles 16 inside the contact hole 15, it is possible to improve both the coverage of the wiring 18 and to suppress an increase in circuit area.

  Thus, the circuit area of the TFT element circuit can be reduced by applying the wiring structure 1 to the wiring structure of the TFT element circuit used in the liquid crystal display panel constituting the liquid crystal display device. As described above, according to the wiring structure 1, in addition to the above-described reliability improvement effect, the frame of the liquid crystal display panel can be reduced, so that the liquid crystal display device can be downsized.

  As a wiring circuit to which the wiring structure 1 can be suitably applied, for example, a monolithic (an electronic circuit such as a gate driver or a source driver is formed on the outer periphery of the liquid crystal display region) a display electronic circuit formation region, a display region, or the like Can be mentioned.

  The side surface inside the contact hole 15 may be tapered. What is necessary is just to select suitably according to the circuit board to which the wiring structure 1 which forms the contact hole 15 is applied.

  In addition, when the photosensitive resin material is not used for the second interlayer insulating film, that is, for example, SiO, SiN, or a laminated structure thereof, which is a material other than the photosensitive resin material and is made of a general material. According to the contact hole manufacturing method using only a film as an interlayer insulating film, in order to flatten the unevenness of the surface and reduce the parasitic capacitance between wirings, generally, increasing the film thickness The area becomes large.

  Here, the second interlayer insulating film 13 is made of a photosensitive resin material, and the contact hole 15 can be formed by a photolithography process. Therefore, the reliability of the wiring circuit to which the wiring structure 1 is applied is improved. It is possible to achieve both suppression of an increase in circuit area.

(Production method)
Next, a method for manufacturing the wiring structure 1 will be described with reference to FIGS.

  3A to 3F are cross-sectional views showing the manufacturing process of the wiring structure 1, and FIG. 3A shows the patterning of the gate electrodes 17a, 17b, and 17c and the first interlayer insulating film 12 stacked. It is sectional drawing showing a mode, (b) is sectional drawing showing a mode that the 2nd interlayer insulation film 13 was laminated | stacked on (a), and the contact hole 15 was formed in the 2nd interlayer insulation film 13. FIG.

  FIG. 3C is a cross-sectional view showing a state in which the barrier metal 14 and the conductive fine particles 16 are laminated on FIG. 3B, and FIG. 3D shows an unnecessary portion of the conductive fine particles 16 in FIG. Shows the state of removal. (E) is a sectional view showing a state in which a conductive film 18a is laminated on the barrier metal 14 and the conductive fine particles 16 in (d), and a resist 19 is patterned on the conductive film 18a, and (f) is a diagram (e). It is sectional drawing showing a mode that the electrically conductive film 18a of 1) was etched and the wiring 18 was patterned.

  As shown in FIG. 3A, a semiconductor layer 10 as an active layer is formed on the substrate 9 in an island shape. The semiconductor layer 10 is formed with a thickness of 10 to 300 nm (preferably 30 nm to 100 nm).

  Next, the gate insulating film 11 is formed with a thickness of 5 nm to 300 nm (preferably 10 nm to 150 nm) over the semiconductor layer 10 and the substrate 9.

  Then, a conductive film with a thickness of 50 nm to 1000 nm (preferably 100 nm to 800 nm) is formed over the gate insulating film 11 by a sputtering method. Then, a plurality of gate electrodes 17a, 17b, and 17c are formed by patterning the conductive film on the gate insulating film 11 into a desired shape by a photolithography process.

  Then, the first interlayer insulating film 12 is stacked on the entire surface of the substrate 9 including the gate electrodes 17a, 17b, and 17c and the gate insulating film 11 so as to have a film thickness of 50 nm to 2000 nm (preferably 100 nm to 1500 nm). The first interlayer insulating film 12 is formed of a single layer or a laminated structure of an insulating film containing silicon (for example, SiO2, SiN, SiNO). Here, the first interlayer insulating film 12 stacked on the gate electrodes 17a, 17b, and 17c is formed with uneven shapes along the shapes of the gate electrodes 17a, 17b, and 17c.

  Next, as shown in FIG. 3B, for example, a film thickness of 80 nm to 8000 nm is formed on the first interlayer insulating film 12 so as to be about 1.5 to 4 times the film thickness of the gate electrode. Then, the second interlayer insulating film 13 made of a photosensitive resin is laminated.

  The second interlayer insulating film 13 laminated on the first interlayer insulating film 12 has a film thickness between the gate electrodes 17a and 17b (arrow P in FIG. 3B), which is a region where the distance between the wirings is narrow, and between the wirings. Is equal to the film thickness between the gate electrodes 17b and 17c (arrow Q in FIG. 3B).

  That is, even if the gate electrodes 17a and 17b and the gate electrodes 17b and 17c having different distances between the wirings (arrows p and q in FIG. 3B) are arranged on the substrate 9, the wirings between the wirings (gate electrodes) 17a and 17b and the second interlayer insulating film 13 stacked on the gate electrodes 17b and 17c), no step is formed, and the film thickness can be made equal.

  Thus, the second interlayer insulating film 13 is formed by applying a solution in which a photosensitive resin material such as a photosensitive transparent acrylic resin is dispersed on the first interlayer insulating film 12, for example. Steps due to the gate electrodes 17a, 17b, and 17c of the first interlayer insulating film 12 can be planarized.

  Further, the second interlayer insulating film 13 is exposed by exposing the second interlayer insulating film 13 to a thickness of about 80 nm to 3000 nm (about 1.5 times the thickness of the gate electrode). Since the time is shortened, the effect of improving the throughput of the exposure processing apparatus can be obtained.

  Then, the second interlayer insulating film 13 is patterned by a photolithography process. That is, the surface of the first interlayer insulating film 12 formed under the second interlayer insulating film 13 by forming an opening in a region where the contact hole of the second interlayer insulating film 13 is to be formed by a photolithography process. To expose.

  Next, the first interlayer insulating film 12 whose surface is exposed is removed by an etching process. That is, the contact hole 15 is formed by removing unnecessary portions of the first interlayer insulating film 12 by etching using the patterned second interlayer insulating film 13 as a mask.

  In the present embodiment, the contact hole 15 is formed to electrically connect the semiconductor layer 10 serving as the source / drain region and the wiring 18.

  The contact hole 15 is for electrically connecting a wiring formed in the lower layer of the second interlayer insulating film 13 and a wiring formed in the upper layer of the second interlayer insulating film 13. For this reason, the position where the contact hole 15 is formed is not limited to the semiconductor layer 10 and may be formed, for example, on the gate electrode.

  Thus, since the second interlayer insulating film 13 is made of a photosensitive resin material, the contact hole 15 can be formed by a photolithography process. For this reason, it is easy to adjust or change the size of the contact hole 15.

  Here, when the side surface of the contact hole 15 is tapered, the photolithography is performed so that the area of the bottom of the contact hole 15 and the area of the opening of the surface of the second interlayer insulating film 13 have a desired size. It is necessary to adjust in the process. If the side surface of the contact hole 15 is not tapered, it is not necessary to adjust the area of the bottom of the contact hole 15 and the area of the opening of the surface of the second interlayer insulating film 13, so the process is simplified. be able to.

  Next, the first interlayer insulating film 12 remaining in the contact hole 15 is removed by etching. As a result, the semiconductor layer 10 is exposed on the bottom surface of the contact hole 15. Here, the aspect ratio of the contact hole (depth of the contact hole / diameter of the contact hole) is 0.5 or more.

  Thereby, the effect which prevents the disconnection of the wiring in the contact hole 15 can be acquired more notably. That is, by setting the aspect ratio of the contact hole to 0.5 or more, the disconnection of the wiring inside the contact hole 15 can be further reliably prevented. When the aspect ratio is smaller than 0.5, the possibility of disconnection of the wiring inside the contact is low, so the liquid conductive material in the contact hole may be omitted.

  Then, as shown in FIG. 3C, the barrier metal 14 is formed on the second interlayer insulating film 13 including the contact hole 15 with a film thickness of 50 nm to 1000 nm (preferably 100 nm to 300 nm) by sputtering or the like. To do. As the material of the barrier metal 14, for example, tantalum and its compounds (Ta, TaN, etc.), titanium and its compounds (Ti, TiN, etc.), tungsten and its compounds (W, WN, etc.) can be used.

  Thereby, the barrier metal 14 is formed on the second interlayer insulating film 13 and inside the contact hole 15.

  Next, a liquid material (solution) containing conductive fine particles 16 is spread on the barrier metal 14 by spin coating. As the liquid material containing the conductive fine particles 16, for example, low temperature firing type Ag ink “L-Ag” series manufactured by ULVAC MATERIAL, conductive ink for fine wiring, and the like can be used.

  Then, the liquid material is dried by baking or the like. Thereby, conductive fine particles 16 are formed on the barrier metal 14 including the inside of the contact hole 15. Here, by using the conductive fine particles 16 of the present embodiment, the material of the second interlayer insulating film 13 can be a material having a heat resistant temperature of about 150 ° C., which is a relatively low temperature. That is, as the material of the second interlayer insulating film 13, it is not necessary to use a material having a heat resistant temperature of 400 ° C. or higher, such as the material of the interlayer insulating film disclosed in Patent Document 4.

  Further, since the second interlayer insulating film 13 covering the gate insulating films 17a, 17b and 17c having different distances between the wirings has a flat surface, it is laminated on the upper layer between the wirings of the gate electrodes 17a and 17b. The film thickness of the conductive fine particles 16 (arrow g in FIG. 3C) and the film thickness of the conductive fine particles 16 stacked in the upper layer between the wirings of the gate electrodes 17b and 17c (arrow h in FIG. 3C) Is equivalent to

  Next, as shown in FIG. 3D, the conductive fine particles 16 other than the conductive fine particles 16 formed in the contact holes 15 are removed by performing wet etching. That is, the conductive fine particles 16 formed in the upper layer of the second interlayer insulating film 13 are removed via the barrier metal 14. Thereby, the conductive fine particles 16 are formed on the barrier metal 14 inside the contact hole 15.

  Further, the thickness of the second interlayer insulating film 13 (arrow P in FIG. 3 (d)) formed in a region where the distance between the wirings is narrow, such as between the gate electrodes 17a and 17b, and between the gate electrodes 17b and 17c. Thus, since the film thickness of the second interlayer insulating film 13 formed in the region where the distance between the wirings is relatively wide (arrow Q in FIG. 3D) is almost equal, unnecessary conductive fine particles 16 are surely removed. The remaining etching on the second interlayer insulating film 13 can be prevented. For this reason, the time for etching the conductive fine particles 16 can be shortened.

  Next, as illustrated in FIG. 3E, a conductive film 18 a to be the wiring 18 is formed on the barrier metal 14 including the contact hole 15 with a film thickness of 100 nm to 2000 nm (preferably 500 nm to 1500 nm). Here, the conductive fine particles 16 are selectively disposed in the contact holes 15. For this reason, the conductive film 18 a can satisfactorily coat the step caused by the contact hole 15.

  Further, since the surface of the second interlayer insulating film 13 is flat, there is no unnecessary etching residue of the conductive fine particles 16.

  Further, since the second interlayer insulating film 13 covering the gate insulating films 17a, 17b and 17c having different distances between the wirings has a flat surface, it is laminated on the upper layer between the wirings of the gate electrodes 17a and 17b. The film thickness of the conductive film 18a (arrow i in FIG. 3E) and the film thickness of the conductive film 18a stacked on the upper layer between the wirings of the gate electrodes 17b and 17c (arrow j in FIG. 3C) equal.

  Then, in order to pattern the conductive film 18a, a resist 19 made of, for example, a novolak resist, a chemically amplified resist, or the like is formed on the conductive film 18a in a region where the conductive film 18a is to be left.

  Here, the conductive film 18a is not affected by the unevenness of the gate gate insulating films 17a, 17b, and 17c, and the film thickness is uniformly formed. Therefore, when the conductive film 18a is etched, unnecessary portions of the conductive film 18a are electrically conductive. Etching residue of the film 18a does not occur. Therefore, the time required for etching the conductive film 18a can be shortened. Thereby, the film thickness of the resist 19 can be reduced, and the wiring 18 can be easily miniaturized.

  Next, as shown in FIG. 3F, the conductive film 18a and the barrier metal 14 are etched using the resist 19 as a mask, and the conductive film 18a and the barrier metal 14 are patterned. As a result, the resist 19 and the conductive film 18 a and the barrier metal 14 in a region where the resist 19 is not formed are removed from the second interlayer insulating film 13. Thereby, the wiring 18 is formed in the vicinity of the contact hole 15. Here, since the second interlayer insulating film 13 covering the gate insulating films 17a, 17b, and 17c is formed to have a flat surface, the conductive film 18a and the barrier layer laminated on the upper layer between the wirings of the gate electrodes 17a and 17b. Etching residue of the metal 14 does not occur.

  Since the wiring 18 is formed on the contact hole 15 filled with the conductive fine particles 16, a step caused by the contact hole 15 can be suppressed. That is, since the conductive fine particles 16 are formed in the contact holes 15, the flatness of the surface of the wiring 18 can be improved. Further, since the conductive fine particles 16 are filled in the contact hole 15, it is possible to prevent a gap from being formed between the barrier metal 14 and the wiring 18 in the contact hole 15. For this reason, better conductivity can be ensured between the wiring 18 and the semiconductor layer 10.

  In the present embodiment, a photosensitive resin material is used as the second interlayer insulating film 13 in order to flatten the steps caused by the gate electrodes 17a, 17b, and 17c. For this reason, the second interlayer insulating film 13 can flatten the lower step. For this reason, as shown in FIGS. 3D and 3F, when the film laminated on the second interlayer insulating film 13 is removed by etching or the like, it is generated on the surface of the second interlayer insulating film 13. It is possible to prevent the film from remaining due to the step.

[Second Embodiment]
When the step due to the gate electrodes 17, 17 b, and 17 c is formed on the surface of the second interlayer insulating film 13, the aspect ratio of the shape of the step that suppresses the wiring short circuit is taken into consideration, so that It is also possible to prevent the occurrence of etching residue.

  FIG. 4 is a cross-sectional view illustrating a schematic configuration of the wiring structure 20 (wiring structure) according to the present embodiment.

  The wiring structure 20 is made of the same photosensitive resin material as the second interlayer insulating film 13 of the wiring structure 1 and is different in that the surface has an uneven shape. In FIG. 4, the gate insulating film 11 and the first interlayer insulating film are different. 12 and the barrier metal 14 are omitted.

  On the surface of the second interlayer insulating film 23, a step due to the unevenness of the gate electrodes 17a, 17b, and 17c is formed. On the surface of the second interlayer insulating film 23, a step l is formed between the gate electrodes 17a and 17b. Further, a step m is formed between the gate electrodes 17b and 17c on the surface of the second interlayer insulating film 23.

  Here, the gate electrodes 17a, 17b, and 17c have a thickness of 400 nm, the second interlayer insulating film 23 has a thickness of 1000 nm, and the wirings 18 and 28 have a thickness of 1000 nm.

  When the depth of the step formed on the surface of the second interlayer insulating film 23 (arrow T in FIG. 4) is T, the width of the step (arrow S in FIG. 4) is S, and the aspect ratio is T / S By setting the aspect ratio to 0.5 or less, it is possible to prevent the wiring 28 (see FIG. 2) from being short-circuited.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and can be obtained by appropriately combining technical means disclosed in different embodiments. Embodiments are also included in the technical scope of the present invention.

  The present invention can flatten the surface of an interlayer insulating film covering a plurality of wirings in which contact holes are formed, and improve the contact hole coverage, so that a wiring structure in which a plurality of electrodes and contact holes are formed Applicable to.

1 Wiring structure (wiring structure)
9 Substrate 10 Semiconductor layer (first electrode)
11 Gate insulating film 12 First interlayer insulating film 13 Second interlayer insulating film (insulating layer)
14 Barrier metal 15 Contact hole 16 Conductive fine particles 17, 17b, 17c Gate electrode (wiring)
18 Wiring (second electrode)
18a conductive film 19 resist 20 wiring structure (wiring structure)
23 Second interlayer insulating film (insulating layer)
28 Wiring

Claims (5)

A first electrode disposed on a substrate on which a plurality of wirings are disposed, an insulating layer disposed on the substrate on which the wirings and the first electrode are disposed, and a second electrode disposed on the insulating layer, A wiring structure in which the first electrode and the second electrode are electrically connected in a contact hole formed in the insulating layer,
The insulating layer is made of a photosensitive resin material,
Furthermore, the contact hole is filled with conductive fine particles,
The wiring structure, wherein the first electrode and the second electrode are electrically connected by the conductive fine particles. The distance between the plurality of wirings arranged on the substrate is different,
The wiring structure according to claim 1, wherein the insulating layers stacked between the plurality of wirings have the same thickness.   The wiring structure according to claim 1, wherein a bottom portion of the contact hole and an area of an opening portion of the contact hole are equal.   A liquid crystal display comprising: a TFT element substrate having the wiring structure according to claim 1; and a counter substrate disposed opposite to the TFT element substrate. apparatus. A first electrode wiring step of arranging a first electrode on a substrate on which a plurality of wirings are arranged;
A contact for exposing the first electrode to the insulating film after applying a solution in which a photosensitive resin material is dispersed on the upper layer of the first electrode and laminating an insulating film made of the photosensitive resin material. A contact hole forming step for forming a hole;
Conductive fine particle forming step of filling the contact hole with conductive fine particles,
And a second electrode forming step of forming a second electrode that covers the contact hole and is electrically connected to the conductive fine particles filled in the contact hole.

Images