CN111244108A - Array substrate and preparation method thereof - Google Patents

Array substrate and preparation method thereof Download PDF

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Publication number
CN111244108A
CN111244108A CN202010045338.4A CN202010045338A CN111244108A CN 111244108 A CN111244108 A CN 111244108A CN 202010045338 A CN202010045338 A CN 202010045338A CN 111244108 A CN111244108 A CN 111244108A
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layer
metal layer
substrate
array
hole
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孙正娟
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TCL China Star Optoelectronics Technology Co Ltd
TCL Huaxing Photoelectric Technology Co Ltd
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TCL Huaxing Photoelectric Technology Co Ltd
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Priority to CN202010045338.4A priority Critical patent/CN111244108A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses an array substrate and a preparation method thereof, wherein the array substrate comprises: a substrate; the array layer is arranged on the surface of one side of the substrate; the array layer comprises a source drain electrode layer; wherein, the source drain electrode layer includes: a first metal layer; and the second metal layer is arranged on the surface of one side of the first metal layer, which is far away from the substrate. The invention has the technical effects that the source drain electrode layer adopts a laminated design of two metal layers, the yield of the array substrate is improved, meanwhile, the arrangement of one metal layer is reduced, the usage amount of metal materials is reduced, and the production cost of the array substrate is saved.

Description

Array substrate and preparation method thereof
Technical Field
The invention relates to the field of display, in particular to an array substrate and a preparation method thereof.
Background
As shown in fig. 1, an array substrate (TFT) is mainly formed on a source/drain (SD) layer by using a three-layer structure, which includes a first metal layer 100, a second metal layer 200, and a third metal layer 300, the first metal layer 100 is made of molybdenum (Mo), the second metal layer 200 is made of aluminum (Al), the third metal layer 300 is made of molybdenum (Mo), the first metal layer 100 effectively prevents the second metal layer 200 from diffusing to an a-Si layer, and a dense and stable insulating layer Al is easily formed on the surface of the second metal layer 2002O3So that the second metal layer 200 and the pixel electrode layer can not be electrically connected, and a stable second metal layer is further formed on the upper surface of the second metal layer 200And a tri-metal layer 300 electrically connected to the pixel electrode layer.
The presence of the third metal layer 300 in the actual production process presents other problems, such as: since the third metal layer 300 is thin, it is easy to permeate water vapor to form a hole, and galvanic corrosion is formed with the second metal layer 200 exposed in the hole, which causes the second metal layer 200 to be rapidly corroded to form a first fracture 210, i.e. the source/drain electrode layer has a fracture problem.
As shown in fig. 2, in the source/drain electrode layer process, the second electrode layer 200 is likely to react with the alkaline substance in the stripping solution, and undercutting (undercut) is performed below the third metal layer 300 to form a chamfer, so that in the subsequent pixel electrode layer preparation process, a second fracture 410 occurs on the upper pixel electrode layer 400 after film formation, and the line is broken.
Disclosure of Invention
The invention aims to solve the galvanic corrosion problem of a source drain electrode layer of the conventional array substrate and the technical problem of fracture of a pixel electrode layer.
In order to achieve the above object, the present invention provides an array substrate, including: a substrate; the array layer is arranged on the surface of one side of the substrate; the array layer comprises a source drain electrode layer; wherein, the source drain electrode layer includes: a first metal layer; and the second metal layer is arranged on the surface of one side of the first metal layer, which is far away from the substrate.
Furthermore, the material of the first metal layer is molybdenum.
Furthermore, the second metal layer is made of aluminum.
Furthermore, the second metal layer is provided with a first through hole, and the first through hole penetrates through the second metal layer.
Furthermore, the array substrate further comprises a passivation layer arranged on the surface of the array layer far away from one side of the substrate; the passivation layer is provided with a second through hole, the second through hole is opposite to the first through hole, and the inner diameter of the second through hole is larger than that of the first through hole.
Further, the array substrate further comprises a pixel electrode layer, and the pixel electrode layer extends from the surface of the passivation layer, which is far away from the substrate side, to the inner side wall of the second through hole, the bottom of the first through hole and the inner side wall of the first through hole.
In order to achieve the above object, the present invention further provides a method for manufacturing an array substrate, including the steps of: a substrate providing step of providing a substrate; preparing an array layer on the upper surface of the substrate; the array layer preparation step comprises a source drain layer preparation step; in the source and drain electrode preparation step, preparing a first metal layer; and preparing a second metal layer on the upper surface of the first metal layer.
Further, after the array layer preparing step, the method for preparing the array substrate further includes: preparing a passivation layer on the upper surface of the array layer; and an electrode layer preparation step, namely preparing an electrode layer on the upper surface of the array layer.
Further, the passivation layer preparing step includes: a film forming step of coating a layer of passivation material on the upper surface of the array layer and forming a film; and a first etching step of etching the passivation material to form a second through hole.
Furthermore, the preparation method of the array substrate further comprises a second etching step, wherein the second metal layer is etched and processed by adopting a wet etching method to form the first through hole.
The array substrate has the technical effects that the source and drain electrode layers are designed by adopting a two-layer metal layer lamination, the pixel electrode layer is directly lapped to the first metal layer through the through hole, the electric connection between the pixel electrode layer and the source and drain electrode layers is ensured, the phenomena of galvanic corrosion of the second metal layer and pixel electrode layer fracture are avoided, the yield of the array substrate is improved, meanwhile, the arrangement of one metal layer is reduced, the use amount of metal materials is reduced, and the production cost of the array substrate is saved.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a source-drain electrode layer after being partially etched in the prior art;
FIG. 2 is a schematic diagram illustrating a prior art method for forming a chamfer on a pixel electrode layer;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of the source/drain electrode layer and the passivation layer in the embodiment of the present invention;
FIG. 5 is a partial enlarged view of the array substrate according to the embodiment of the invention;
fig. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Some of the components are identified as follows:
100. a first metal layer; 200. a second metal layer; 210. a first break; 300. a third metal layer; 400. a pixel electrode layer; 410. a second fracture;
1. a substrate; 2. an array layer; 3. a passivation layer; 4. a pixel electrode layer;
21. a source drain electrode layer; 211. a first metal layer; 212. a second metal layer; 213. a first through hole;
31. a second via.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
Specifically, referring to fig. 3 to 5, specifically, as shown in fig. 3, an array substrate according to an embodiment of the present invention includes a substrate 1, an array layer 2, a passivation layer 3, and a pixel electrode layer 4.
The base plate 1 is a substrate base plate, and is generally a hard base plate, such as a glass base plate, and plays a role of a substrate and a supporting role.
The array layer 2 is arranged on the upper surface of the substrate 1, is a main film layer of the array substrate and plays a role of a control circuit. The array layer 2 includes a light-shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, and a source/drain electrode layer 21.
The upper surface of base plate 1 is located to the light shield layer, the material of light shield layer is the shading material, the shading material is the metal, includes: molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or an alloy, the light shielding layer plays a role of shielding light.
The buffer layer is arranged on the upper surfaces of the light shielding layer and the substrate 1 and plays a role in buffering, the buffer layer is made of inorganic materials, and the inorganic materials comprise silicon oxides or silicon nitrides or are of a multilayer structure.
The active layer is arranged on the upper surface of the buffer layer, the active layer is made of a semiconductor material, and the semiconductor material comprises Indium Gallium Zinc Oxide (IGZO), indium gallium titanium oxide (IZTO) and Indium Gallium Zinc Titanium Oxide (IGZTO). The active layer is arranged above the light shielding layer, namely the active layer is arranged opposite to the light shielding layer and provides circuit support for the array substrate.
The grid electrode insulating layer is arranged on the upper surface of the active layer, the material of the grid electrode insulating layer is an inorganic material, and the inorganic material comprises silicon oxide or silicon nitride or a multilayer film structure. The grid electrode insulating layer is arranged opposite to the active layer, plays an insulating role and prevents short circuit among all circuits in the array.
The gate layer is arranged on the upper surface of the gate insulating layer and made of a metal material, wherein the metal material comprises molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti) and the like, or an alloy or a multilayer film structure. The gate layer is disposed opposite to the gate insulating layer.
The interlayer insulating layer is arranged on the upper surfaces of the grid electrode layer, the grid electrode insulating layer, the active layer and the buffer layer, the interlayer insulating layer is made of inorganic materials, and the inorganic materials comprise silicon oxide or silicon nitride or a multilayer film structure, so that the insulating effect is achieved, and the short circuit of a circuit is prevented. Through holes are formed above the active layer and the shading layer, and the through holes are convenient for electrical connection between the pixel electrode layer and the active layer.
The source/drain electrode layer 21 is disposed on the upper surface of the interlayer insulating layer and electrically connected to the active layer through the interlayer insulating layer, as shown in fig. 4, the source/drain electrode layer 21 includes a first metal layer 211 and a second metal layer 212.
The first metal layer 211 is disposed on the upper surface of the interlayer insulating layer, the material of the first metal layer 211 is molybdenum (Mo), which has good conductivity, and the thickness of the first metal layer 211 is generally 150 to 450 angstroms. The second metal layer 212 is disposed on the upper surface of the first metal layer 211, the material of the second metal layer 212 is aluminum, the thickness of the second metal layer 212 is usually 2600 to 3900 angstroms, the second metal layer 212 is provided with a first through hole 213, and the first through hole 213 penetrates through the second metal layer 212 to provide a channel for the pixel electrode layer 4.
In this embodiment, the source/drain electrode layer 21 has a two-layer stacked structure, so that a dense aluminum oxide film is formed on the surface of aluminum, and is not prone to permeating water vapor, and galvanic corrosion does not occur on the second metal layer 212, thereby ensuring the integrity of the second metal layer 212.
The passivation layer 3 is disposed on the upper surface of the second metal layer 212, and the passivation layer 3 plays a role in insulating and isolating external water and oxygen. The second through hole 31 penetrates through the passivation layer 3 and is disposed opposite to the first through hole 213, and an inner diameter of the second through hole 31 is larger than an inner diameter of the first through hole 213 for providing a channel for the pixel electrode layer 4.
As shown in fig. 5, the pixel electrode layer 4 is disposed on the upper surface of the passivation layer 3 and extends to the bottom and the inner sidewall of the first through hole 213 and the bottom and the inner sidewall of the second through hole 31. Because the surface of the second metal layer 212 forms a dense and stable alumina film Al2O3The aluminum oxide film has an insulating effect, so that through holes are formed in the second metal layer 212 and the passivation layer 3, so that the pixel electrode layer 4 can be directly overlapped with the first metal layer 211 to form an electrical connection between the pixel electrode layer 4 and the first metal layer 211, that is, an electrical connection between the pixel electrode layer 4 and the source/drain electrode layer 21 is formed, and an electrical signal support is provided for light emission of the display panel.
The second metal layer 212 is not covered by the top molybdenum layer, so that a chamfer between the second metal layer 212 and the top molybdenum layer is not generated in the subsequent etching process, the problem of fracture is avoided in the preparation process of the pixel electrode layer, and the yield of the pixel electrode layer of the array substrate is improved.
The array substrate has the advantages that the source electrode layer and the drain electrode layer are designed in a laminated mode through two metal layers, the pixel electrode layer is directly overlapped to the first metal layer through the through hole, the electric connection between the pixel electrode layer and the source electrode layer is guaranteed, the technical problems that the pixel electrode layer is broken due to the fact that the galvanic corrosion of the second metal layer and the chamfer angle appears in the source electrode layer are effectively solved, the yield of the array substrate is improved, meanwhile, the arrangement of one metal layer is reduced, the using amount of metal materials is reduced, and the production cost of the array substrate is saved.
As shown in fig. 6, the present embodiment further provides a method for manufacturing an array substrate, including steps S1 to S4.
S1 providing a substrate, wherein the substrate is a hard substrate, such as a glass substrate, and the substrate is used for supporting.
S2 step of preparing an array layer, where the step of preparing the array layer includes a step of preparing a light shielding layer, a step of preparing a buffer layer, a step of preparing an active layer, a step of preparing a gate insulating layer, a step of preparing a gate layer, a step of preparing an interlayer insulating layer, and a step of preparing a source drain electrode layer.
The source and drain electrode layer preparation step comprises a first metal layer preparation step and a second metal layer preparation step. In the first metal layer preparation step, a layer of metal material is coated on the upper surface of the interlayer insulating layer, the metal material is molybdenum, a first metal layer is formed after patterning treatment, and the thickness of the first metal layer is 150-450 angstroms. In the second metal layer preparation step, a layer of metal material is coated on the upper surface of the first metal layer, the metal material is metal aluminum, a second metal layer is formed, and the thickness of the second metal layer is 2600-3900 angstroms.
And S3, preparing a passivation layer on the upper surface of the second metal layer, specifically, the method comprises a film forming step and a first etching step, wherein in the film forming step, a layer of passivation material is coated on the upper surface of the second metal layer, and a film is formed. In the first etching step, the passivation material is etched by a dry etching method to form a through hole, where the through hole is the second through hole, and the second through hole penetrates through the passivation layer to provide a channel for the pixel electrode layer.
And S4, performing etching treatment on the second metal layer by using a wet etching method to form a through hole, wherein the through hole is the first through hole, the first through hole penetrates through the second metal layer, and the inner diameter of the first through hole is smaller than that of the second through hole, so that a channel is provided for the pixel electrode layer, and the pixel electrode layer is conveniently lapped on the first metal layer to form electric connection.
And S4, preparing a pixel electrode layer on the upper surface of the passivation layer, the bottom and the inner side wall of the first through hole, and the bottom and the inner side wall of the second through hole.
Because the second metal layer is made of aluminum metal, a dense and stable insulating layer of aluminum oxide is formed on the surface of the aluminum metal, and if a pixel electrode layer is directly prepared on the upper surface of the second metal layer, the electrical connection between the pixel electrode layer and the source/drain electrode layer is blocked.
The manufacturing method of the array substrate has the technical effects that through holes are formed in the second metal layer and the passivation layer, so that the pixel electrode layer is directly electrically connected to the first metal layer, the electric connection between the pixel electrode layer and the source drain electrode layer is guaranteed, meanwhile, the galvanic corrosion problem of the second metal layer and the technical problem that the pixel electrode layer is broken due to the fact that chamfers appear in the source drain electrode layer are effectively solved, the yield of the array substrate is improved, meanwhile, the arrangement of the metal layer is reduced, the use amount of metal materials is reduced, and the production cost of the array substrate is saved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the method for manufacturing the same provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the description of the embodiments is only used to help understanding the technical solutions and the core ideas of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. An array substrate, comprising:
a substrate; and
the array layer is arranged on the surface of one side of the substrate; the array layer comprises a source drain electrode layer;
wherein, the source drain electrode layer includes:
a first metal layer; and
and the second metal layer is arranged on the surface of one side of the first metal layer, which is far away from the substrate.
2. The array substrate of claim 1,
the first metal layer is made of molybdenum.
3. The array substrate of claim 1,
the second metal layer is made of aluminum.
4. The array substrate of claim 1,
the second metal layer is provided with a first through hole, and the first through hole penetrates through the second metal layer.
5. The array substrate of claim 4, further comprising
The passivation layer is arranged on the surface of one side of the array layer, which is far away from the substrate;
the passivation layer is provided with a second through hole, the second through hole is opposite to the first through hole, and the inner diameter of the second through hole is larger than that of the first through hole.
6. The array substrate of claim 5, further comprising
And the pixel electrode layer extends from the surface of the passivation layer, which is far away from one side of the substrate, to the inner side wall of the second through hole, the bottom of the first through hole and the inner side wall of the first through hole.
7. The preparation method of the array substrate is characterized by comprising the following steps:
a substrate providing step of providing a substrate; and
preparing an array layer on the upper surface of the substrate;
the array layer preparation step comprises a source drain layer preparation step;
in the step of preparing the source and the drain,
preparing a first metal layer;
and preparing a second metal layer on the upper surface of the first metal layer.
8. The method of manufacturing an array substrate according to claim 7,
after the array layer preparing step, the method further comprises the following steps:
preparing a passivation layer on the upper surface of the array layer; and
and preparing an electrode layer on the upper surface of the array layer.
9. The method of manufacturing an array substrate of claim 8,
the preparation method of the passivation layer comprises the following steps:
a film forming step of coating a layer of passivation material on the upper surface of the array layer and forming a film;
and a first etching step of etching the passivation material to form a second through hole.
10. The method for manufacturing the array substrate according to claim 7, further comprising a second etching step of etching the second metal layer by a wet etching method to form the first via hole.
CN202010045338.4A 2020-01-16 2020-01-16 Array substrate and preparation method thereof Pending CN111244108A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050041170A1 (en) * 2001-12-27 2005-02-24 Chae Gee Sung Array substrate for a liquid crystal display device having an improved contact property and fabricating method thereof
US20100155733A1 (en) * 2008-12-18 2010-06-24 Lg Display Co., Ltd. Array substrate for display device and method for fabricating the same
CN104733475A (en) * 2015-03-26 2015-06-24 南京中电熊猫液晶显示科技有限公司 Array substrate and manufacturing method thereof
CN110534549A (en) * 2019-08-08 2019-12-03 深圳市华星光电半导体显示技术有限公司 The production method of array substrate, display panel and array substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050041170A1 (en) * 2001-12-27 2005-02-24 Chae Gee Sung Array substrate for a liquid crystal display device having an improved contact property and fabricating method thereof
US20100155733A1 (en) * 2008-12-18 2010-06-24 Lg Display Co., Ltd. Array substrate for display device and method for fabricating the same
CN104733475A (en) * 2015-03-26 2015-06-24 南京中电熊猫液晶显示科技有限公司 Array substrate and manufacturing method thereof
CN110534549A (en) * 2019-08-08 2019-12-03 深圳市华星光电半导体显示技术有限公司 The production method of array substrate, display panel and array substrate

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Application publication date: 20200605