WO2020082623A1

WO2020082623A1 - Thin film transistor and fabrication method therefor

Info

Publication number: WO2020082623A1
Application number: PCT/CN2019/071733
Authority: WO
Inventors: 朱茂霞; 徐洪远
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2018-10-26
Filing date: 2019-01-15
Publication date: 2020-04-30
Also published as: CN109494257B; CN109494257A

Abstract

A thin film transistor (100) and a fabrication method therefor. The thin film transistor (100) comprises: a base substrate (1), a gate (2), a gate insulating layer (3), and an active layer (4), wherein the active layer (4) comprises a first protruding part (41) and a second protruding part (42), a source (8) is electrically connected to the first protrusion (41), a drain (9) is electrically connected to the second protrusion (42), and the source (8) and drain (9) are fabricated by means of a two-time patterning process, which may shorten the length of a channel (10) and reduce an AS tail within the channel (10), and thereby increase the electrical performance and illumination stability of the thin film transistor (100) as well as the charging rate of a large panel.

Description

Thin film transistor and its manufacturing method

Technical field

The present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof.

Background technique

Thin-film transistor liquid crystal display TFT-LCD (Thin Film Transistor-Liquid Crystal Display), the function of thin film transistor TFT is equivalent to a switch tube. A commonly used TFT is a three-terminal device. Generally, a semiconductor layer is prepared on a glass substrate, and a source electrode and a drain electrode connected thereto are provided at both ends, and the current applied between the source electrode and the drain electrode is controlled by the voltage applied to the gate electrode.

TFT devices work in the linear region, the channel is equivalent to a resistor, and the current is proportional to the channel width-to-length ratio (W / L). In order to improve the charging rate of large-size panels, the resistance of the channel needs to be small enough to meet a certain The on-state current and a certain charging rate, but due to the limitation of the pixel aperture ratio, the channel width W cannot be too large, so in order to increase the on-state current, the channel length L is reduced to a trend of designing large-size panels, and the traditional method Due to the limitation of exposure accuracy, which affects the yield, it is impossible to realize ultra-short channel TFTs for large-size panels.

In the preparation of thin film transistor TFTs in the prior art, there will be a certain difference between the edges of the active layer and the source-drain metal layer. The part of the active layer that protrudes from the source-drain metal layer is called amorphous silicon pigtail AS Tail (Amorphous Silicon tail, referred to as a-Si tail or AS tail), currently cannot avoid AS tail. As there is no metal on the upper part of the AS tail for light shielding, when light is irradiated on the TFT, the electrical properties of the device will deteriorate. It is more obvious that the leakage current increases, which prevents the device from shutting down normally, so reducing the AS tail has become the mainstream of the current design of TFT. trend.

Therefore, there is a need to provide a new thin film transistor and its manufacturing method, array substrate, and display device to solve the above problems.

technical problem

The present disclosure provides a thin film transistor and a manufacturing method thereof, which can solve how to shorten the TFT channel length and reduce AS Technical problems with tail.

Technical solution

To solve the above problems, the technical solutions provided by the disclosed embodiments are as follows:

An embodiment of the present disclosure provides a thin film transistor, including:

Substrate

A grid on the base substrate;

A gate insulating layer on the base substrate, covering the gate;

An active layer above the gate insulating layer, the active layer includes a first convex portion and a second convex portion; and

A source electrode and a drain electrode located above the active layer; the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the first An edge of a convex portion coincides, an edge of the drain and the second convex portion coincide, a region between the source and the drain corresponding to the active layer is a channel, and the length of the channel Less than 2μm.

Substrate

A grid on the base substrate;

A gate insulating layer on the base substrate, covering the gate;

A source electrode and a drain electrode located above the active layer; the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the drain electrode are electrically connected The region between the poles corresponding to the active layer is a channel.

In the thin film transistor provided by the embodiment of the present disclosure, the channel length is less than 2 μm.

In the thin film transistor provided by the embodiment of the present disclosure, the source electrode coincides with the edge of the first convex portion, and the drain electrode coincides with the edge of the second convex portion.

Embodiments of the present disclosure provide a method for manufacturing a thin film transistor, including the following steps:

S10: forming a gate, a gate insulating layer, an active layer, and a first source-drain metal layer in sequence on the base substrate;

S20: forming a first photoresist layer on the first source-drain metal layer;

S30: etching the first photoresist layer on the side of the first source-drain metal layer to form an over-etched region;

S40: forming a second source-drain metal layer on the surfaces of the first photoresist layer and the active layer;

S50: stripping the first photoresist layer;

S60: forming a second photoresist layer on the over-etched region and the second source-drain metal layer;

S70: Use the second photoresist layer to etch the over-etched area and the second source-drain metal layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode correspond to the The area of the source layer is the channel;

S80: Etching the active layer with the second photoresist layer to remove both end regions of the active layer;

S90: stripping the second photoresist layer; and

S100: Using the source electrode and the drain electrode as masks to etch the active layer to form a first convex portion and a second convex portion electrically connected to the source electrode and the drain electrode, respectively.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the step S10 specifically includes the following steps:

S101: forming the gate on the base substrate;

S102: forming the gate insulating layer above the gate;

S103: forming the active layer on the gate insulating layer; and

S104: Form the first source-drain metal layer on the active layer.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the gate insulating layer, the active layer, and the first source-drain metal layer are sequentially formed by methods such as deposition, coating, and sputtering.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, in the step S30, a wet etching method is used to etch the first source-drain metal layer under the first photoresist layer The over-etched area is formed.

In the method for manufacturing a thin film transistor provided by an embodiment of the present disclosure, in the step S40, a second source-drain metal layer is formed on the surface of the active layer by methods such as deposition, coating, and sputtering.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the first source-drain metal layer and the second source-drain metal layer are made of the same material.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the step S50 uses a photoresist stripping solution to strip the first photoresist layer.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, in step S70, a wet etching method is used to etch the over-etched region and the second source-drain metal layer to form the source and Drain.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the etching method used in the step S80 is a dry etching method.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the step S90 uses a photoresist stripping solution to strip the second photoresist layer.

In the manufacturing method of the thin film transistor provided by the embodiment of the present disclosure, the etching method used in the step S100 is a dry etching method.

Beneficial effect

Beneficial effect of the present disclosure: The present disclosure manufactures the source and drain of the thin film transistor TFT through two patterning processes, and a channel is formed between the source and drain, wherein the channel is over-etched by wet etching The formation of the region not only shortens the channel length of the TFT and improves the channel width-to-length ratio, but also reduces the AS tail in the channel, which improves the electrical performance and light stability of the TFT, thereby increasing the charging rate of the large-size panel.

BRIEF DESCRIPTION

In order to more clearly explain the embodiments or the technical solutions in the prior art, the following will briefly introduce the drawings used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only disclosed For some embodiments, those of ordinary skill in the art can obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure;

2 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the disclosure;

FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.

Embodiments of the invention

The descriptions of the following embodiments refer to the additional drawings to illustrate specific embodiments that can be implemented in the present disclosure. Directional terms mentioned in this disclosure, such as [upper], [lower], [front], [back], [left], [right], [inner], [outer], [side], [vertical] , [Horizontal], etc., only refer to the directions of the attached drawings. Therefore, the directional terminology is used to illustrate and understand this disclosure, not to limit it. In the figure, units with similar structures are indicated by the same reference numerals.

Example one

1 is a schematic structural diagram of a thin film transistor 100 according to an embodiment of the present disclosure. The thin film transistor 100 includes a base substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, and a source 8. Drain 9; the gate 2 is provided on the base substrate 1, the gate insulating layer 3 is provided on the base substrate 1 and covers the gate 2, the active layer 4 is provided on Above the gate insulating layer 3, the active layer 4 includes a first convex portion 41 and a second convex portion 42, the source electrode 8 is disposed above the first convex portion 41, and the drain electrode 9 is disposed on Above the second convex portion 42, that is, the source electrode 8 is electrically connected to the first convex portion 41, and the drain 9 is electrically connected to the second convex portion 42, that is, the source electrode 8 is connected to all A channel 10 is formed in the region corresponding to the active layer 4 between the drain 9, and the length of the channel 10 is less than 2 μm, which is formed through two patterning processes compared with the thin film transistor channel made by the traditional manufacturing process The source electrode 8 and the drain electrode 9 can greatly shorten the channel length of the channel 10, and effectively improve the electrical performance of the thin film transistor 100.

Since the source electrode 8 coincides with the edge of the first convex portion 41 and the drain electrode 9 coincides with the edge of the second convex portion 42, the size of the AS tail (not shown in the figure) can be The reduction to 0 μm effectively improves the light stability of the thin film transistor 100.

Example 2

2 is a flowchart of a method for manufacturing a thin film transistor 100 according to an embodiment of the present disclosure; FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor 100 according to an embodiment of the present disclosure; the The production method includes the following steps:

Step S10: forming the gate electrode 2, the gate insulating layer 3, the active layer 4 and the first source-drain metal layer 51 on the base substrate 1 in this order;

First, the gate electrode 2 is formed on the base substrate through a photolithography process, and then the gate electrode 1 and the gate electrode 2 can be selected according to different materials, and the gate electrode can be sequentially formed by deposition, coating, sputtering, etc. The three steps of the insulating layer 3, the active layer 4, and the first source-drain metal layer 51 are as follows:

S101: forming the gate electrode 2 on the base substrate 1;

S102: Form the gate insulating layer 3 above the gate 2, and the gate insulating layer 3 covers the gate 2;

S103: forming the active layer 4 on the gate insulating layer 3; and

S104: Form the first source-drain metal layer 51 on the active layer 4.

This step is the same as the traditional 4mask process, and the structure shown in Figure 3-1 can be obtained by the above preparation method.

Step S20: forming a first photoresist layer 61 on the first source-drain metal layer 51;

As shown in FIG. 3-2, a layer of photoresist may be coated on the first source-drain metal layer 51 formed in step S10, and the photoresist may be exposed using a halftone mask or a gray tone mask After development, the remaining part of the photoresist forms a first photoresist layer 61, and the first photoresist layer 61 corresponds to a region of the first source-drain metal layer 51.

Step S30: etching the first photoresist layer 61 on the side of the first source-drain metal layer 51 to form an over-etched region 7;

As shown in FIG. 3-3, the first source-drain metal layer 51 is etched by a wet etching method to etch away a portion of the first part that is not protected by the first photoresist layer 61 Since the source-drain metal layer 51 is etched isotropically by the wet etching method, the over-etched region 7 is formed under the first photoresist layer 61.

Step S40: forming a second source-drain metal layer 52 on the surfaces of the first photoresist layer 61 and the gate insulating layer 3;

The surface of the first photoresist layer 61 and the active layer 4 is covered with a second source-drain metal layer 52. The second source-drain metal layer 52 can be deposited, coated, sputtered, etc. By different methods, the second source-drain metal layer 52 and the first source-drain metal layer 51 can be selected from the same material. Therefore, the preparation process can use the same method, which simplifies the preparation process of the thin film transistor and improves To improve production efficiency and reduce costs.

Since the over-etched area 7 is formed under the first photoresist layer 61, when the second source-drain metal layer 52 is covered, the second source-drain metal layer 52 will be in the over-etched area The thickness of 7 places becomes thinner, and then breaks, forming the structure shown in Figure 3-4.

Step S50: stripping the first photoresist layer 61;

The first photoresist layer 61 may be removed by a stripping process. As described in step S40, since the second source-drain metal layer 52 breaks at the over-etched region 7, the photoresist stripping liquid may The first photoresist layer 61 is contacted from both sides of the over-etched area 7, and the first photoresist layer 61 is dissolved in the photoresist stripping solution. 3-5 are schematic structural diagrams of the thin film transistor after stripping the first photoresist layer 61.

Step S60: forming a second photoresist layer 62 on the over-etched region 7 and the second source-drain metal layer 52;

As shown in FIGS. 3-6, similar to the method for preparing the first photoresist layer 61 in step S20, a photoresist may be covered on the surface of the over-etched area 7 and the second source / drain metal layer 52 , A half-tone mask or a gray-tone mask can be used to expose and develop the photoresist, and the remaining part of the photoresist forms a second photoresist layer 62, and the second photoresist layer 62 corresponds to the over-etched area 7 and part of the region of the second source-drain metal layer 52.

Step S70: the second photoresist layer 62 is etched into the over-etched region 7 and the second source-drain metal layer 52 to form a source electrode 8 and a drain electrode 9, the source electrode 8 and the drain electrode The region between the poles 9 corresponding to the active layer 4 is a channel;

As shown in FIG. 3-7, similar to the preparation method of the over-etched area 7 in step S30, the over-etched area 7 and the second source-drain metal layer 52 are etched by a wet etching method, Etching away part of the over-etched region 7 and part of the second source-drain metal layer 52 that are not protected by the second photoresist layer 62, due to the wet etching method, the material is etched to be isotropic Therefore, a source electrode 8 and a drain electrode 9 can be formed under the second photoresist layer 62, and a region between the source electrode 8 and the drain electrode 9 corresponding to the active layer 4 forms a channel 10. Since the source electrode 8 and the drain electrode 9 are manufactured by the above two patterning processes, the length of the channel 10 can be greatly shortened, and the length of the channel 10 obtained by this preparation method can be less than 2 μm The electrical performance of the thin film transistor is improved, and the charging efficiency of the thin film transistor is greatly improved.

At the same time, since the edge of the active layer 4 and the source electrode 8 and the drain electrode 9 after the etching process have a certain difference, the active layer 4 protrudes from the source electrode 8, the The AS tail region 11 of the drain 9 has no metal to shield the upper part of the AS tail region 11, so when light is irradiated to the upper part of the thin film transistor, the leakage current will increase, so that the device cannot shut down normally, affecting the thin film transistor performance.

Step S80: Etching the active layer 4 with the second photoresist layer 62 to remove both end regions of the active layer 4;

As shown in FIGS. 3-8, a dry etching method may be used, and the active layer 4 is etched using the second photoresist layer 62 as a mask, thereby removing the active layer 4 The regions at both ends make the edge of the active layer 4 coincide with the edge of the gate insulating layer 3.

Step S90: stripping the second photoresist layer 62;

Similar to the method of stripping the first photoresist layer 61 in step S50, the second photoresist layer 62 uses a stripping process, and a photoresist stripping solution is used to contact the second photoresist layer 62, and The two photoresist layers 62 are dissolved in the photoresist stripping solution. 3-9 are schematic structural diagrams of the thin film transistor after stripping the second photoresist layer 62. as well as

Step S100: etching the active layer 4 using the source electrode 8 and the drain electrode 9 as a mask to form a first convex portion 41 and a second electrode electrically connected to the source electrode 8 and the drain electrode 9, respectively Convex part 42.

As shown in FIG. 3-10, similar to the process in step S80, the active layer 4 may be etched using a dry etching method, but the difference is that the step S80 is based on The second photoresist layer 62 is a mask to etch the active layer 4, and in this step S100, the source electrode 8 and the drain electrode 9 formed in the above steps are directly used as a mask, The active layer 4 is etched without the need to provide a mask plate, which simplifies the manufacturing process.

At the same time, the dry etching process is performed directly using the source electrode and the drain electrode as masks. Since the dry etching method etches the material to be anisotropic, the active layer can be formed after the etching process The first convex portion 41 and the second convex portion 42, the edge of the first convex portion coincides with the edge of the source, and the second convex portion coincides with the edge of the drain. Therefore, the AS The length of tail 11 (not shown in the figure) can be reduced to 0 μm, thereby improving the light stability of the thin film transistor.

Example Three

An embodiment of the present disclosure provides an array substrate including the thin film transistor provided in the above embodiment.

Since the above-mentioned thin-film transistor is fabricated through two patterning processes to make the source and the drain, the channel length of the thin-film transistor can be reduced, the channel width-to-length ratio is improved, and the AS in the channel can also be made Tail reduction makes the thin film transistor have good electrical performance and light stability. Therefore, the array substrate using the thin film transistor also has good electrical performance and light stability.

Example 4

This embodiment provides a display device including the array substrate provided in Embodiment 5.

Since the thin film transistor used in the array substrate provided in the fifth embodiment is manufactured by two patterning processes to make the source electrode and the drain electrode, the channel length of the thin film transistor can be reduced, the channel width-to-length ratio can be improved, and the trench Intra-AS Tail reduction makes the array substrate using the thin film transistor have good electrical performance and light stability. Therefore, the display device using the array substrate also has good electrical performance.

In specific implementation, the display device provided in this embodiment may be any product or component with a display function such as a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. .

In summary, although the present disclosure has been disclosed as preferred embodiments above, the above preferred embodiments are not intended to limit the present disclosure. Those of ordinary skill in the art can make various changes without departing from the spirit and scope of the present disclosure Such changes and retouching, therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.

Claims

A thin film transistor, including:

Substrate

A grid on the base substrate;

A gate insulating layer on the base substrate, covering the gate;

An active layer above the gate insulating layer, the active layer includes a first convex portion and a second convex portion; and

A source electrode and a drain electrode located above the active layer; the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the first An edge of a convex portion coincides, an edge of the drain and the second convex portion coincide, a region between the source and the drain corresponding to the active layer is a channel, and the length of the channel Less than 2μm.
A thin film transistor, including:

Substrate

A grid on the base substrate;

A gate insulating layer on the base substrate, covering the gate;

An active layer above the gate insulating layer, the active layer includes a first convex portion and a second convex portion; and

A source electrode and a drain electrode located above the active layer; the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the drain electrode are electrically connected The region between the poles corresponding to the active layer is a channel.
The thin film transistor according to claim 2, wherein the channel length is less than 2 μm.
The thin film transistor according to claim 2, wherein the source electrode coincides with an edge of the first convex portion, and the drain electrode coincides with an edge of the second convex portion.
A method for preparing a thin film transistor, which includes the following steps:

S10: forming a gate, a gate insulating layer, an active layer, and a first source-drain metal layer in sequence on the base substrate;

S20: forming a first photoresist layer on the first source-drain metal layer;

S30: Etching the first photoresist layer on the first source-drain metal layer to form an over-etched region;

S40: forming a second source-drain metal layer on the surfaces of the first photoresist layer and the active layer;

S50: stripping the first photoresist layer;

S60: forming a second photoresist layer on the over-etched region and the second source-drain metal layer;

S70: Use the second photoresist layer to etch the over-etched area and the second source-drain metal layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode correspond to the The area of the source layer is the channel;

S80: Etching the active layer with the second photoresist layer to remove both end regions of the active layer;

S90: stripping the second photoresist layer; and

S100: Using the source electrode and the drain electrode as masks to etch the active layer to form a first convex portion and a second convex portion electrically connected to the source electrode and the drain electrode, respectively.
The method for manufacturing a thin film transistor according to claim 5, wherein the step S10 specifically includes the following steps:

S101: forming the gate on the base substrate;

S102: forming the gate insulating layer above the gate;

S103: forming the active layer on the gate insulating layer; and

S104: Form the first source-drain metal layer on the active layer.
The method for manufacturing a thin film transistor according to claim 6, wherein the gate insulating layer, the active layer, and the first source-drain metal layer are sequentially formed by deposition, coating, sputtering, or the like.
The method for manufacturing a thin film transistor according to claim 5, wherein in step S30, a wet etching method is used to etch the first source-drain metal layer under the first photoresist layer The over-etched area is formed.
The method for manufacturing a thin film transistor according to claim 5, wherein in the step S40, a second source-drain metal layer is formed on the surface of the active layer by methods such as deposition, coating, sputtering, and the like.
The method for manufacturing a thin film transistor according to claim 5, wherein the first source-drain metal layer and the second source-drain metal layer are made of the same material.
The method of manufacturing a thin film transistor according to claim 5, wherein the step S50 uses a photoresist stripping solution to strip the first photoresist layer.
The method for manufacturing a thin film transistor according to claim 5, wherein in step S70, a wet etching method is used to etch the over-etched region and the second source-drain metal layer to form a source electrode Drain.
The method for manufacturing a thin film transistor according to claim 5, wherein the etching method used in the step S80 is a dry etching method.
The method for manufacturing a thin film transistor according to claim 5, wherein the step S90 uses a photoresist stripping solution to strip the second photoresist layer.
The method for manufacturing a thin film transistor according to claim 5, wherein the etching method used in step S100 is a dry etching method.