WO2020082623A1 - Transistor à couches minces et son procédé de fabrication - Google Patents

Transistor à couches minces et son procédé de fabrication Download PDF

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Publication number
WO2020082623A1
WO2020082623A1 PCT/CN2019/071733 CN2019071733W WO2020082623A1 WO 2020082623 A1 WO2020082623 A1 WO 2020082623A1 CN 2019071733 W CN2019071733 W CN 2019071733W WO 2020082623 A1 WO2020082623 A1 WO 2020082623A1
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WO
WIPO (PCT)
Prior art keywords
source
layer
film transistor
thin film
drain
Prior art date
Application number
PCT/CN2019/071733
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English (en)
Chinese (zh)
Inventor
朱茂霞
徐洪远
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020082623A1 publication Critical patent/WO2020082623A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof.
  • Thin-film transistor liquid crystal display TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the function of thin film transistor TFT is equivalent to a switch tube.
  • a commonly used TFT is a three-terminal device.
  • a semiconductor layer is prepared on a glass substrate, and a source electrode and a drain electrode connected thereto are provided at both ends, and the current applied between the source electrode and the drain electrode is controlled by the voltage applied to the gate electrode.
  • the channel is equivalent to a resistor, and the current is proportional to the channel width-to-length ratio (W / L).
  • W / L channel width-to-length ratio
  • the resistance of the channel needs to be small enough to meet a certain The on-state current and a certain charging rate, but due to the limitation of the pixel aperture ratio, the channel width W cannot be too large, so in order to increase the on-state current, the channel length L is reduced to a trend of designing large-size panels, and the traditional method Due to the limitation of exposure accuracy, which affects the yield, it is impossible to realize ultra-short channel TFTs for large-size panels.
  • the present disclosure provides a thin film transistor and a manufacturing method thereof, which can solve how to shorten the TFT channel length and reduce AS Technical problems with tail.
  • An embodiment of the present disclosure provides a thin film transistor, including:
  • An active layer above the gate insulating layer includes a first convex portion and a second convex portion;
  • a source electrode and a drain electrode located above the active layer the source electrode is electrically connected to the first convex portion, the drain electrode is electrically connected to the second convex portion, and the source electrode and the first An edge of a convex portion coincides, an edge of the drain and the second convex portion coincide, a region between the source and the drain corresponding to the active layer is a channel, and the length of the channel Less than 2 ⁇ m.
  • An embodiment of the present disclosure provides a thin film transistor, including:
  • An active layer above the gate insulating layer includes a first convex portion and a second convex portion;
  • the region between the poles corresponding to the active layer is a channel.
  • the channel length is less than 2 ⁇ m.
  • the source electrode coincides with the edge of the first convex portion
  • the drain electrode coincides with the edge of the second convex portion
  • Embodiments of the present disclosure provide a method for manufacturing a thin film transistor, including the following steps:
  • S10 forming a gate, a gate insulating layer, an active layer, and a first source-drain metal layer in sequence on the base substrate;
  • S70 Use the second photoresist layer to etch the over-etched area and the second source-drain metal layer to form a source electrode and a drain electrode, and the source electrode and the drain electrode correspond to the The area of the source layer is the channel;
  • S80 Etching the active layer with the second photoresist layer to remove both end regions of the active layer
  • S100 Using the source electrode and the drain electrode as masks to etch the active layer to form a first convex portion and a second convex portion electrically connected to the source electrode and the drain electrode, respectively.
  • the step S10 specifically includes the following steps:
  • S104 Form the first source-drain metal layer on the active layer.
  • the gate insulating layer, the active layer, and the first source-drain metal layer are sequentially formed by methods such as deposition, coating, and sputtering.
  • step S30 a wet etching method is used to etch the first source-drain metal layer under the first photoresist layer The over-etched area is formed.
  • a second source-drain metal layer is formed on the surface of the active layer by methods such as deposition, coating, and sputtering.
  • the first source-drain metal layer and the second source-drain metal layer are made of the same material.
  • the step S50 uses a photoresist stripping solution to strip the first photoresist layer.
  • step S70 a wet etching method is used to etch the over-etched region and the second source-drain metal layer to form the source and Drain.
  • the etching method used in the step S80 is a dry etching method.
  • the step S90 uses a photoresist stripping solution to strip the second photoresist layer.
  • the etching method used in the step S100 is a dry etching method.
  • the present disclosure manufactures the source and drain of the thin film transistor TFT through two patterning processes, and a channel is formed between the source and drain, wherein the channel is over-etched by wet etching
  • the formation of the region not only shortens the channel length of the TFT and improves the channel width-to-length ratio, but also reduces the AS tail in the channel, which improves the electrical performance and light stability of the TFT, thereby increasing the charging rate of the large-size panel.
  • FIG. 1 is a schematic structural diagram of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for manufacturing a thin film transistor provided by an embodiment of the disclosure
  • FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • the thin film transistor 100 includes a base substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, and a source 8. Drain 9; the gate 2 is provided on the base substrate 1, the gate insulating layer 3 is provided on the base substrate 1 and covers the gate 2, the active layer 4 is provided on Above the gate insulating layer 3, the active layer 4 includes a first convex portion 41 and a second convex portion 42, the source electrode 8 is disposed above the first convex portion 41, and the drain electrode 9 is disposed on Above the second convex portion 42, that is, the source electrode 8 is electrically connected to the first convex portion 41, and the drain 9 is electrically connected to the second convex portion 42, that is, the source electrode 8 is connected to all A channel 10 is formed in the region corresponding to the active layer 4 between the drain 9, and the length of the channel 10 is less than 2 ⁇ m, which is formed through two patterning processes compared with the thin film
  • the size of the AS tail (not shown in the figure) can be The reduction to 0 ⁇ m effectively improves the light stability of the thin film transistor 100.
  • FIGS. 3-1 to 3-10 are schematic diagrams of a method for manufacturing a thin film transistor 100 according to an embodiment of the present disclosure; the The production method includes the following steps:
  • Step S10 forming the gate electrode 2, the gate insulating layer 3, the active layer 4 and the first source-drain metal layer 51 on the base substrate 1 in this order;
  • the gate electrode 2 is formed on the base substrate through a photolithography process, and then the gate electrode 1 and the gate electrode 2 can be selected according to different materials, and the gate electrode can be sequentially formed by deposition, coating, sputtering, etc.
  • the three steps of the insulating layer 3, the active layer 4, and the first source-drain metal layer 51 are as follows:
  • S104 Form the first source-drain metal layer 51 on the active layer 4.
  • This step is the same as the traditional 4mask process, and the structure shown in Figure 3-1 can be obtained by the above preparation method.
  • Step S20 forming a first photoresist layer 61 on the first source-drain metal layer 51;
  • a layer of photoresist may be coated on the first source-drain metal layer 51 formed in step S10, and the photoresist may be exposed using a halftone mask or a gray tone mask After development, the remaining part of the photoresist forms a first photoresist layer 61, and the first photoresist layer 61 corresponds to a region of the first source-drain metal layer 51.
  • Step S30 etching the first photoresist layer 61 on the side of the first source-drain metal layer 51 to form an over-etched region 7;
  • the first source-drain metal layer 51 is etched by a wet etching method to etch away a portion of the first part that is not protected by the first photoresist layer 61 Since the source-drain metal layer 51 is etched isotropically by the wet etching method, the over-etched region 7 is formed under the first photoresist layer 61.
  • Step S40 forming a second source-drain metal layer 52 on the surfaces of the first photoresist layer 61 and the gate insulating layer 3;
  • the surface of the first photoresist layer 61 and the active layer 4 is covered with a second source-drain metal layer 52.
  • the second source-drain metal layer 52 can be deposited, coated, sputtered, etc.
  • the second source-drain metal layer 52 and the first source-drain metal layer 51 can be selected from the same material. Therefore, the preparation process can use the same method, which simplifies the preparation process of the thin film transistor and improves To improve production efficiency and reduce costs.
  • the over-etched area 7 is formed under the first photoresist layer 61, when the second source-drain metal layer 52 is covered, the second source-drain metal layer 52 will be in the over-etched area The thickness of 7 places becomes thinner, and then breaks, forming the structure shown in Figure 3-4.
  • Step S50 stripping the first photoresist layer 61;
  • the first photoresist layer 61 may be removed by a stripping process. As described in step S40, since the second source-drain metal layer 52 breaks at the over-etched region 7, the photoresist stripping liquid may The first photoresist layer 61 is contacted from both sides of the over-etched area 7, and the first photoresist layer 61 is dissolved in the photoresist stripping solution.
  • 3-5 are schematic structural diagrams of the thin film transistor after stripping the first photoresist layer 61.
  • Step S60 forming a second photoresist layer 62 on the over-etched region 7 and the second source-drain metal layer 52;
  • a photoresist may be covered on the surface of the over-etched area 7 and the second source / drain metal layer 52 .
  • a half-tone mask or a gray-tone mask can be used to expose and develop the photoresist, and the remaining part of the photoresist forms a second photoresist layer 62, and the second photoresist layer 62 corresponds to the over-etched area 7 and part of the region of the second source-drain metal layer 52.
  • Step S70 the second photoresist layer 62 is etched into the over-etched region 7 and the second source-drain metal layer 52 to form a source electrode 8 and a drain electrode 9, the source electrode 8 and the drain electrode
  • the region between the poles 9 corresponding to the active layer 4 is a channel;
  • the over-etched area 7 and the second source-drain metal layer 52 are etched by a wet etching method, Etching away part of the over-etched region 7 and part of the second source-drain metal layer 52 that are not protected by the second photoresist layer 62, due to the wet etching method, the material is etched to be isotropic Therefore, a source electrode 8 and a drain electrode 9 can be formed under the second photoresist layer 62, and a region between the source electrode 8 and the drain electrode 9 corresponding to the active layer 4 forms a channel 10.
  • the length of the channel 10 can be greatly shortened, and the length of the channel 10 obtained by this preparation method can be less than 2 ⁇ m
  • the electrical performance of the thin film transistor is improved, and the charging efficiency of the thin film transistor is greatly improved.
  • the edge of the active layer 4 and the source electrode 8 and the drain electrode 9 after the etching process have a certain difference, the active layer 4 protrudes from the source electrode 8, the The AS tail region 11 of the drain 9 has no metal to shield the upper part of the AS tail region 11, so when light is irradiated to the upper part of the thin film transistor, the leakage current will increase, so that the device cannot shut down normally, affecting the thin film transistor performance.
  • Step S80 Etching the active layer 4 with the second photoresist layer 62 to remove both end regions of the active layer 4;
  • a dry etching method may be used, and the active layer 4 is etched using the second photoresist layer 62 as a mask, thereby removing the active layer 4
  • the regions at both ends make the edge of the active layer 4 coincide with the edge of the gate insulating layer 3.
  • Step S90 stripping the second photoresist layer 62;
  • the second photoresist layer 62 uses a stripping process, and a photoresist stripping solution is used to contact the second photoresist layer 62, and The two photoresist layers 62 are dissolved in the photoresist stripping solution.
  • 3-9 are schematic structural diagrams of the thin film transistor after stripping the second photoresist layer 62. as well as
  • Step S100 etching the active layer 4 using the source electrode 8 and the drain electrode 9 as a mask to form a first convex portion 41 and a second electrode electrically connected to the source electrode 8 and the drain electrode 9, respectively Convex part 42.
  • the active layer 4 may be etched using a dry etching method, but the difference is that the step S80 is based on The second photoresist layer 62 is a mask to etch the active layer 4, and in this step S100, the source electrode 8 and the drain electrode 9 formed in the above steps are directly used as a mask, The active layer 4 is etched without the need to provide a mask plate, which simplifies the manufacturing process.
  • the dry etching process is performed directly using the source electrode and the drain electrode as masks. Since the dry etching method etches the material to be anisotropic, the active layer can be formed after the etching process The first convex portion 41 and the second convex portion 42, the edge of the first convex portion coincides with the edge of the source, and the second convex portion coincides with the edge of the drain. Therefore, the AS The length of tail 11 (not shown in the figure) can be reduced to 0 ⁇ m, thereby improving the light stability of the thin film transistor.
  • An embodiment of the present disclosure provides an array substrate including the thin film transistor provided in the above embodiment.
  • the channel length of the thin-film transistor can be reduced, the channel width-to-length ratio is improved, and the AS in the channel can also be made Tail reduction makes the thin film transistor have good electrical performance and light stability. Therefore, the array substrate using the thin film transistor also has good electrical performance and light stability.
  • This embodiment provides a display device including the array substrate provided in Embodiment 5.
  • the thin film transistor used in the array substrate provided in the fifth embodiment is manufactured by two patterning processes to make the source electrode and the drain electrode, the channel length of the thin film transistor can be reduced, the channel width-to-length ratio can be improved, and the trench Intra-AS Tail reduction makes the array substrate using the thin film transistor have good electrical performance and light stability. Therefore, the display device using the array substrate also has good electrical performance.
  • the display device provided in this embodiment may be any product or component with a display function such as a liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un transistor à couches minces (100) et son procédé de fabrication. Le transistor à couches minces (100) comprend : un substrat de base (1), une grille (2), une couche d'isolation de grille (3), et une couche active (4), la couche active (4) comprend une première partie saillante (41) et une seconde partie saillante (42), une source (8) est électriquement connectée à la première saillie (41), un drain (9) est connecté électriquement à la seconde saillie (42), et la source (8) et le drain (9) sont fabriqués au moyen d'un processus de formation de motifs en deux temps, qui peut raccourcir la longueur d'un canal (10) et réduire une queue d'AS à l'intérieur du canal (10), et ainsi augmenter la performance électrique et la stabilité d'éclairage du transistor à couches minces (100) ainsi que le taux de charge d'un grand panneau.
PCT/CN2019/071733 2018-10-26 2019-01-15 Transistor à couches minces et son procédé de fabrication WO2020082623A1 (fr)

Applications Claiming Priority (2)

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CN201811260510.7A CN109494257B (zh) 2018-10-26 2018-10-26 一种薄膜晶体管及其制造方法、阵列基板、显示装置
CN201811260510.7 2018-10-26

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CN110854134B (zh) * 2019-10-29 2022-04-26 Tcl华星光电技术有限公司 阵列基板的制作方法、阵列基板及显示装置
CN111129037B (zh) * 2019-12-25 2022-09-09 Tcl华星光电技术有限公司 Tft阵列基板及其制作方法
CN115485760A (zh) 2021-03-01 2022-12-16 京东方科技集团股份有限公司 显示面板及显示装置
CN113964191B (zh) * 2021-10-20 2023-06-23 京东方科技集团股份有限公司 氧化物薄膜晶体管及其制作方法、阵列基板、显示装置
CN117525164A (zh) * 2024-01-04 2024-02-06 惠科股份有限公司 阵列基板、阵列基板的制备方法及显示面板

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