CN111613576A - Array substrate and manufacturing method thereof - Google Patents
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- CN111613576A CN111613576A CN202010434763.2A CN202010434763A CN111613576A CN 111613576 A CN111613576 A CN 111613576A CN 202010434763 A CN202010434763 A CN 202010434763A CN 111613576 A CN111613576 A CN 111613576A
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- 239000000758 substrate Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 102
- 239000002184 metal Substances 0.000 claims abstract description 102
- 239000004065 semiconductor Substances 0.000 claims abstract description 61
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 37
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 152
- 239000011241 protective layer Substances 0.000 claims description 21
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910001257 Nb alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention provides an array substrate and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: depositing a metal oxide semiconductor layer and a second metal layer in sequence, firstly, removing the second metal layer in the area where the pixel electrode is located through exposure and etching, reserving the second metal layer above the channel area, and forming a temporary metal layer which is not separated from a source electrode and a drain electrode in the pixel area and a bridging part in the peripheral area; and then carrying out low impedance treatment on the metal oxide semiconductor layer which is not covered by the second metal layer to form a pixel electrode. The invention forms a temporary metal layer and a temporary semiconductor layer region by using 1 photomask, forms a pixel electrode by using an ion implantation mode, shields the semiconductor layer region by using the temporary metal layer to protect the semiconductor layer region, and forms the pixel electrode, a source electrode, a drain electrode and a channel region by adopting two continuous wet etching processes on a metal oxide semiconductor layer and a second metal layer.
Description
Technical Field
The invention belongs to the technical field of panel display, and particularly relates to an array substrate and a manufacturing method thereof.
Background
In recent years, display devices are continuously developed towards large size, narrow frame, low power consumption, high resolution, high refresh rate, flexibility and the like, and the metal oxide semiconductor layer and the technical display panel industry adopting copper to form the gate lines and the data lines have natural advantages. Meanwhile, with the continuous development of the TFT-LCD display technology, reducing the production cost of the display panel gradually becomes the first choice for production of each enterprise, the liquid crystal display panel is formed by assembling an array substrate and a color film substrate through a box-forming process, wherein the array substrate defines patterns on different layers by adopting a plurality of photomasks, each layer of pattern preparation process includes the steps of cleaning, film forming, photoresist coating, mask exposure, developing, etching and stripping, and the preparation of the array substrate is finally completed through the multiple cycles of the steps. In order to reduce the panel production cost and improve the product yield, engineering technicians are dedicated to reducing the number of times of using the photomask.
The conventional amorphous silicon array substrate adopts an FFS display technology, 5 photomasks or 6 photomasks are used in the mass production manufacturing process, for metal oxide, the process stability is more complicated than that of amorphous silicon, the existing main mass production process technology is 9 photomasks (channel etching blocking type), part of the existing main mass production process technology also adopts 8 photomasks (back channel etching type), and the engineering technology also carries out 7 photomasks (back channel etching type), but the photomask technologies are still relatively complicated in the preparation process of a metal oxide TFT device process.
Taking 7 masks as an example, as shown in fig. 1 and 2, the manufacturing steps are: the first step is as follows: forming a grid 20 on the substrate 10 by using a 1 st photomask; the second step is that: forming a gate insulating layer 30 covering the gate electrode 20; the third step: forming a semiconductor active layer 40 above the gate electrode 20 by using the 2 nd mask; the fourth step: forming a first contact hole in contact with the gate 10 in the peripheral region by using the 3 rd photomask; the fifth step: forming a source electrode 51 and a drain electrode 52 which are respectively contacted with the semiconductor active layer 40 in the pixel region by adopting the 4 th photomask, and forming a source-drain connection electrode 53 which is positioned in the first contact hole and is contacted with the gate electrode 10 in the peripheral region; and a sixth step: laying a first insulating layer 60 on the whole surface; the seventh step: forming a common electrode 70 by using the 5 th photomask; the seventh step: laying a second insulating layer 80 on the whole surface; eighthly, forming a second contact hole on the drain electrode 52 by adopting a 6 th photomask; the ninth step: the pixel electrode 90 is formed using the 7 th mask and the pixel electrode 90 contacts the drain electrode 52 through the second contact hole.
Disclosure of Invention
The invention aims to provide an array substrate and a manufacturing method thereof, wherein the array substrate is capable of reducing production cost and simplifying process flow.
The invention provides a manufacturing method of an array substrate, which comprises the following steps:
s1: depositing a first metal layer on a substrate, etching the first metal layer to form a grid in a pixel area, and forming a first metal line in a peripheral area; then forming a gate insulating layer covering the first metal layer;
s2: depositing a metal oxide semiconductor layer and a second metal layer in sequence, firstly, removing the second metal layer in the area where the pixel electrode is located through exposure and etching, reserving the second metal layer above the channel area, and forming a temporary metal layer which is not separated from a source electrode and a drain electrode in the pixel area and a bridging part in the peripheral area; then carrying out low impedance treatment on the metal oxide semiconductor layer which is not covered by the second metal layer to form a pixel electrode;
s3: firstly, covering a pixel electrode, a bridging part, a data line region, a source electrode region and a drain electrode region by using a light resistor; then etching to form a semiconductor channel between the region where the source electrode is located and the region where the drain electrode is located; finally, stripping the photoresistance to form a source electrode and a drain electrode;
s4: depositing a protective layer on the basis of the step S3, and simultaneously forming a first contact hole and a second contact hole on the bridging portion on the first layer metal line in the peripheral area;
s5: firstly, paving a transparent electrode on the whole surface, then coating a light resistance and exposing and etching to form an independent common electrode in a pixel area, and forming a transparent metal conductor layer connected with a first layer of metal wire and a bridging part in a peripheral area.
Preferably, in step S1, the first metal layer has a film thickness of
The film structure is a single-layer metal copper or aluminum or a double-layer structure.
Preferably, in step S2, the second metal layer has a film thickness of
The film layer structure is a double-layer metal structure.
Preferably, the metal oxide semiconductor layer has a film thickness of
Preferably, the material of the metal oxide semiconductor layer is indium gallium zinc oxide or indium gallium zinc oxide doped with Sn element.
Preferably, in steps S1 and S2, the bridge portion and the first layer metal line located in the peripheral region do not spatially overlap.
Preferably, in step S2, the exposed metal oxide semiconductor layer is subjected to a resistance lowering treatment using plasma to form a pixel electrode.
Preferably, the protective layer in step S4 has a film thickness of
The protective layer comprises a silicon dioxideA lower protective layer formed of silicon nitride and an upper protective layer formed of silicon nitride.
The present invention also provides an array substrate comprising criss-cross gate and data lines, a pixel region defined by intersections of the gate and data lines, a TFT switch having a pixel electrode located in the pixel region at an intersection of the gate and data lines, a gate insulating layer covering the gate line, a protective layer covering the TFT switch, and a common electrode located on the protective layer, wherein the TFT switch comprises a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a semiconductor layer region both in contact with the source electrode and the drain electrode and located above the gate electrode; the pixel electrode and the semiconductor layer region are located on the same layer and are formed by metal oxide semiconductor materials through ion implantation.
Preferably, the array substrate further includes a first metal line located in the peripheral region and formed simultaneously with the gate, a bridge portion formed simultaneously with the source, a peripheral semiconductor layer region located below the second metal line, and a transparent metal conductor layer formed simultaneously with the common electrode, wherein the first metal line and the bridge portion are connected through the transparent metal conductor layer with the gate insulating layer interposed therebetween.
The method comprises the steps of forming a temporary metal layer and a temporary semiconductor layer region by using 1 photomask, forming a pixel electrode in an ion implantation mode, shielding and protecting the semiconductor layer region by using the temporary metal layer, and forming the pixel electrode, a source electrode, a drain electrode and a channel region by performing wet etching on a metal oxide semiconductor layer and a second metal layer twice continuously; the invention solves the problems of high manufacturing cost and complex process of 9 photomask processes in the metal oxide FFS display technology; the advantages of reducing the production cost and simplifying the process flow are realized through 5 light covers.
Drawings
Fig. 1 is a schematic diagram of a pixel region of a conventional array substrate;
fig. 2 is a schematic view of a peripheral region of the array substrate shown in fig. 1;
FIGS. 3 and 4 are schematic structural diagrams illustrating one of the steps of the method for manufacturing an array substrate according to the present invention;
fig. 5 to 7 are schematic structural views of a second step of the manufacturing method of the array substrate according to the present invention;
fig. 8 and 9 are schematic structural views of a third step of the manufacturing method of the array substrate according to the present invention;
FIG. 10 is a structural diagram of a fourth step of the manufacturing method of the array substrate of the present invention;
FIG. 11 is a schematic structural diagram of a fifth step of the method for manufacturing an array substrate according to the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The invention discloses a manufacturing method of an array substrate, which integrates a pixel electrode, a semiconductor layer and a source drain electrode on a mask plate, wherein the semiconductor layer and the pixel electrode layer are arranged on the same layer and are formed at the same time, the semiconductor pixel electrode is conducted by shielding of a second layer of metal in an ion injection mode, and the pixel electrode, the source drain electrode and a semiconductor channel are formed by etching, so that the purposes of reducing the number of the mask plates, completing the production of 5 mask plates, improving the production efficiency and reducing the production cost are finally realized.
The manufacturing method of the array substrate comprises the following steps:
s1: as shown in fig. 3 and 4, a first metal layer 2 is deposited on a substrate 1, a gate line (not shown) connecting a gate electrode M11 and a gate electrode M11 is formed in a pixel region by etching the first metal layer 2, a first metal line M12 is formed in a peripheral region, and then a gate insulating layer covering the first metal layer 2 is formed.
As shown in FIG. 3, first, a first metal layer 2 is formed on a substrate 1 by PVD, and has a thickness of
The film structure can be single-layer metal copper or aluminum or double-layer structure, the bottom layer is titanium, molybdenum or molybdenum niobium alloy, and the upper layer is metal copper or metal aluminum; then, coating photoresist on the first metal layer 2, exposing, developing and etching to form a pattern, as shown in fig. 4, on the gate M11 in the pixel region and the first metal line M12 in the peripheral region; finally, a gate insulating layer is deposited overlying the first metal layer 2, the gate insulating layer comprising a stacked structure of a lower insulating layer 3 overlying the first metal layer 2 and an upper insulating layer 4 overlying the lower insulating layer 3.
S2: as shown in fig. 5 to 7, the metal oxide semiconductor layer 5 and the second metal layer 6 are sequentially deposited, and the second metal layer 6 in the area where the pixel electrode is located is first removed by exposure and etching, the second metal layer 6 above the channel area is remained, and a temporary metal layer M21 in which the source and drain electrodes in the pixel area are not separated and a bridge portion M2 in the peripheral area are formed; then, the metal oxide semiconductor layer 5 not covered with the second metal layer 6 is subjected to a low resistance treatment by hydrogen Plasma (H + Plasma) or the like to form a pixel electrode OS 12.
As shown in fig. 5, the metal oxide semiconductor layer 5 is used as a temporary semiconductor layer region, and the metal oxide semiconductor layer 5 and the second metal layer 6 are sequentially formed by physical vapor deposition, wherein the metal oxide semiconductor layer 5 has a film thickness of
The metal oxide semiconductor layer 5 is made of indium gallium zinc oxide(IGZO) or Indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO) doped with Sn or a mixture thereof; the second metal layer 6 has a film thickness of
The film structure is a double-layer metal structure, the bottom layer is titanium or titanium alloy, molybdenum or molybdenum-niobium alloy, and the upper layer is metal copper.
As shown in fig. 6, after performing processes of applying glue, exposing light, developing and etching the second metal layer 6, a temporary metal layer M21 without separating the source and the drain in the pixel region, a data line connected to the source, and a bridge portion M22 in the peripheral region are formed, and the second metal layer 6 in the region of the pixel electrode is etched away, so that the metal oxide semiconductor 5 in the region of the pixel electrode is exposed, that is, the metal oxide semiconductor 5 is exposed except the region covered by the temporary metal layer M21 and the bridge portion M22.
The bridge portion M22 located in the peripheral region and the first-layer metal wire M12 do not overlap in space.
As shown in fig. 7, the pixel electrode OS12 and the metal oxide region OS12 located in the peripheral region are formed by performing a resistance lowering process on the exposed metal oxide semiconductor layer 5 by using H + Plasma (Plasma) or the like, and the regions of the metal oxide semiconductor layer 5 covered with the temporary metal layer M21 and the bridge portion M2 are the semiconductor layer region OS11 and the peripheral semiconductor layer region OS13, respectively.
S3: as shown in fig. 8 and 9, the pixel electrode OS12, the bridge portion M22, the region where the data line is located, the region where the source electrode is located, and the region where the drain electrode is located are covered with the photoresist 100; then etching to form a semiconductor channel between the region where the source electrode is located and the region where the drain electrode is located; finally, the photoresist 100 is stripped to form a source M23, a drain M24 and a data line (not shown) connected to the source M23.
As shown in fig. 8, after the processes of glue coating, exposure, and development, the pixel electrode OS12, the bridge portion M22, the region where the source electrode is located, and the region where the drain electrode is located are covered with the photoresist 100; as shown in fig. 9, the metal oxide semiconductor layer 5 is etched to form a semiconductor channel between the source region and the drain region, and then the photoresist 100 is stripped to form the source M23 and the drain M24 in the second metal layer 6. Thus, the pixel electrode, the source and drain, and the semiconductor channel are completed. The following requirements are required to be made on the selection of the etching liquid: the metal etching liquid has no damage to the metal oxide; the etching rate of the metal oxide etching liquid to the metal cannot be too high.
S4: as shown in fig. 10, a protective layer is deposited on the basis of step S3, while forming a first contact hole 101 on the first-layer metal line M12 of the non-display terminal area (i.e., the peripheral area) and a second contact hole 102 on the bridging portion M22.
As shown in FIG. 10, first, a protective layer is formed by chemical vapor deposition to a film thickness of
The protective layer has a two-layer structure including a lower protective layer 7 formed of silicon dioxide and an upper protective layer 8 formed of silicon nitride. Then, after exposure and dry etching processes, a first contact hole 101 is formed in the first layer metal line M12 in the peripheral region, and a second contact hole 102 is formed in the bridge portion M22.
S5: as shown in fig. 11, the transparent electrode 9 is first spread over the whole surface, then a photoresist (not shown) is coated and exposed and etched to form an independent common electrode C91 in the pixel region, and a transparent metal conductor layer C92 connected to the first-layer metal line M12 and the bridge portion M22 is formed in the peripheral region.
As shown in FIG. 11, first, the transparent common electrode 9 is formed by physical vapor deposition to cover the pixel region and the peripheral region entirely and to have a film thickness of
Then, as shown in fig. 11, a photoresist is coated, exposed and developed, and a wet etching process is performed once to form a pattern, a common electrode C91 is formed in a pixel region, a transparent metal conductor layer C92 is formed in a peripheral region, and a transparent metal conductor layer C92 is located in the first contact hole 101 and the second contact hole 102 to connect the first-layer metal line M12 and the bridge portion M22.
The present invention also provides an array substrate including criss-crossed gate and data lines, a pixel region defined by intersections of the gate and data lines, a TFT switch located at a pixel electrode OS12 located at an intersection of the gate and data lines in the pixel region, the TFT switch including a gate electrode M11 connected to the gate line, a source electrode M23 connected to the data line, a drain electrode M24, a semiconductor layer region OS11 both in contact with the source electrode M23 and the drain electrode M24 and located above the gate electrode M11, a gate insulating layer covering the gate line, a protective layer covering the TFT switch, and a common electrode C91 located on the protective layer, wherein the pixel electrode OS12 is located at the same layer as the semiconductor layer region OS11 and is formed of a metal oxide semiconductor material through ion implantation.
The array substrate further comprises a first-layer metal wire M12 located in the peripheral region and formed simultaneously with the gate M11, a bridge portion M22 formed simultaneously with the source M23, a peripheral semiconductor layer region OS13 located below the second-layer metal wire M22, and a transparent metal conductor layer C92 formed simultaneously with the common electrode C91, wherein the first-layer metal wire M12 and the bridge portion M22 are connected through the transparent metal conductor layer C92 with a gate insulating layer interposed between the first-layer metal wire M12 and the peripheral semiconductor layer region OS 13.
A fringe field is formed between the pixel electrode OS12 and the common electrode C91, and the liquid crystal is driven by the fringe field, so that the array substrate of the present invention is an FFS array substrate.
The method comprises the steps of forming a temporary metal layer and a temporary semiconductor layer region by using 1 photomask, forming a pixel electrode in an ion implantation mode, shielding and protecting the semiconductor layer region by using the temporary metal layer, and forming the pixel electrode, a source electrode, a drain electrode and a channel region by performing wet etching on a metal oxide semiconductor layer and a second metal layer twice continuously; the invention solves the problems of high manufacturing cost and complex process of 9 photomask processes in the metal oxide FFS display technology; the advantages of reducing the production cost and simplifying the process flow are realized through 5 light covers.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A manufacturing method of an array substrate is characterized by comprising the following steps:
s1: depositing a first metal layer on a substrate, etching the first metal layer to form a grid in a pixel area, and forming a first metal line in a peripheral area; then forming a gate insulating layer covering the first metal layer;
s2: depositing a metal oxide semiconductor layer and a second metal layer in sequence, firstly, removing the second metal layer in the area where the pixel electrode is located through exposure and etching, reserving the second metal layer above the channel area, and forming a temporary metal layer which is not separated from a source electrode and a drain electrode in the pixel area and a bridging part in the peripheral area; then carrying out low impedance treatment on the metal oxide semiconductor layer which is not covered by the second metal layer to form a pixel electrode;
s3: firstly, covering a pixel electrode, a bridging part, a data line region, a source electrode region and a drain electrode region by using a light resistor; then etching to form a semiconductor channel between the region where the source electrode is located and the region where the drain electrode is located; finally, stripping the photoresistance to form a source electrode and a drain electrode;
s4: depositing a protective layer on the basis of the step S3, and simultaneously forming a first contact hole and a second contact hole on the bridging portion on the first layer metal line in the peripheral area;
s5: firstly, paving a transparent electrode on the whole surface, then coating a light resistance and exposing and etching to form an independent common electrode in a pixel area, and forming a transparent metal conductor layer connected with a first layer of metal wire and a bridging part in a peripheral area.
2. The method of claim 1, wherein in step S1, the first metal layer has a thickness of
The film structure is a single-layer metal copper or aluminum or a double-layer structure.
3. The method of claim 1, wherein in step S2, the second metal layer has a thickness of
The film layer structure is a double-layer metal structure.
4. The method of claim 1, wherein the metal oxide semiconductor layer has a film thickness of
5. The method of claim 1, wherein the metal oxide semiconductor layer is made of indium gallium zinc oxide or indium gallium zinc oxide doped with Sn.
6. The method of claim 1, wherein in the steps S1 and S2, the bridging portion and the first metal line in the peripheral region do not overlap in space.
7. The method of claim 1, wherein in step S2, the exposed metal oxide semiconductor layer is subjected to a resistance lowering treatment by plasma to form a pixel electrode.
8. The method of claim 1, wherein the protective layer in step S4 has a film thickness of
The protective layer comprises an underlayer formed of silicon dioxideA protective layer and an upper protective layer formed of silicon nitride.
9. An array substrate comprising criss-cross gate and data lines, a pixel region defined by the intersection of the gate and data lines, a TFT switch having a pixel electrode located in the pixel region at the intersection of the gate and data lines, a gate insulating layer covering the gate line, a protective layer covering the TFT switch, and a common electrode located on the protective layer, wherein the TFT switch comprises a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode, and a semiconductor layer region both in contact with the source and drain electrodes and located above the gate electrode; the pixel electrode and the semiconductor layer region are located on the same layer and are formed by metal oxide semiconductor materials through ion implantation.
10. The array substrate of claim 9, further comprising a first metal line formed simultaneously with the gate electrode in the peripheral region, a bridge portion formed simultaneously with the source electrode, a peripheral semiconductor layer region under the second metal line, and a transparent metal conductor layer formed simultaneously with the common electrode, wherein the first metal line and the bridge portion are connected by the transparent metal conductor layer with the gate insulating layer therebetween.
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| CN112420738A (en) * | 2020-10-29 | 2021-02-26 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
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| CN110794630A (en) * | 2019-10-09 | 2020-02-14 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
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