KR100417915B1 - Array Panel for Liquid Crystal Display Device and Method for Fabricating the same - Google Patents

Abstract

According to the present invention, an array substrate for a liquid crystal display device is provided by a four-mask process consisting of a gate process, a semiconductor layer and a source process, a protective layer process, and an ITO process. A gate wiring including a pad is formed, and in the semiconductor layer and the source process, a gate insulating film, a first active layer, an ohmic contact layer, a source and a drain electrode are formed, and the gate insulating film is formed in the channel portion of the separation section between the source and the drain electrode. The first active layer and the ohmic contact layer in this section are removed so as to be exposed. Next, in the passivation layer process, the second active layer and the passivation layer are sequentially formed, and then, the drain contact hole and the data pad contact hole are formed. The second active layer formed on the gate insulating layer of the channel portion is formed in the channel. Is achieved. In the ITO process, four masks are formed by forming a pixel electrode connected to the drain electrode through the drain contact hole, a data pad electrode connected to the data pad through the data pad contact hole, and a gate pad electrode directly covering the gate pad. An array substrate for a liquid crystal display device is fabricated, and in the protective layer process, an insulating material serving as a buffer layer may be included in a lower layer of the second active layer.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {Array Panel for Liquid Crystal Display Device and Method for Fabricating the same}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device.

Recently, liquid crystal displays have been spotlighted as next generation advanced display devices having low power consumption, good portability, technology-intensive, and high added value.

Among such liquid crystal display devices, an active matrix liquid crystal display device having a thin film transistor, which is a switching element capable of controlling voltage on / off for each pixel, has received the most attention due to its excellent resolution and video performance.

In general, an LCD device forms an array substrate and a color filter substrate through an array substrate manufacturing process for forming a thin film transistor and a pixel electrode, and a color filter substrate manufacturing process for forming a color filter and a common electrode, respectively. It completes through the liquid crystal cell process through a liquid crystal between them.

FIG. 1 is a three-dimensional view of a portion of a general liquid crystal display, and is shown centering on an active region defined as a region in which a liquid crystal is driven.

As shown in the figure, the upper and lower substrates 10 and 30 face each other with a predetermined distance therebetween, and the liquid crystal layer 50 is interposed between the upper and lower substrates 10 and 30.

A plurality of gates and data lines 32 and 34 cross each other on the lower substrate 30, and a thin film transistor T is formed at a point where the gates and data lines 32 and 34 cross each other. A pixel electrode 46 connected to the thin film transistor T is formed in the pixel area P defined as an area where the gate and the data lines 32 and 34 intersect.

Although not shown in the drawing, the thin film transistor T includes a gate electrode to which a gate voltage is applied, a source and drain electrode to which a data voltage is applied, and a channel for controlling voltage on / off by a difference between the gate voltage and the data voltage ( ch; channel).

The color filter layer 12 and the common electrode 16 are sequentially formed below the upper substrate 10.

Although not shown in detail in the drawing, the color filter layer 12 is composed of a color filter for transmitting only light of a specific wavelength band and a black matrix positioned at a boundary of the color filter to block light on an area where the arrangement of liquid crystals is not controlled.

In addition, upper and lower polarizers 52 and 54 for transmitting only light parallel to the polarization axis are positioned on each outer surface of the upper and lower substrates 10 and 30, and a backlight, which is a separate light source, is provided below the lower polarizer 54. light) is placed.

FIG. 2 is a plan view of one pixel portion of an array substrate for a liquid crystal display device, including a non-display area connected to an external circuit.

As shown in the drawing, gate and data lines 62 and 74 are formed in a direction crossing each other, and a thin film transistor T is formed at a point where the gate and data lines 62 and 74 intersect with each other. The pixel electrode 88 is formed by being connected to the thin film transistor T through the contact hole 80.

Gates and data pads 64 and 73 connected to external circuits are formed at ends of the gate and data lines 62 and 74, respectively, and gate and data through gate and data pad contact holes 82 and 84. Gate and data pad electrodes 90 and 92 which are connected to the pads 64 and 73 and made of the same material as the pixel electrode 88 are formed, respectively.

Each wiring and electrode pattern of the liquid crystal display array substrate is formed by a photolithography process using a photoresist as a photosensitive material.

In the photolithography process, a photoresist layer is coated on a corresponding metal material (or an insulating material or a semiconductor material), a mask having a predetermined pattern is disposed and exposed, and the exposed photoresist layer is developed to develop a photo. A resist layer pattern is formed, and a metal material is etched using the photoresist layer pattern as a mask to form a wiring or electrode pattern.

In this case, the photoresist material may be divided into a positive type in which the exposed part is developed and a negative type in which the exposed part remains. In general, a positive photoresist material is used in an array process. .

Since the number of steps is determined according to the number of masks, the photolithography step will be referred to as a mask step.

3A to 3E are cross-sectional views illustrating the cross sections cut along the cutting lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc of FIG. 2 according to a mask process.

In FIG. 3A, after the first metal material is deposited, the gate pad 64 and the gate electrode 60 are formed by the first mask process.

Although not shown in the drawings, a gate wiring including a gate electrode 60 and a gate pad 64 is formed in this step.

In FIG. 3B, after the first insulating material, pure amorphous silicon (a-Si), and impurity amorphous silicon (n + a-Si) are successively deposited, the first insulating material is used as the gate insulating film 68 and the pure amorphous silicon layer The impurity amorphous silicon layer is a step of forming the semiconductor layer 70 by forming the active layer 70a and the ohmic contact layer 70b at positions covering the gate electrode 60 by the second mask process.

In FIG. 3C, after depositing the second metal material, the data pad 73 and the source and drain electrodes 76 and 78 which are spaced apart from each other on the semiconductor layer 70 by a third mask process are formed. Step.

In this step, the ohmic contact layer 70b of the separation section is removed using the source and drain electrodes 76 and 78 as a mask, and the active layer 70a constituting the lower layer is exposed to form a channel ch. Process is included.

The gate electrode 60, the semiconductor layer 70, the source and drain electrodes 76 and 78 form a thin film transistor T.

In more detail, in order to completely remove the ohmic contact layer 70b of the channel ch portion, an overetch process is performed. The thickness of the active layer 70a varies according to the degree of excessive etching. In order to keep the electrical characteristics of the thin film transistors constant, it is necessary to deposit thick amorphous silicon in consideration of the degree of excessive etching.

In FIG. 3D, after depositing (or coating) the second insulating material, the drain contact hole 80 exposing a part of the drain electrode 78, the gate pad 64, and the data pad 73 by a fourth mask process. ) And forming a protective layer 86 having gates and data pad contact holes 82 and 84.

In FIG. 3E, after the transparent conductive material is deposited, the pixel electrode 88, the gate and the data pad electrodes 90 and 92 are formed by the fifth mask process.

As described above, in the conventional array process for liquid crystal display devices, an array substrate is manufactured by a five mask process.

However, the mask process requires equipment for each deposition (coating), exposure, development, and etching process, and the process cost is high as the physical and chemical processes are repeated, and there is a high possibility of damaging other devices during the process, so the process efficiency This has the disadvantage of falling.

In addition, in the conventional array process using 5 masks, the channel is formed through a transient etching process. However, since the electrical characteristics of the thin film transistor depend on the transient etching process, the process conditions become difficult.

In order to solve the above problems, an object of the present invention is to provide an array substrate for a liquid crystal display device with improved production yield in a low mask process.

It is still another object of the present invention to provide an array substrate for a liquid crystal display device in which channel fabrication is simplified by a low mask process.

To this end, in the present invention, an array substrate for a liquid crystal display device is manufactured by a four mask process including a gate process, a semiconductor layer and a source process, a protective layer process, and an ITO process.

1 is a three-dimensional view of a portion of a general liquid crystal display device.

2 is a plan view of one pixel portion of an array substrate for a liquid crystal display device;

3A to 3E are cross-sectional views illustrating the cross sections cut along the cutting lines IIIa-IIIa, IIIb-IIIb, and IIIc-IIIc of FIG. 2 according to a mask process.

4 is a plan view of an array substrate for a liquid crystal display according to the present invention.

5A to 5D are cross-sectional views illustrating the cross sections cut along the cutting lines Va-Va, Vb-Vb, and Vc-Vc of FIG.

<Description of Symbols for Main Parts of Drawings>

100 transparent substrate 110 gate electrode

114: gate pad 118: gate insulating film

120a: first active layer 120b: ohmic contact layer

120: semiconductor layer 124: data wiring

126 source electrode 128 drain electrode

130: data pad 131: drain contact hole

134: data pad contact hole 136: second active layer

138: protective layer 140: pixel electrode

142: gate pad electrode 144: data pad electrode

In order to achieve the above object, in one aspect of the present invention, there is provided a semiconductor device comprising: a gate wiring formed on a substrate in a first direction and having a gate electrode and a gate pad at one end thereof; A semiconductor layer in which the first active layer and the ohmic contact layer are sequentially formed in the state insulated by the gate wiring and the gate insulating film; A data line positioned in a region corresponding to the semiconductor layer and formed in a second direction crossing the first direction, the data line including a source electrode and a data pad at one end thereof, and a drain disposed at a predetermined distance from the source electrode; An electrode; A second active layer and a protection layer positioned in a region corresponding to the data line and the drain electrode, the second active layer and the protective layer having the drain electrode, the drain contact hole partially exposing the data pad, and the data pad contact hole in common; A channel part disposed in the separation period between the source and drain electrodes, the channel part including a second active layer connected to the first active layer on an exposed gate insulating layer in a portion corresponding to the separation period; A gate pad electrode directly covering the gate pad; A data pad electrode connected to the data pad through the data pad contact hole; An array substrate for a liquid crystal display device including a pixel electrode connected to a drain electrode through the drain contact hole is provided.

The first and second active layers may be amorphous silicon (a-Si), the ohmic contact layer may be impurity amorphous silicon (n + a-Si), and the material of the pixel electrode, the gate, and the data pad electrode may be a transparent conductive material. It features.

A buffer layer is included below the second active layer, and the material of the buffer layer is silicon nitride (SiNx).

The pixel electrode is positioned in a pixel area defined as an area where a gate and a data line cross each other, and the pixel electrode on the pixel area is configured to be in contact with a substrate from which a gate insulating film is removed.

In still another aspect of the present invention, after the first metal material is formed on the substrate, the first metal material is positioned in the first direction by a first mask process including an exposure, development, and etching process. Forming a gate wiring comprising a gate pad; After the first insulating material, amorphous silicon, impurity amorphous silicon, and second metal material are sequentially formed on the substrate on which the gate wiring is formed, the first active layer is positioned in the second direction by a second mask process. A semiconductor layer having an ohmic contact layer formed sequentially, a data line including a source and a data pad at one end thereof, and a drain electrode spaced apart from the source electrode at a predetermined distance, and forming a gate between the source and drain electrodes. Exposing the insulating film to form a channel region; After forming amorphous silicon and a second insulating material in order on the substrate on which the data wiring and the drain electrode are formed, a gate insulating film and the drain electrode having a region corresponding to the data wiring and the drain electrode by a third mask process Forming a drain contact hole partially exposing the data pad, a second active layer having the data pad contact hole, and a protective layer; Completing a channel portion including a gate insulating film on the channel region and a second active layer connected to the first active layer on the gate insulating film; A pixel electrode and a data pad electrode respectively connected to the drain electrode and the data pad through the drain contact hole and the data pad contact hole by a fourth mask process using a transparent conductive material on the substrate on which the channel part is completed; It provides a method of manufacturing an array substrate for a liquid crystal display device comprising the step of forming each of the gate pad electrode directly covering the gate pad.

The first insulating material is silicon nitride (SiNx), and in the forming of the second active layer and the protective layer, forming a buffer layer under the second active layer, wherein the buffer layer comprises a first insulating material It is the same material and the thickness of the buffer layer is characterized in that the 100 ~ 500 Å.

In addition, the deposition thicknesses of the first and second active layers may be selected in the same range.

In the present invention, an array substrate for a liquid crystal display device is provided by a four-mask process consisting of a gate process, a semiconductor layer and a source process, a protective layer process, and an ITO process.

In more detail, in the gate process, a gate wiring including a gate electrode and a gate pad is formed, and in the semiconductor layer and the source process, a gate insulating film, a first active layer, an ohmic contact layer, a source and a drain electrode are formed. And the first active layer and the ohmic contact layer are removed so that the gate insulating film is exposed in the channel portion of the separation section between the drain electrodes. Next, in the passivation layer process, the second active layer and the passivation layer are sequentially formed, and then, the drain contact hole and the data pad contact hole are formed. The second active layer formed on the gate insulating layer of the channel portion is formed in the channel. Is achieved. In the ITO process, four masks are formed by forming a pixel electrode connected to the drain electrode through the drain contact hole, a data pad electrode connected to the data pad through the data pad contact hole, and a gate pad electrode directly covering the gate pad. An array substrate for a liquid crystal display device is produced.

In the present invention, the protective layer may include an insulating material serving as a buffer layer in the lower layer of the second active layer.

According to the present invention, an array substrate for a liquid crystal display device is manufactured by using a less mask process, and a channel is more easily manufactured than a process of exposing an active layer by a conventional excessive etching process in forming a channel. It features.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

4 is a plan view of an array substrate for a liquid crystal display according to the present invention.

As shown in the drawing, the gate wiring 112 is formed in the first direction, the data wiring 124 is formed in the second direction crossing the first direction, and the gate and the data wiring 112 and 124 intersect with each other. The thin film transistor (T) is formed at the point.

The thin film transistor T includes a gate electrode 110 branched from the gate line 112, a semiconductor layer 120 covering the gate electrode 110, a source electrode 126 branched from the data line 124, and The drain electrode 128 is positioned to be spaced apart from the source electrode 126 by a predetermined distance. In the pixel region defined as the region where the gate and the data lines 112 and 124 intersect, the pixel electrode 140 connected to the drain electrode 128 of the thin film transistor T through the drain contact hole 131 is formed. Formed.

In addition, a channel CH is positioned between the source and drain electrodes 126 and 128, and the channel CH is formed by another amorphous silicon layer in addition to the amorphous silicon layer forming the semiconductor layer 120. It is done.

The gate and data pads 114 and 130 are formed at one end of the gate and data lines 112 and 124, respectively, and the gate pad electrode 142 directly covering the gate pad 114, and the data pad. The data pad electrode 144 is connected to the data pad 130 through the contact hole 134.

The material forming the pixel electrode 140, the gate and the data pad electrodes 142 and 144 is selected from a transparent conductive material, and is preferably made of indium tin oxide (ITO).

Although not shown in the drawings, the liquid crystal display array substrate further includes a storage capacitor C _ST by a front gate method, a common method, or another method.

5A to 5D are cross-sectional views illustrating the cross sections cut along the cutting lines Va-Va, Vb-Vb, and Vc-Vc of FIG.

In FIG. 5A, after depositing a first metal material on the transparent substrate 100, a gate electrode 110 and a gate pad 114 are formed by a first mask process.

Although not shown in the drawings, a gate wiring including the gate electrode 110 and the gate pad 114 is formed in this step.

The first metal material is selected from a metal material having a low resistivity value to prevent a delay of gate signal processing. Preferably, the first metal material is a double layer metal material having aluminum neodymium (AlNd) as a lower layer and molybdenum (Mo) as a top layer. It is to use.

The deposition process is typically performed using a sputtering apparatus.

In FIG. 5B, a first insulating material, pure amorphous silicon, impurity amorphous silicon, and a second metal material are sequentially deposited on the substrate having passed through FIG. 5A, and then the first insulating material is used as the gate insulating film 118. , The semiconductor layer 120 including the first active layer 120a and the ohmic contact layer 120b using pure amorphous silicon, impurity amorphous silicon, and a second metal material as a second mask process, a data line 124, a source, and Forming the drain electrodes 126 and 128 and the data pad 130, respectively.

In this case, the first insulating material, pure amorphous silicon, and impurity amorphous silicon may be continuously deposited using a PECVD (Plasma Enhanced Chemical Vapor Deposition) device, and the second metal material may be deposited using a sputtering device.

In more detail, the second metal material is drained from the data line 124 including the data pad 130 and the source electrode 126 and the drain electrode 128 at a predetermined interval by a wet etching method. ).

Next, the first active layer 120a and the ohmic contact layer 120b may include the amorphous silicon and the impurity amorphous silicon as patterns corresponding to the source and drain electrodes 126 and 128, the data pad 130, and the data line. To form a semiconductor layer 120.

In particular, in the present invention, the channel portion VI exposing the gate insulating layer 118 is formed in a section between the source and drain electrodes 126 and 128.

Conventionally, the active layer is exposed to the channel portion by using the source and drain electrodes as masks in the source process, but in the present invention, the semiconductor layer 120 material is removed at this stage, and an additional active layer material is additionally configured. Characterized in that.

The first insulating material is selected from a silicon insulating material, preferably silicon nitride (SiNx).

The second metal material is selected from a metal material having strong chemical corrosion resistance, and preferably, any one of molybdenum, nickel (Ni), chromium (Cr), and tungsten (W).

In FIG. 5C, after the amorphous silicon and the second insulating material are sequentially deposited on the substrate having passed through FIG. 5B, the drain electrode 128 and the data pad 130 are partially exposed by the third mask process. The second active layer 136 and the protection layer 138 having the contact hole 131 and the data pad contact hole 134 in common are sequentially formed.

In this step, the gate wiring 112 including the gate pad 114 is exposed in its entirety, and the gate insulating layer 118 of the pixel region P is removed.

In particular, the second active layer 136 positioned in the channel part VI forms a channel CH together with the gate insulating layer 118 forming a lower layer while being connected to both sides of the first active layer 120a. It is done.

The protective layer 138 is used to prevent damage or deterioration of the thin film transistor caused by rubbing or moisture infiltration during the liquid crystal cell process of the liquid crystal display device. The second insulating material constituting the second insulating material is selected from a silicon insulating material or an organic insulating material, preferably one of a silicon nitride film, a silicon oxide film (SiOx), and a benzocyclobutene (BCB).

In FIG. 5D, the gate pad electrode 142, the drain contact hole 131, and the data pad which directly cover the gate pad 114 after depositing a transparent conductive material on the substrate having passed through FIG. 5C are deposited. The drain electrode 128, the pixel electrode 140 connected to the data pad 130, and the data pad electrode 144 are formed through the contact hole 134, respectively.

Indium Tin Oxide (ITO) is generally used as this transparent conductive material.

As described above, the array substrate for a liquid crystal display device according to the present invention can provide a liquid crystal display device having improved production yield with reduced process cost and process time as manufactured by a four mask process.

In addition, in the present invention, in the forming of the second active layer for channel formation, a separate insulating material may be included under the second active layer.

<Example 2>

Embodiment 2 relates to an embodiment including forming a buffer layer under a second active layer in a third mask process in fabricating an array substrate for a four mask liquid crystal display device.

FIG. 6 is a cross-sectional view of an array substrate for a four mask liquid crystal display according to a second exemplary embodiment of the present invention. The thin film transistor unit, the gate, and the data pad unit are illustrated in FIG. do.

As illustrated, a gate pad 214 and a gate electrode 210 are formed on the transparent substrate 100, and the first active layer 220a and the ohmic contact layer 220b are formed on the gate electrode 210. A semiconductor layer 220 is formed, a data line 224 having a pattern corresponding to the semiconductor layer 220, source and drain electrodes 226 and 228, and a data pad 230 are formed. 218, the data wiring 224, the source and drain electrodes 226 and 228, the drain electrode 228 and the drain contact hole 231 partially exposing the data pad 230, and the data on the data pad 230. The buffer layer 235, the second active layer 236, and the protective layer 238 having the pad contact hole 234 in common are sequentially formed.

The gate pad electrode 242, the drain contact hole 231, and the data pad contact hole 234, which directly cover the gate pad 214, are connected to the drain electrode 228 and the data pads 214 and 230. The pixel electrode 240 and the data pad electrode 244 are formed, respectively.

In the present exemplary embodiment, a separate buffer layer 235 is disposed on a lower layer of the second active layer 236 formed in a pattern corresponding to the data line 224, the source and drain 226 and 228, and the data pad 230. By forming, the metal materials in contact with the second active layer 236 are insulated from each other.

In this case, the material constituting the buffer layer 235 is selected from a silicon insulating material, preferably a silicon nitride film.

For example, the deposition thickness of the buffer layer 235 made of the silicon nitride film 235 is preferably set to 100 mW to 500 mW.

In order to increase the transmittance in the pixel region P, the pixel electrode 240 is positioned directly on the gate insulating layer 218 in the pixel region P.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

As described above, the array substrate for a four mask liquid crystal display device according to the present invention has an advantage of providing a liquid crystal display device having improved production yield by increasing process efficiency as the number of masks decreases.

Claims (12)

A gate wiring formed on the substrate in a first direction and having a gate electrode and a gate pad at one end thereof; A semiconductor layer in which the first active layer and the ohmic contact layer are sequentially formed in the state insulated by the gate wiring and the gate insulating film; A data line positioned in a region corresponding to the semiconductor layer and formed in a second direction crossing the first direction, the data line including a source electrode and a data pad at one end thereof, and a drain spaced apart from the source electrode at a predetermined interval; An electrode; A second active layer and a protection layer positioned in a region corresponding to the data line and the drain electrode, the second active layer and the protective layer having the drain electrode, the drain contact hole partially exposing the data pad, and the data pad contact hole in common; A channel part disposed in the separation period between the source and drain electrodes, the channel part including a second active layer connected to the first active layer on an exposed gate insulating layer in a portion corresponding to the separation period; A gate pad electrode directly covering the gate pad; A data pad electrode connected to the data pad through the data pad contact hole; A pixel electrode connected to the drain electrode through the drain contact hole Array substrate for a liquid crystal display device comprising a. The method of claim 1, And the first and second active layers are amorphous silicon (a-Si) and the ohmic contact layer is an impurity amorphous silicon (n + a-Si). The method of claim 1, And the material forming the pixel electrode, the gate and the data pad electrode is a transparent conductive material. The method of claim 1, An array substrate for a liquid crystal display device including a buffer layer under the second active layer. The method of claim 4, wherein The material of the buffer layer is a silicon nitride film (SiNx) array substrate for a liquid crystal display device. The method of claim 1, And the pixel electrode is positioned in a pixel area defined as an area where a gate and a data line cross each other, and the pixel electrode on the pixel area is in contact with a substrate from which a gate insulating film is removed. After the first metal material is formed on the substrate, a gate wiring including a gate electrode and a gate pad at one end is positioned in a first direction by a first mask process including an exposure, development, and etching process. Making a step; After the first insulating material, amorphous silicon, impurity amorphous silicon, and second metal material are sequentially formed on the substrate on which the gate wiring is formed, the first active layer is positioned in the second direction by a second mask process. A semiconductor layer having an ohmic contact layer formed sequentially, a data line including a source and a data pad at one end thereof, and a drain electrode spaced apart from the source electrode at a predetermined distance, and forming a gate between the source and drain electrodes. Exposing the insulating film to form a channel region; After forming amorphous silicon and a second insulating material in order on the substrate on which the data wiring and the drain electrode are formed, a gate insulating film and the drain electrode having a region corresponding to the data wiring and the drain electrode by a third mask process Forming a drain contact hole partially exposing the data pad, a second active layer having the data pad contact hole, and a protective layer; Completing a channel portion including a gate insulating film on the channel region and a second active layer connected to the first active layer on the gate insulating film; A pixel electrode and a data pad electrode respectively connected to the drain electrode and the data pad through the drain contact hole and the data pad contact hole by a fourth mask process using a transparent conductive material on the substrate on which the channel part is completed; Respectively forming gate pad electrodes directly covering the gate pads; Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 7, wherein The first insulating material is a silicon nitride film (SiNx) manufacturing method of an array substrate for a liquid crystal display device. The method of claim 7, wherein The forming of the second active layer and the protective layer comprises forming a buffer layer under the second active layer. The method according to any one of claims 7 to 9, The buffer layer is a manufacturing method of an array substrate for a liquid crystal display device of the same material as the first insulating material. The method of claim 9, The thickness of the buffer layer is a manufacturing method of the array substrate for a liquid crystal display device 100 ~ 500 Å. The method of claim 7, wherein And the deposition thicknesses of the first and second active layers are selected in the same range.