CN102683353B - Array substrate for display device and producing method of array substrate - Google Patents
Array substrate for display device and producing method of array substrate Download PDFInfo
- Publication number
- CN102683353B CN102683353B CN201210099582.4A CN201210099582A CN102683353B CN 102683353 B CN102683353 B CN 102683353B CN 201210099582 A CN201210099582 A CN 201210099582A CN 102683353 B CN102683353 B CN 102683353B
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- Prior art keywords
- scan line
- data wire
- oxide semiconductor
- semiconductor layer
- array substrate
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000011241 protective layer Substances 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 4
- 238000003672 processing method Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Abstract
Disclosed are an array substrate for a display device and a producing method of the array substrate. The array substrate for the display device comprises the substrate having a pixel region, a scanning line, a grid electrode, a data line, an insulation layer, an oxide semiconductor layer and a protective layer, wherein the scanning line, the grid electrode and the data line are located on the substrate, the grid electrode is connected with the scanning line, the scanning line and the data line intersect so as to define the pixel region, the data line is broken at the intersection position of the data line and the scanning line, the insulation layer is arranged above the scanning line, the grid electrode and the data line, the insulation layer is provided with a contact hole which is exposed out of a terminal portion of the scanning line, a terminal portion of the data line and two sides of the position where a source electrode and the data line are disconnected with the scanning line, the oxide semiconductor layer is arranged above the insulation layer and the pixel region, the oxide semiconductor layer is connected to the terminal portion of the scanning line, the terminal portion of the data line, the source electrode and the two sides of the data line at the position where the data line is disconnected with the scanning line, and the protective layer is arranged on the oxide semiconductor layer above the grid electrode. An ion implantation method or an annealing processing method is used, so that the oxide semiconductor layer of a region which is outside the protective layer forms a transparent electrode having conductor characteristics.
Description
Technical field
The present invention relates to the array base palte for display device, particularly comprise the array base palte of the thin-film transistor with oxide semiconductor layer, and the manufacture method of this array base palte.
Background technology
The processing procedure of metal current oxide semiconductor TFT (thin-film transistor) is similar with existing amorphous silicon processing procedure, except traditional BCE (Back Channel Etching, back of the body channel etch)) outside structure, consider characteristic of semiconductor and have ESL (Etch Stop Layer, etching barrier layer) and the coplanar framework of Co-Planar, required processing procedure needs five roads or six road light shields, and processing procedure is comparatively complicated, and manufacturing cost is higher.Fig. 1 is for adopt IGZO (Indium Gallium Zinc Oxide at present; indium gallium zinc oxide) make the main ESL structure of thin-film transistor; with the BCE similar of a-Si (amorphous silicon) thin-film transistor, main difference is adding that ESL dielectric protection layer semiconductor layer is to maintain good TFT characteristic.
Summary of the invention
Goal of the invention: for above-mentioned prior art Problems existing and deficiency, the object of this invention is to provide and a kind ofly can simplify processing procedure for the array base palte of display device and the manufacture method of this array base palte, reduces manufacturing cost.
Technical scheme: for achieving the above object, the first technical scheme that the present invention adopts is a kind of array base palte for display device, comprising:
There is the substrate of pixel region;
Be positioned at the scan line on described substrate, grid and data wire, described grid is connected to described scan line, and described scan line and data wire intersect to limit described pixel region, and described data wire disconnects at the infall with described scan line;
Be positioned at the insulating barrier on described scan line, grid and data wire, this insulating barrier has the portion of terminal, the portion of terminal of data wire, source electrode and the contact hole of data wire in the both sides with scan line gap that expose described scan line;
Be positioned at the oxide semiconductor layer on described insulating barrier and pixel region, described oxide semiconductor layer is connected to the portion of terminal of described scan line, the portion of terminal of data wire, source electrode and data wire in the both sides with scan line gap by described contact hole;
To be positioned at above described grid and the protective layer be positioned on oxide semiconductor layer;
Adopt the mode of ion implantation or annealing in process to make to be positioned at protective layer and become the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
The material preferred indium gallium zinc oxide of described oxide semiconductor layer.
The preferred silicon dioxide of material of described insulating barrier and protective layer or the combination of silicon nitride or silicon dioxide and silicon nitride.
The second technical scheme that the present invention adopts is a kind of method of manufacturing array substrate, comprises the steps:
(1) first light shield: form scan line, grid and data wire on the array base palte with pixel region, described grid is connected to described scan line, described scan line and data wire intersect to limit described pixel region, and described data wire disconnects at the infall with described scan line;
(2) on described scan line, grid and data wire, insulating barrier is formed;
(3) second light shield: form the portion of terminal, the portion of terminal of data wire, source electrode and the contact hole of data wire in the both sides with scan line gap that have and expose described scan line on described insulating barrier;
(4) the 3rd road light shields: form oxide semiconductor layer on described insulating barrier and pixel region, described oxide semiconductor layer is connected to the portion of terminal of described scan line, the portion of terminal of data wire, source electrode and data wire in the both sides with scan line gap by described contact hole;
(5) the 4th road light shields: form protective layer above described grid on oxide semiconductor layer;
(6) adopt the mode of ion implantation or annealing in process to make to be positioned at protective layer and become the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
The material preferred indium gallium zinc oxide of described oxide semiconductor layer.
The preferred silicon dioxide of material of described insulating barrier and protective layer or the combination of silicon nitride or silicon dioxide and silicon nitride.
Beneficial effect: the present invention can simplify the processing procedure of IGZO semiconductor TFT, is reduced to four road light shields by original five to six road light shields, effectively reduces manufacturing cost.
Accompanying drawing explanation
Fig. 1 is the ESL schematic cross-section of prior art metal oxide semiconductor films transistor;
Fig. 2 (A) forms the structural representation of scan line, grid and data wire for the present invention; Fig. 2 (B) is the A-A ' profile of Fig. 2 (A);
Fig. 3 (A) forms the structural representation of insulating barrier and contact hole for the present invention; Fig. 3 (B) is the B-B ' profile of Fig. 3 (A);
Fig. 4 (A) forms the structural representation of IGZO layer for the present invention; Fig. 4 (B) is the C-C ' profile of Fig. 4 (A);
Fig. 5 (A) forms the structural representation of protective layer for the present invention; Fig. 5 (B) is the D-D ' profile of Fig. 5 (A).
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
As shown in Fig. 2 (A) and Fig. 2 (B), the array base palte with pixel region utilize underlying metal form scan line, grid and data wire, described grid is connected to described scan line, described scan line and data wire intersect to limit described pixel region, and described data wire disconnects at the infall with described scan line;
As shown in Fig. 3 (A) and Fig. 3 (B), described scan line, grid and data wire form the insulating barrier of earth silicon material; Described insulating barrier is formed the portion of terminal, the portion of terminal (not shown) of data wire, source electrode (be actually subsequent step and form the position connecting source electrode) and the contact hole of data wire in the both sides with scan line gap that have and expose described scan line;
As shown in Fig. 4 (A) and Fig. 4 (B), described insulating barrier and pixel region are formed IGZO layer, and described IGZO layer is connected to the portion of terminal of described scan line, the portion of terminal (not shown) of data wire, source electrode and data wire in the both sides with scan line gap by described contact hole;
As shown in Fig. 5 (A) and Fig. 5 (B), above described grid, on IGZO layer, form the protective layer of earth silicon material; Adopt the mode of ion implantation to make to be positioned at protective layer and become the transparency electrode with conductor characteristics with the IGZO layer of exterior domain.Now, the IGZO layer bridge joint of transparency electrode is originally known as at the data wire disconnected with scan line infall, and being connected to the source electrode be positioned on the left of protective layer, the IGZO layer on the right side of protective layer is then connected to as drain electrode the IGZO layer (i.e. pixel electrode) being positioned at pixel region; The IGZO layer be positioned at below protective layer remains semiconductor layer, ensures it is the open circuit in electricity between source electrode and drain electrode.
Claims (3)
1. a method for manufacturing array substrate, comprises the steps:
(1) first light shield: form scan line, grid and data wire on the array base palte with pixel region, described grid is connected to described scan line, described scan line and data wire intersect to limit described pixel region, and described data wire disconnects at the infall with described scan line;
(2) on described scan line, grid and data wire, insulating barrier is formed;
(3) second light shield: form the portion of terminal, the portion of terminal of data wire, source electrode and the contact hole of data wire in the both sides with scan line gap that have and expose described scan line on described insulating barrier;
(4) the 3rd road light shields: form oxide semiconductor layer on described insulating barrier and pixel region, described oxide semiconductor layer is connected to the portion of terminal of described scan line, the portion of terminal of data wire, source electrode and data wire in the both sides with scan line gap by described contact hole;
(5) the 4th road light shields: form protective layer above described grid on oxide semiconductor layer;
(6) adopt the mode of ion implantation or annealing in process to make to be positioned at protective layer and become the transparency electrode with conductor characteristics with the oxide semiconductor layer of exterior domain.
2. the method for manufacturing array substrate according to claim 1, is characterized in that: the material of described oxide semiconductor layer is indium gallium zinc oxide.
3. the method for manufacturing array substrate according to claim 1, is characterized in that: the material of described insulating barrier and protective layer is the combination of silicon dioxide or silicon nitride or silicon dioxide and silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210099582.4A CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210099582.4A CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
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| Publication Number | Publication Date |
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| CN102683353A CN102683353A (en) | 2012-09-19 |
| CN102683353B true CN102683353B (en) | 2014-12-17 |
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| CN201210099582.4A Expired - Fee Related CN102683353B (en) | 2012-04-05 | 2012-04-05 | Array substrate for display device and producing method of array substrate |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199094B (en) * | 2013-03-25 | 2016-01-20 | 南京中电熊猫液晶显示科技有限公司 | TFT-LCD array substrate and manufacture method thereof |
| CN103257499A (en) * | 2013-05-28 | 2013-08-21 | 南京中电熊猫液晶显示科技有限公司 | Thin film transistor liquid crystal display (TFT-LCD) array substrate and manufacturing method thereof |
| CN104793420B (en) * | 2015-05-08 | 2018-04-06 | 厦门天马微电子有限公司 | Array base palte and preparation method, display device |
| CN107425008B (en) * | 2015-11-27 | 2020-04-10 | 南京中电熊猫液晶显示科技有限公司 | Array substrate and manufacturing method thereof |
| CN106057818B (en) * | 2016-05-26 | 2019-05-07 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display device |
| CN106201150B (en) * | 2016-08-31 | 2019-04-16 | 武汉华星光电技术有限公司 | Array substrate and touch-control display panel |
| CN106887406B (en) * | 2017-03-29 | 2019-11-15 | 深圳市华星光电半导体显示技术有限公司 | A kind of production method of array substrate |
| CN108008586B (en) * | 2017-12-19 | 2021-04-30 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, array substrate preparation method and display device |
| CN108206182A (en) * | 2017-12-28 | 2018-06-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and its manufacturing method |
| CN111427207B (en) * | 2020-03-31 | 2022-08-12 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114089571B (en) * | 2021-11-30 | 2024-01-16 | 昆山龙腾光电股份有限公司 | Array substrate, manufacturing method and display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478005A (en) * | 2009-02-13 | 2009-07-08 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and manufacturing process thereof |
| CN102157563A (en) * | 2011-01-18 | 2011-08-17 | 上海交通大学 | Method for manufacturing metal oxide thin film transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102034750B (en) * | 2009-09-25 | 2015-03-11 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478005A (en) * | 2009-02-13 | 2009-07-08 | 北京大学深圳研究生院 | Metal oxide thin-film transistor and manufacturing process thereof |
| CN102157563A (en) * | 2011-01-18 | 2011-08-17 | 上海交通大学 | Method for manufacturing metal oxide thin film transistor |
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| CN102683353A (en) | 2012-09-19 |
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