KR20020080857A - Method for manufacturing thin film transistor liquid crystal display device - Google Patents
Method for manufacturing thin film transistor liquid crystal display device Download PDFInfo
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- KR20020080857A KR20020080857A KR1020010020704A KR20010020704A KR20020080857A KR 20020080857 A KR20020080857 A KR 20020080857A KR 1020010020704 A KR1020010020704 A KR 1020010020704A KR 20010020704 A KR20010020704 A KR 20010020704A KR 20020080857 A KR20020080857 A KR 20020080857A
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- film transistor
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000010409 thin film Substances 0.000 title claims abstract description 45
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000005530 etching Methods 0.000 claims abstract description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000004380 ashing Methods 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 6
- 238000001312 dry etching Methods 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 2
- 229910001882 dioxygen Inorganic materials 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 26
- 150000002739 metals Chemical class 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
- G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
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- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
Description
본 발명은 박막트랜지스터 액정표시장치의 제조방법에 관한 것으로, 보다 상세하게는 백채널에치형 박막트랜지스터 액정표시장치의 제조방법에 있어서 소오스/드레인 에칭공정과 오믹층 에칭공정 사이에 포토레지스트 스트립공정 또는 포토레지스트 에싱공정을 추가하여 낮은 누설전류값을 갖는 박막트랜지스터 액정표시장치의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, in a method for manufacturing a back channel etch type thin film transistor liquid crystal display device, a photoresist strip process between a source / drain etching process and an ohmic layer etching process. The present invention relates to a method of manufacturing a thin film transistor liquid crystal display device having a low leakage current value by adding a photoresist ashing process.
주지된 바와 같이, 백채널에치(BCE)형 박막트랜지스터 구조에서는 소오스/드레인 메탈과 비정질실리콘사이에 오믹접합(Ohmic junction)을 형성하기 위해 비정질실리콘에 5족 원소인 인(P)을 첨가한 도핑된 비정질실리콘층이 필요하다.As is well known, in the back channel etch (BCE) type thin film transistor structure, phosphorus (P), which is a Group 5 element, is added to the amorphous silicon to form an ohmic junction between the source / drain metal and the amorphous silicon. A doped amorphous silicon layer is needed.
이러한 도핑된 비정질실리콘은 비정질실리콘층과 소오스/드레인 사이에서 접촉저항을 낮추기 위한 목적이고 실제로 전자가 이동하는 채널은 도핑된 비정질실리콘층 에칭시 형성되는 비정질실리콘층, 즉 채널층이다.Such doped amorphous silicon is intended to reduce contact resistance between the amorphous silicon layer and the source / drain, and the channel through which electrons move is an amorphous silicon layer, that is, a channel layer formed during etching of the doped amorphous silicon layer.
도 1은 종래 기술에 따른 소오스/드레인 에칭후의 박막트랜지스터의 단면도이고, 도 2는 종래 기술에 따른 도핑된 비정질실리콘층 에칭후의 박막트랜지스터의 단면도이고, 도 3은 종래 기술에 따른 포토레지스트 스트립후 박막트랜지스터의 단면도이다.1 is a cross-sectional view of a thin film transistor after source / drain etching according to the prior art, FIG. 2 is a cross-sectional view of a thin film transistor after etching a doped amorphous silicon layer according to the prior art, and FIG. 3 is a thin film after a photoresist strip according to the prior art. A cross section of a transistor.
먼저, 도 1에 도시된 바와 같이, 기판(10),게이트 전극(12),절연막(14),비정질실리콘층(16),도핑된 비정질실리콘층(18),소오스(20a) 및 드레인(20b),포토레지스트(22)가 형성되어 있는 경우, 소오스/드레인(20a)(20b)의 습식에칭(wet etching)시에는 포토레지스트(22)의 하부에 까지 에천트가 침입하여 에칭이 진행된다. 따라서, 포토레지스트(22)를 통해 측정된 채널의 길이(L2)보다 실제 소오스(20a)와 드레인(20b)간의 채널의 길이(L1)는 더 큰 값을 갖는다.First, as shown in FIG. 1, the substrate 10, the gate electrode 12, the insulating film 14, the amorphous silicon layer 16, the doped amorphous silicon layer 18, the source 20a and the drain 20b. In the case where the photoresist 22 is formed, an etchant penetrates into the lower portion of the photoresist 22 during wet etching of the source / drain 20a and 20b to perform etching. Therefore, the length L1 of the channel between the actual source 20a and the drain 20b has a larger value than the length L2 of the channel measured through the photoresist 22.
이어, 도 2에 도시된 바와 같이, 포토레지스트(22)가 도포된 채로 도핑된 비정질실리콘층(18)의 에칭공정을 진행하면 L1이 아닌 L2길이로 에칭된다. 그 다음, 도 3에 도시된 바와 같이, 포토레지스트 스트립(PR strip)공정을 진행하면 박막트랜지스터를 완성한다.Subsequently, as shown in FIG. 2, the etching process of the doped amorphous silicon layer 18 with the photoresist 22 applied is etched to L2 length rather than L1. Next, as shown in FIG. 3, the thin film transistor is completed by performing a photoresist strip process.
그러나, 상기와 같은 박막트랜지스터는 포토레지스트 하부로의 오버에칭 현상으로 인하여 후속의 도핑된 비정질실시콘층 에칭시, 소오스/드레인 사이에 도핑된 실리콘층이 완전히 제거되지 않으며, 에칭중 포토레지스트 성분(C,H,O등)이 채널영역에 잔류하여 채널을 오염시키게 된다.However, such a thin film transistor does not completely remove the doped silicon layer between the source / drain during etching of the doped amorphous silicon layer due to the overetching phenomenon under the photoresist. , H, O, etc.) remain in the channel region to contaminate the channel.
따라서, 박막트랜지스터가 구동하여 투명전도막과 공통전극 사이에 전하가 충전되어 있는 동안 포토레지스트 성분에 의한 채널의 오염 또는 에칭되지 않고 잔류하는 도핑된 비정질실리콘층에 의해 누설전류 양이 증가할 수 있다.Accordingly, the amount of leakage current may increase due to the doped amorphous silicon layer remaining without being etched or etched from the channel by the photoresist component while the thin film transistor is driven to charge charge between the transparent conductive film and the common electrode. .
이에 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법은 종래 기술의 문제점을 해결하고자 안출된 것으로, 본 발명의 목적은 소오스/드레인 에칭공정후 오믹층 에칭공정전에 포토레지스트 스트립공정 또는 포토레지스트 에싱공정을 추가하여 채널영역내에 남아있는 도핑된 비정질실리콘을 제거하여 누설전류의 양을 감소시키는 박막트랜지스터 액정표시장치의 제조방법을 제공함에 있다.Accordingly, a method of manufacturing a thin film transistor liquid crystal display device according to the present invention is devised to solve the problems of the prior art, and an object of the present invention is a photoresist strip process or a photoresist ashing process before an ohmic layer etching process after a source / drain etching process. The present invention provides a method of manufacturing a thin film transistor liquid crystal display device by removing the doped amorphous silicon remaining in the channel region to reduce the amount of leakage current.
도 1은 종래 기술에 따른 소오스/드레인 에칭후의 박막트랜지스터의 단면도.1 is a cross-sectional view of a thin film transistor after source / drain etching according to the prior art.
도 2는 종래 기술에 따른 도핑된 비정질실리콘층 에칭후의 박막트랜지스터의 단면도.2 is a cross-sectional view of a thin film transistor after etching a doped amorphous silicon layer in accordance with the prior art.
도 3은 종래 기술에 따른 포토레지스트 스트립후 박막트랜지스터의 단면도.3 is a cross-sectional view of a thin film transistor after a photoresist strip according to the prior art.
도 4는 본 발명의 실시예 1에 따른 소오스/드레인 메탈 에칭후 박막트랜지스터의 단면도.4 is a cross-sectional view of a thin film transistor after source / drain metal etching according to Example 1 of the present invention;
도 5는 본 발명의 실시예 1에 따른 포토레지스트 스트립후의 박막트랜지스터의 단면도.Fig. 5 is a sectional view of the thin film transistor after the photoresist strip according to the first embodiment of the present invention.
도 6은 본 발명의 실시예 1에 따른 오믹층 에칭후의 박막트랜지터의 단면도.6 is a cross-sectional view of a thin film transistor after ohmic layer etching according to Embodiment 1 of the present invention;
도 7은 본 발명의 실시예 2에 따른 소오스/드레인 메탈 에칭후 박막트랜지스터의 단면도.7 is a cross-sectional view of a thin film transistor after source / drain metal etching according to Example 2 of the present invention;
도 8은 본 발명의 실시예 2에 따른 포토레지스트 에싱후의 박막트랜지스터의 단면도.8 is a cross-sectional view of a thin film transistor after photoresist ashing according to Example 2 of the present invention;
도 9는 본 발명의 실시예 2에 따른 오믹층 에칭후의 박막트랜지스터의 단면도.9 is a cross-sectional view of a thin film transistor after ohmic layer etching according to Embodiment 2 of the present invention;
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100,200;기판112,212;게이트100,200; Substrate 112,212; Gate
114,214;절연막116,216;채널층114,214; insulating film 116,216; channel layer
118,218;오믹층120a,220a;소오스118,218; ohmic layers 120a, 220a; source
120b,220b;드레인122,222;포토레지스트120b, 220b; drain 122,222; photoresist
상기와 같은 본 발명의 목적을 달성하기 위한 본 발명의 실시예 1에 따른 박막트랜지스터 액정표시장치의 제조방법은, 기판상에 게이트와 절연막, 채널층, 오믹층 및 소오스/드레인 메탈 에칭공정을 포함하여 구성되는 박막트랜지스터 액정표시장치의 제조방법에 있어서, 상기 소오스/드레인 메탈 에칭공정후, 포토레지스트 스트립공정과 오믹층 에칭공정을 순차로 진행하는 것을 특징으로 한다.A method of manufacturing a thin film transistor liquid crystal display device according to Embodiment 1 of the present invention for achieving the above object of the present invention includes a gate and insulating film, a channel layer, an ohmic layer and a source / drain metal etching process on a substrate. In the method of manufacturing a thin film transistor liquid crystal display device, the photoresist strip process and the ohmic layer etching process are sequentially performed after the source / drain metal etching process.
또한, 상기와 같은 본 발명의 목적을 달성하기 위한 본 발명의 실시예 2에 따른 박막트랜지스터 액정표시장치의 제조방법은, 기판상에 게이트와 절연막, 채널층, 오믹층 및 소오스/드레인 메탈 에칭공정을 포함하여 구성되는 박막트랜지스터 액정표시장치의 제조방법에 있어서, 상기 소오스/드레인 메탈 에칭공정후, 포토레지스트 에싱공정과 오믹층 에칭공정을 순차로 진행하는 것을 특징으로 한다.In addition, the manufacturing method of the thin film transistor liquid crystal display device according to the second embodiment of the present invention for achieving the above object of the present invention, the gate and insulating film, the channel layer, ohmic layer and source / drain metal etching process on the substrate In the method for manufacturing a thin film transistor liquid crystal display device comprising a, characterized in that after the source / drain metal etching process, the photoresist ashing process and the ohmic layer etching process is sequentially performed.
이하 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a thin film transistor liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명의 실시예 1에 따른 소오스/드레인 메탈 에칭후 박막트랜지스터의 단면도이고, 도 5는 본 발명의 실시예 1에 따른 포토레지스트 스트립후의 박막트랜지스터의 단면도이고, 도 6은 본 발명의 실시예 1에 따른 오믹층 에칭후의 박막트랜지터의 단면도이다.4 is a cross-sectional view of a thin film transistor after source / drain metal etching according to Embodiment 1 of the present invention, FIG. 5 is a cross-sectional view of a thin film transistor after a photoresist strip according to Embodiment 1 of the present invention, and FIG. It is sectional drawing of the thin film transistor after ohmic layer etching which concerns on Example 1. FIG.
먼저, 본 발명을 설명하기에 앞서 기판(100)상에 게이트(112),절연막(114),채널층(116), 오믹층(118), 소오스/드레인 메탈(120a)(120b) 및 포토레지스트(122)가 이미 형성되어 있다고 가정한다.First, before describing the present invention, the gate 112, the insulating film 114, the channel layer 116, the ohmic layer 118, the source / drain metals 120a and 120b and the photoresist on the substrate 100 are described. Assume that 122 is already formed.
여기서, 상기 소오스/드레인 메탈(120a)(120b)은 Mo/Al/Mo, Mo/AlNd/Mo, Cr, 또는 Cr/Al을 포함하며, 소오스/드레인 메탈로 Mo/Al/Mo 또는 Mo/AlNd/Mo을 사용하는 경우, 즉 3개층의 복합층으로 소오스/드레인을 형성하는 경우 상부층의 Mo은 150 내지 1,000Å 두께로 형성하는 것이 바람직하다.Here, the source / drain metals 120a and 120b include Mo / Al / Mo, Mo / AlNd / Mo, Cr, or Cr / Al, and Mo / Al / Mo or Mo / AlNd as source / drain metals. When / Mo is used, that is, when the source / drain is formed of a composite layer of three layers, the Mo of the upper layer is preferably formed to a thickness of 150 to 1,000 GPa.
그리고, 상기 채널층(116)으로는 비정질실리콘으로, 오믹층(118)으로는 도핑된 비정질실리콘으로 형성하는 것이 바람직하다.The channel layer 116 is preferably formed of amorphous silicon and the ohmic layer 118 is formed of doped amorphous silicon.
본 발명의 실시예 1에 따른 박막트랜지스터 액정표시장치의 제조방법은, 도 4에 도시된 바와 같이, 먼저 상기 포토레지스트(122)를 마스크로 하여 상기 소오스/드레인(120a)(120b)을 에칭한다. 이때, 상기 소오스/드레인 에칭은 에천트를 이용한 습식에칭 또는 플라즈마를 이용한 건식에칭을 포함한다.In the method of manufacturing the thin film transistor liquid crystal display according to the first exemplary embodiment of the present invention, as shown in FIG. 4, first, the source / drain 120a and 120b are etched using the photoresist 122 as a mask. . In this case, the source / drain etching may include wet etching using an etchant or dry etching using plasma.
상기 소오스/드레인 에칭시 소오스/드레인(120a)(120b)이 오버에칭이 되어 상기 포토레지스트(122)하부까지 에칭되어 버린다.During the source / drain etching, the source / drain 120a and 120b are overetched and are etched to the lower portion of the photoresist 122.
그 다음, 도 5에 도시된 바와 같이, 포토레지스트 스트립공정으로 상기 소오스/드레인상의 포토레지스트를 완전히 제거한다. 그리고 나서, 상기소오스/드레인(120a)(120b)을 마스크로 하여 오믹층으로 사용되는 도핑된 비정질실리콘층(118)을 에칭한다.Then, as shown in FIG. 5, the photoresist strip process completely removes the photoresist on the source / drain. Then, the doped amorphous silicon layer 118 used as the ohmic layer is etched using the source / drain 120a and 120b as a mask.
그러면, 도 6에 도시된 바와 같이, 상기 소오스/드레인(120a)(120b) 사이의 채널길이와 도핑된 비정질실리콘층(118)의 길이가 완전히 일치하게 된다. 다시 말하면, 전자가 이동하는 통로역할을 하는 채널층(116)내, 즉 채널영역내 도핑된 비정질실리콘을 완전히 제거할 수 있게 되는 것이다.Then, as shown in Figure 6, the channel length between the source / drain (120a, 120b) and the length of the doped amorphous silicon layer 118 is completely matched. In other words, it is possible to completely remove the doped amorphous silicon in the channel layer 116, that is, the channel region, which serves as a path through which electrons move.
도 7은 본 발명의 실시예 2에 따른 소오스/드레인 메탈 에칭후 박막트랜지스터의 단면도이고, 도 8은 본 발명의 실시예 2에 따른 포토레지스트 에싱후의 박막트랜지스터의 단면도이고, 도 9는 본 발명의 실시예 2에 따른 오믹층 에칭후의 박막트랜지스터의 단면도이다.7 is a cross-sectional view of a thin film transistor after source / drain metal etching according to Embodiment 2 of the present invention, FIG. 8 is a cross-sectional view of a thin film transistor after photoresist ashing according to Embodiment 2 of the present invention, and FIG. It is sectional drawing of the thin film transistor after ohmic layer etching which concerns on Example 2.
본 발명의 실시예 2에 따른 박막트랜지스터 액정표시장치의 제조방법은, 도 7에 도시된 바와 같이, 먼저 상기 포토레지스트(222)를 마스크로 하여 상기 소오스/드레인(220a)(220b)을 에칭한다. 이때, 상기 소오스/드레인 에칭은 에천트를 이용한 습식에칭 또는 플라즈마를 이용한 건식에칭을 포함한다.In the method of manufacturing the thin film transistor liquid crystal display device according to the second exemplary embodiment of the present invention, as shown in FIG. 7, first, the source / drain 220a and 220b are etched using the photoresist 222 as a mask. . In this case, the source / drain etching may include wet etching using an etchant or dry etching using plasma.
상기 소오스/드레인 에칭시 소오스/드레인(220a)(220b)이 오버에칭이 되어 상기 포토레지스트(222)하부까지 에칭되어 버린다.During the source / drain etching, the source / drain 220a and 220b are overetched and are etched to the lower portion of the photoresist 222.
그 다음, 포토레지스트 에싱공정으로 상기 소오스/드레인(220a)(220b)상의 포토레지스트를 제거하면, 도 8에 도시된 바와 같이, 상기 소오스/드레인(220a)(220b)과 일치하도록 일부의 포토레지스트(223)만 잔류한다. 이때, 상기 포토레지스트 에싱공정조건은 전력밀도(Power density)가 3.2 내지 6.0㎽/㎠이고, 산소가스의 유량은 500 내지 900 sccm(standard cubic centimeter per minute), 압력은 1,200 내지 2,200mTorr이다.Then, when the photoresist on the source / drain 220a and 220b is removed by a photoresist ashing process, as shown in FIG. 8, a part of the photoresist is matched with the source / drain 220a and 220b. Only 223 remains. At this time, the photoresist ashing process conditions are the power density (Power density) is 3.2 to 6.0 ㎽ / ㎠, the flow rate of oxygen gas is 500 to 900 sccm (standard cubic centimeter per minute), the pressure is 1,200 to 2,200mTorr.
그 다음, 상기 잔류된 포토레지스트(223)를 마스크로 하여 오믹층으로 사용되는 도핑된 비정질실리콘층(218)을 에칭한다.Then, the doped amorphous silicon layer 218 used as the ohmic layer is etched using the remaining photoresist 223 as a mask.
그러면, 도 9에 도시된 바와 같이, 상기 소오스/드레인(220a)(220b) 사이의 채널길이와 도핑된 비정질실리콘층(218)의 길이가 완전히 일치하게 된다. 다시 말하면, 전자가 이동하는 통로역할을 하는 채널층(216)내, 즉 채녈영역내 도핑된 비정질실리콘을 완전히 제거할 수 있게 되는 것이다.Then, as shown in Figure 9, the channel length between the source / drain (220a, 220b) and the length of the doped amorphous silicon layer 218 is completely matched. In other words, it is possible to completely remove the doped amorphous silicon in the channel layer 216 that acts as a passage for electrons, that is, in the channel region.
본 발명은 소오스/드레인 메탈 에칭후 오믹층 에칭전에 포토레지스트를 제거하는 포토레지스트 스트립 또는 포토레지스트 에싱으로 채널내 도핑된 비정질실리콘을 제거하는 것을 핵심으로 한다. 따라서, 본 발명의 요지를 벗어나지 않는 범위에서 다양하게 변경하여 실시할 수 있다.The present invention focuses on removing doped amorphous silicon in a channel by photoresist strips or photoresist ashing that removes photoresist after source / drain metal etching and before ohmic layer etching. Accordingly, various modifications can be made without departing from the spirit of the invention.
따라서, 하프톤 노광을 이용하여 박막트랜지스터 액정표시장치를 제조하는 공정에 있어서 소오스/드레인 패턴을 마스크로 이용하여 오믹층을 에칭하는 공정도 본 발명의 권리범위에 속한다.Therefore, in the process of manufacturing a thin film transistor liquid crystal display using halftone exposure, the process of etching the ohmic layer using the source / drain pattern as a mask is also within the scope of the present invention.
이상에서 살펴본 바와 같이, 본 발명에 따른 박막트랜지스터 액정표시장치의 제조방법은 다음과 같은 효과가 있다.As described above, the method of manufacturing the thin film transistor liquid crystal display according to the present invention has the following effects.
본 발명에 있어서는 소오스/드레인 메탈 에칭공정후 오믹층 에칭공정전에 포토레지스트를 제거하는 공정을 추가함으로써 소오스와 드레인 사이의 채널내에 도핑된 비정질실리콘을 제거할 수 있고, 또한 오믹층 에칭시 포토레지스트 성분에 의한 채널영역의 오염을 방지할 수 있다.In the present invention, by adding a step of removing the photoresist after the source / drain metal etching process and before the ohmic layer etching process, the amorphous silicon doped in the channel between the source and the drain can be removed, and the photoresist component during the ohmic layer etching. It is possible to prevent the contamination of the channel region by the.
따라서, 박막트랜지스터 구동시 종래보다 작은 누설전류값을 갖는 박막트랜지스터 액정표시장치를 제조할 수 있다.Accordingly, a thin film transistor liquid crystal display device having a smaller leakage current value than the conventional one when driving the thin film transistor can be manufactured.
Claims (11)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101319332B1 (en) * | 2007-03-22 | 2013-10-16 | 엘지디스플레이 주식회사 | Manufacturing Method of Thin Film Transistor array substrate |
| US20160380010A1 (en) * | 2015-03-02 | 2016-12-29 | Boe Technology Group Co., Ltd. | Fabrication method of pixel structure |
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| JPH04324833A (en) * | 1991-04-25 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of liquid crystal display device |
| KR19980014192A (en) * | 1996-08-08 | 1998-05-25 | 김광호 | Tapered texture |
| KR19980041518A (en) * | 1996-11-30 | 1998-08-17 | 김광호 | Gate etching method of amorphous silicon LCD |
| JP2000155335A (en) * | 1998-11-20 | 2000-06-06 | Advanced Display Inc | Manufacture of liquid crystal display device |
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| JPH04324833A (en) * | 1991-04-25 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of liquid crystal display device |
| KR19980014192A (en) * | 1996-08-08 | 1998-05-25 | 김광호 | Tapered texture |
| KR19980041518A (en) * | 1996-11-30 | 1998-08-17 | 김광호 | Gate etching method of amorphous silicon LCD |
| JP2000155335A (en) * | 1998-11-20 | 2000-06-06 | Advanced Display Inc | Manufacture of liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101319332B1 (en) * | 2007-03-22 | 2013-10-16 | 엘지디스플레이 주식회사 | Manufacturing Method of Thin Film Transistor array substrate |
| US20160380010A1 (en) * | 2015-03-02 | 2016-12-29 | Boe Technology Group Co., Ltd. | Fabrication method of pixel structure |
| US9818774B2 (en) * | 2015-03-02 | 2017-11-14 | Boe Technology Group Co., Ltd. | Fabrication method of pixel structure |
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