KR100309138B1 - Method for forming space of semiconductor device - Google Patents
Method for forming space of semiconductor device Download PDFInfo
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- KR100309138B1 KR100309138B1 KR1019950047318A KR19950047318A KR100309138B1 KR 100309138 B1 KR100309138 B1 KR 100309138B1 KR 1019950047318 A KR1019950047318 A KR 1019950047318A KR 19950047318 A KR19950047318 A KR 19950047318A KR 100309138 B1 KR100309138 B1 KR 100309138B1
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- Prior art keywords
- forming
- spacer
- oxide film
- silicon substrate
- gate electrode
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 반도체 소자의 스페이서 형성방법에 관한 것으로, 특히 산화막 스페이서 형성시 오버컷 또는 언더컷을 방지할 수 있도록 한 반도체소자의 스페이서 형성방법에 관한 것이다.The present invention relates to a method of forming a spacer of a semiconductor device, and more particularly, to a method of forming a spacer of a semiconductor device to prevent overcut or undercut when forming an oxide film spacer.
일반적으로 반도체 소자는 고집적화에 따라 열전자효과 및 쇼트채널 효과등의 영향을 최소화하기 위하여 게이트전극 하부에 LDD영역을 형성시켜 주는데, 상기 LDD영역은 스페이서를 이용하여 형성하게 된다. 그러면 종래 LDD영역을 형성하기 위한 반도체 소자의 스페이서 형성방법을 첨부도면 1A 내지 1E 도를 참조하여 설명하면 다음과 같다.In general, a semiconductor device forms an LDD region under a gate electrode in order to minimize the effects of thermoelectric and short channel effects due to high integration, and the LDD region is formed using a spacer. A method of forming a spacer of a semiconductor device for forming a conventional LDD region will now be described with reference to the accompanying drawings 1A to 1E.
제 1A 내지 1E 도는 종래 반도체 소자의 스페이서 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of a device for explaining a method of forming a spacer of a conventional semiconductor device.
제 1A 도는 필드산화막(2)이 형성된 상기 실리콘기판(1)상에 게이트 산화막(3), 폴리실리콘층(4) 및 실리사이드층(5)을 순차적으로 형성하고, 게이트 전극용 마스크(도시안됨)를 이용하여 상기 실리사이드층(5), 폴리실리콘층(4) 및 게이트산화막(3)을 순차적으로 패터닝하여 게이트전극(10)을 형성한 후 노출된 상기 실리콘기판(1)의 표면에 적합영역(8)을 형성한 상태의 단면도이다.In FIG. 1A, a gate oxide film 3, a polysilicon layer 4, and a silicide layer 5 are sequentially formed on the silicon substrate 1 on which the field oxide film 2 is formed, and a mask for a gate electrode (not shown). After forming the gate electrode 10 by sequentially patterning the silicide layer 5, the polysilicon layer 4 and the gate oxide film 3 by using a suitable region on the exposed surface of the silicon substrate 1 ( It is sectional drawing of the state which formed 8).
제 1B 도는 상기 실리콘기판(1)의 전체 상부면에 산화막(6)을 형성한 상태의 단면도이며, 제 1C 도는 상기 산화막(6)을 플라즈마 식각하여 상기 게이트전극(10)의 양측벽에 산화막 스페이서(6A)를 형성한 후 상기 산화막 스페이서(6A)를 이용하여 노출된 상기 실리콘기판(1)의 표면에 웰영역 형성공정을 실시하므로써 LDD영역(8A) 및 웰영역(9A)을 형성 한 상태의 단면도이다.FIG. 1B is a cross-sectional view of the oxide film 6 formed on the entire upper surface of the silicon substrate 1, and FIG. 1C is an oxide spacer on both sidewalls of the gate electrode 10 by plasma etching the oxide film 6. After the formation of the 6A, the well region forming process is performed on the exposed surface of the silicon substrate 1 using the oxide spacer 6A to form the LDD region 8A and the well region 9A. It is a cross section.
제 1D 도는 상기 제 1B 도에 도시한 산화막(6)막을 플라즈마 식각하여 상기 게이트전극(10)의 양측벽에 산화막 스페이서(6B)를 형성한 후 웰영역 형성공정을 실시하므로써 LDD영역(8B) 및 웰영역(99)을 형성한 상태의 단먼도이다. 그러나 상기 산화막 스페이서(6B) 형성시 상기 산화막(6)의 오버식각(Over Etch)으로 인하여 상기 LDD영역(8B)은 크기가 감소한 상태이다.In FIG. 1D, the oxide film 6 shown in FIG. 1B is plasma-etched to form oxide spacers 6B on both side walls of the gate electrode 10, and then the well region forming process is performed. It is a short diagram in the state in which the well region 99 is formed. However, when the oxide spacer 6B is formed, the LDD region 8B is reduced in size due to over etching of the oxide layer 6.
제 1E 도는 상기 제 1B 도에 도시한 산화막(6)막을 플라즈마 식각하여 상기 게이트전극(10)의 양측벽에 산화막 스페이서(6C)를 형성 한 후 웰영역 형성공정을 실시하므로써 LDD영역(8C) 및 웰영역(9C)을 형성한 상태의 단면도이다. 그러나 상기 산화막 스페이서(6C) 형성시 상기 산화막(6)의 언더식각(Under Etch)으로 인하여 상기 LDD영역(8C)은 크기가 증가한 상태이다.In FIG. 1E, the oxide film 6 shown in FIG. 1B is plasma-etched to form oxide spacers 6C on both sidewalls of the gate electrode 10, and then the well region forming process is performed. It is sectional drawing of the state in which the well region 9C was formed. However, when the oxide spacer 6C is formed, the LDD region 8C is increased in size due to under etching of the oxide layer 6.
그러므로 상기 산화막 스페이서 형성시 상기 산화막(6)이 오버식각되어 상기 LDD영역(8B)이 감소하거나, 혹은 언더식각되어 상기 LDD영역(8c)이 증가하게 되면 소자의 특성이 악화되어 소자의 수율이 저하된다는 문제점이 있다.Therefore, when the oxide film 6 is over-etched when the oxide film spacer is formed and the LDD region 8B is reduced or under-etched and the LDD region 8c is increased, the device characteristics are deteriorated and the yield of the device is lowered. There is a problem.
따라서 본 발명은 반도체 소자의 LDD영역의 크기를 규정하는 스페이서 형성시 감광막을 이용하여 오버식각 및 언더식각을 방지하므로써 상기한 단점을 해소할 수 있도록 한 반도체 소자의 스페이서 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a spacer of a semiconductor device, which can solve the above disadvantages by preventing over-etching and under-etching by using a photosensitive film when forming a spacer defining a size of an LDD region of a semiconductor device. have.
상기한 목적을 달성하기 위한 본 발명은 필드산화막이 형성된 상기 실리콘기판상에 게이트산화막, 폴리실리콘층 및 실리사이드층을 순차적으로 형성한 후 게이트 전극용 마스크를 이용한 상기 실리사이드층, 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하여 게이트전극을 형성한 후 노출된 상기 실리콘기판의 표면에 접합영역을 형성하는 단계와, 상기 단계로부터 상기 실리콘기판상의 전체 상부면에 감광막을 도포한 후 상기 게이트전극 및 실리콘기판의 LDD영역이 노출되도록 상기 감광막을 패터닝하고, 그 위에 산화막을 형성하는 단계와, 상기 단계로부터 상기감광막이 노출되는 시점까지 상기 산화막을 습식식각하여 산화막 스페이서를 형성하는 단계와, 상기 단계로부터 노출된 상기 감광막을 제거하고, 세정공정을 실시한 후 웰영역 형성공정을 실시하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention sequentially forms a gate oxide film, a polysilicon layer, and a silicide layer on the silicon substrate on which the field oxide film is formed, and then uses the gate electrode mask to form the silicide layer, polysilicon layer, and gate oxide film. Sequentially forming a gate electrode, and then forming a junction region on the exposed surface of the silicon substrate; and applying a photoresist to the entire upper surface of the silicon substrate from the step, and then forming the gate electrode and the silicon substrate. Patterning the photoresist such that an LDD region is exposed, forming an oxide film thereon, wet etching the oxide film from the step to a time point at which the photoresist is exposed, and forming an oxide spacer; Well region type after removal of photoresist film and cleaning process That comprising the step of performing the process features.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 2A 내지 2D 도는 본 발명에 따른 반도체 소자의 스페이서 형성방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for explaining a method of forming a spacer of a semiconductor device according to the present invention.
제 24 도는 필드산화막(12)이 형성된 상기 실리콘기판(11)상에 게이트산화막(13), 폴리실리콘층(14) 및 실리사이드층(15)을 순차적으로 형성한 후 게이트 전극용 마스크(도시 안됨)를 이용한 상기 실리사이드층(15), 폴리실리콘층(14) 및 게이트산화막(13)을 순차적으로 패터닝하여 게이트전극(20)을 형성한 후 노출된 상기 실리콘기판(11)의 표면에 접합영역(18)을 형성한 상태의 단면도이다.24 shows a gate oxide film 13, a polysilicon layer 14, and a silicide layer 15 sequentially formed on the silicon substrate 11 on which the field oxide film 12 is formed (not shown). After forming the gate electrode 20 by sequentially patterning the silicide layer 15, the polysilicon layer 14, and the gate oxide layer 13 using the junction region 18 on the exposed surface of the silicon substrate 11. It is sectional drawing of the state formed.
제 2B 도는 상기 실리콘기판(11)상의 전체 상부면에 감광막(17)을 도포한 후 상기 게이트전극(20) 및 실리콘기판(11)의 LDD영역이 노출되도록 상기 감광막(17)을 패터닝하고, 그 위에 산화막(16)을 형성한 상태의 단면도이다. 상기 산화막(16)은 100 내지 150℃의 온도에서 1800내지 2200Å의 두께로 형성한다.In FIG. 2B, after the photoresist film 17 is applied to the entire upper surface of the silicon substrate 11, the photoresist film 17 is patterned to expose the LDD regions of the gate electrode 20 and the silicon substrate 11. It is sectional drawing of the state which formed the oxide film 16 on. The oxide film 16 is formed to a thickness of 1800 to 2200 kPa at a temperature of 100 to 150 ℃.
제 2C도는 상기 감광막(17)이 노출되는 시점까지 상기 산화막(16)을 습식식각하면 산화막 스페이서(16A)를 형성 한 상태의 단면도이다. 상기 습식식각은 50 : 1의 BOE(Buffered Oxide Etchant)용액에 12 내지 18분 정도 담근다.FIG. 2C is a cross-sectional view of the oxide spacer 16A when the oxide film 16 is wet-etched until the photosensitive film 17 is exposed. The wet etching is soaked for 12 to 18 minutes in a 50: 1 BOE (Buffered Oxide Etchant) solution.
제 2D 도는 노출된 상기 감광막(17)을 제거하고, 세정공정을 실시한 후 웰영역 형성공정을 실시하여 LDD영역(18A) 및 웰영역(18B)을 형성한 상태의 단면도이다. 그러므로 본 실시예의 방법에 의하면 상기 습식식각공정시 오버식각 혹은 언더식각이 되더라도 LDD영역(18A)의 크기는 변함이 없다.FIG. 2D is a cross-sectional view of the LDD region 18A and the well region 18B formed by removing the exposed photoresist film 17, performing a cleaning process, and then forming a well region. Therefore, according to the method of the present exemplary embodiment, the size of the LDD region 18A does not change even when over etching or under etching occurs in the wet etching process.
상기한 본 실시예는 상술에 한정되는 것은 아니며 필요에 따라서 변형할 수 있음은 물론이다. 즉 본 실시예에서는 LDD영역(18A)을 규정하는 산화막 스페이서(16A)의 형성시 게이트전극(20)의 위면을 상기 산화막 스페이서(16A)가 덮도록 하고 있으나 상기 감광막(17) 또는 습식식각의 시간에 따라서 그 두께를 조절할 수 있다.The present embodiment described above is not limited to the above description and can be modified as necessary. In other words, in the present embodiment, the oxide spacer 16A covers the upper surface of the gate electrode 20 when the oxide spacer 16A defining the LDD region 18A is formed. Depending on the thickness can be adjusted.
상술한 바와 같이 본 발명에 의하면 반도체 소자자 LDD영역의 크기를 규정하는 스페이서 형성시 감광막을 이용하여 오버식각 및 언더식각을 방지하므로 소자의 수율을 향상시킬 수 있는 탁원한 효과가 있다.As described above, according to the present invention, since overetching and underetching are prevented by using a photosensitive film when forming a spacer defining the size of the semiconductor device element LDD region, the yield of the device can be improved.
제 1A 내지 1E 도는 종래 반도체 소자의 스페이서 형성 방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of forming a spacer of a conventional semiconductor device.
제 2A 내지 2D 도는 본 발명에 따른 반도체 소자의 산화막 스페이서 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming an oxide film spacer of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호설명 ** Explanation of Signs of Major Parts of Drawings *
1 및 11 : 실리콘기판 2 및 12 : 필드산화막1 and 11: silicon substrate 2 and 12: field oxide film
3 및 13 : 게이트산화막 4 및 14 : 폴리실리콘층3 and 13: gate oxide film 4 and 14: polysilicon layer
5 및 15 : 실리사이드층 6 및 16A : 산화막5 and 15: silicide layers 6 and 16A: oxide film
6A,6B,6C 및 16A : 스페이서 7 : 마스크6A, 6B, 6C and 16A: Spacer 7: Mask
10 및 20 : 게이트전극10 and 20: gate electrode
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950047318A KR100309138B1 (en) | 1995-12-07 | 1995-12-07 | Method for forming space of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950047318A KR100309138B1 (en) | 1995-12-07 | 1995-12-07 | Method for forming space of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053014A KR970053014A (en) | 1997-07-29 |
| KR100309138B1 true KR100309138B1 (en) | 2003-07-12 |
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|---|---|---|---|
| KR1019950047318A KR100309138B1 (en) | 1995-12-07 | 1995-12-07 | Method for forming space of semiconductor device |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287072A (en) * | 1987-05-19 | 1988-11-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04115537A (en) * | 1990-09-05 | 1992-04-16 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0714848A (en) * | 1993-06-17 | 1995-01-17 | Kawasaki Steel Corp | Manufacture of mos transistor |
| KR950021201A (en) * | 1993-12-28 | 1995-07-26 | 김주용 | Spacer Formation Method of Semiconductor Device |
-
1995
- 1995-12-07 KR KR1019950047318A patent/KR100309138B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287072A (en) * | 1987-05-19 | 1988-11-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04115537A (en) * | 1990-09-05 | 1992-04-16 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0714848A (en) * | 1993-06-17 | 1995-01-17 | Kawasaki Steel Corp | Manufacture of mos transistor |
| KR950021201A (en) * | 1993-12-28 | 1995-07-26 | 김주용 | Spacer Formation Method of Semiconductor Device |
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| Publication number | Publication date |
|---|---|
| KR970053014A (en) | 1997-07-29 |
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