KR970053014A - Spacer Formation Method of Semiconductor Device - Google Patents

Spacer Formation Method of Semiconductor Device Download PDF

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Publication number
KR970053014A
KR970053014A KR1019950047318A KR19950047318A KR970053014A KR 970053014 A KR970053014 A KR 970053014A KR 1019950047318 A KR1019950047318 A KR 1019950047318A KR 19950047318 A KR19950047318 A KR 19950047318A KR 970053014 A KR970053014 A KR 970053014A
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KR
South Korea
Prior art keywords
forming
oxide film
semiconductor device
spacer
silicon substrate
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Application number
KR1019950047318A
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Korean (ko)
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KR100309138B1 (en
Inventor
조승건
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김주용
현대전자산업 주식회사
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Priority to KR1019950047318A priority Critical patent/KR100309138B1/en
Publication of KR970053014A publication Critical patent/KR970053014A/en
Application granted granted Critical
Publication of KR100309138B1 publication Critical patent/KR100309138B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 스페이서 형성방법을 제공하는 것으로, 반도체 소자의 LDD영역의 크기를 규정하는 스페이서 형성시 감광막을 이용하여 오버식각 및 언더식각을 방지하므로 소자의 수율을 향상시킬 수 있는 효과가 있다.The present invention provides a method of forming a spacer of a semiconductor device, and prevents over-etching and under-etching by using a photosensitive film when forming a spacer that defines the size of the LDD region of the semiconductor device, thereby improving the yield of the device. .

Description

반도체 소자의 스페이서 형성방법Spacer Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A 내지 2D도는 본 발명에 따른 반도체 소자의 산화막 스페이서 형성방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method of forming an oxide film spacer of a semiconductor device according to the present invention.

Claims (3)

반도체 소자의 스페이서 형성방법에 있어서, 필드산화막이 형성된 상기 실리콘기판상에 게이트산화막, 폴리실리콘층 및 실리사이드층을 순차적으로 형성한 후 게이트 전극용 마스크를 이용한 상기 실리사이드층, 폴리실리콘층 및 게이트산화막을 순차적으로 패터닝하여 게이트전극을 형성한 후 노출된 상기 실리콘기판의 표면에 접합영역을 형성하는 단계와, 상기 단계로부터 상기 실리콘기판상의 전체 상부면에 감광막을 도포한 후 상기 게이트전극 및 실리콘기판의 LDD영역이 노출되도록 상기 감광막을 패터닝하여, 그 위에 산화막을 형성하는 단계와, 상기 단꼐로부터 상기 감광막이 노출되는 시점까지 상기 산화막을 습식식각하여 산화막 스페이서를 형성하는 단계와, 상기 단계로부터 노출된 상기 감광막을 제거하고, 세정공정을 실시한 후 웰영역 형성공정을 실시하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 스페이서 형성방법.In the method for forming a spacer of a semiconductor device, a gate oxide film, a polysilicon layer, and a silicide layer are sequentially formed on the silicon substrate on which the field oxide film is formed, and then the silicide layer, the polysilicon layer, and the gate oxide film are formed using a gate electrode mask. Patterning sequentially to form a gate electrode, and then forming a junction region on the exposed surface of the silicon substrate; and applying a photosensitive film to the entire upper surface of the silicon substrate from the step, and then LDD of the gate electrode and the silicon substrate. Patterning the photoresist film so as to expose an area, forming an oxide film thereon, wet etching the oxide film from the step to a time point at which the photoresist film is exposed, and forming an oxide spacer, wherein the photoresist film exposed from the step is exposed. Was removed, and after the cleaning process, Welyoung The spacer forming a semiconductor device characterized in that comprising a step of conducting formation process. 제1항에 있어서, 상기 산화막은 100 내지 150℃의 온도에서 1800 내지 2200Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 스페이서 형성방법.The method of claim 1, wherein the oxide film is formed to a thickness of 1800 to 2200 Å at a temperature of 100 to 150 ° C. 7. 제1항에 있어서, 상기 습식식각은 50:1의 BOE용액에서 12 내지 18분 동안 실시하는 것을 특징으로 하는 반도체 소자의 스페이서 형성방법.The method of claim 1, wherein the wet etching is performed for 12 to 18 minutes in a 50: 1 BOE solution. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950047318A 1995-12-07 1995-12-07 Method for forming space of semiconductor device KR100309138B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950047318A KR100309138B1 (en) 1995-12-07 1995-12-07 Method for forming space of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950047318A KR100309138B1 (en) 1995-12-07 1995-12-07 Method for forming space of semiconductor device

Publications (2)

Publication Number Publication Date
KR970053014A true KR970053014A (en) 1997-07-29
KR100309138B1 KR100309138B1 (en) 2003-07-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950047318A KR100309138B1 (en) 1995-12-07 1995-12-07 Method for forming space of semiconductor device

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Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63287072A (en) * 1987-05-19 1988-11-24 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH04115537A (en) * 1990-09-05 1992-04-16 Oki Electric Ind Co Ltd Manufacture of semiconductor device
JPH0714848A (en) * 1993-06-17 1995-01-17 Kawasaki Steel Corp Manufacture of mos transistor
KR950021201A (en) * 1993-12-28 1995-07-26 김주용 Spacer Formation Method of Semiconductor Device

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Publication number Publication date
KR100309138B1 (en) 2003-07-12

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