KR970023727A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
KR970023727A
KR970023727A KR1019950036825A KR19950036825A KR970023727A KR 970023727 A KR970023727 A KR 970023727A KR 1019950036825 A KR1019950036825 A KR 1019950036825A KR 19950036825 A KR19950036825 A KR 19950036825A KR 970023727 A KR970023727 A KR 970023727A
Authority
KR
South Korea
Prior art keywords
gate electrode
insulating film
forming
semiconductor device
manufacturing
Prior art date
Application number
KR1019950036825A
Other languages
Korean (ko)
Other versions
KR0166845B1 (en
Inventor
성기천
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950036825A priority Critical patent/KR0166845B1/en
Publication of KR970023727A publication Critical patent/KR970023727A/en
Application granted granted Critical
Publication of KR0166845B1 publication Critical patent/KR0166845B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로, ILD 열처리공정 및 식각공정을 단순화하여 TAT를 단축시키는 적당한 반도체 소자의 제조방법을 제공하기 위함이다.The present invention relates to a method for manufacturing a semiconductor device, and to provide a method for manufacturing a suitable semiconductor device to shorten the TAT by simplifying the ILD heat treatment process and etching process.

이를 위한 본 발명의 반도체 소자의 제조방법은 반도체 기판상에 활성영역과 필드영역을 정의하고 상기 활성영역상의 소정부분에 게이트전극을 형성하는 공정 상기 게이트전극을 포함한 반도체기판 전면에 절연막을 형성하는 공정, 상기 절연막 상부에 제 1 감광막을 도포하고 활성 마스크를 통한 노광 및 현상공정으로 게이트전극 양측의 반도체 기판이 노출되도록 절연막을 선택적으로 제거하는 공정, 상기 결과물에 접합형성용 이온주입을 실시하는 공정, 상기 절연물에 열처리공정을 실시하여 게이트 물질에 불순물이 도핑되고 셀프콘택을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The semiconductor device manufacturing method of the present invention for this purpose is to define an active region and a field region on the semiconductor substrate and to form a gate electrode on a predetermined portion on the active region forming a insulating film on the entire surface of the semiconductor substrate including the gate electrode Applying a first photoresist film over the insulating film and selectively removing the insulating film to expose semiconductor substrates on both sides of the gate electrode through an exposure and development process through an active mask; and performing ion implantation for forming a junction on the resultant. And performing a heat treatment process on the insulator to form a self contact and doping impurities into the gate material.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2 도 (a)∼(c)는 본 발명의 반도체소자 제조방법에 따른 공정단면도.2 (a) to 2 (c) are process cross-sectional views of the semiconductor device manufacturing method of the present invention.

Claims (4)

반도체 기판상에 활성영역과 필드영역을 정의하고 상기 활성영역상의 소정부분에 게이트전극을 형성하는 공정, 상기 게이트전극을 포함한 반도체 기판 전면에 절연막을 형성하는 공정, 상기 절연막 상부에 제 1 감광막을 도포하고 활성 마스크를 통한 노광 및 현상공정으로 게이트전극 양측의 반도체 기판이 노출되도록 절연막을 선택적으로 제거하는 공정 상기 결과물에 접합형성용 이온주입을 실시하는 공정, 상기 절연물에 열처리공정을 실시하여 게이트 물질에 불순물이 도핑되고 셀프콘택을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조방법.Defining an active region and a field region on a semiconductor substrate, forming a gate electrode on a predetermined portion of the active region, forming an insulating film on the entire surface of the semiconductor substrate including the gate electrode, and applying a first photoresist film on the insulating film. And selectively removing the insulating film so that the semiconductor substrates on both sides of the gate electrode are exposed through an exposure and development process through an active mask. A process of performing ion implantation for forming a junction on the resultant, and performing a heat treatment process on the insulator. And impurity doping and forming a self contact. 제 1 항에 있어서, 상기 게이트전극은 불순물이 도핑되지 않은 폴리실리콘을 저압증착법(LPCVD)에 의해 형성됨을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the gate electrode is formed of low pressure doping polysilicon by LPCVD. 제 1 항에 있어서, 상기 게이트전극 형성후 ILD층으로는 PSG를 사용함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein PSG is used as an ILD layer after the gate electrode is formed. 제 1 항에 있어서, 상기 PSG는 15wt% P농도 이상의 박막을 기압증착법(APCVD)에 의해 증착함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the PSG deposits a thin film having a concentration of 15 wt% P or more by pressure vapor deposition (APCVD). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950036825A 1995-10-24 1995-10-24 Manufacturing method of semiconductor device KR0166845B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950036825A KR0166845B1 (en) 1995-10-24 1995-10-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950036825A KR0166845B1 (en) 1995-10-24 1995-10-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR970023727A true KR970023727A (en) 1997-05-30
KR0166845B1 KR0166845B1 (en) 1999-02-01

Family

ID=19431082

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950036825A KR0166845B1 (en) 1995-10-24 1995-10-24 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0166845B1 (en)

Also Published As

Publication number Publication date
KR0166845B1 (en) 1999-02-01

Similar Documents

Publication Publication Date Title
KR960005896A (en) Method of manufacturing thin film transistor
KR960024604A (en) Dual channel thin film transistor and its manufacturing method
KR970018187A (en) Semiconductor device manufacturing method
KR970054431A (en) MOS transistor and manufacturing method thereof
KR970023727A (en) Manufacturing method of semiconductor device
KR960002691A (en) Semiconductor device and manufacturing method
KR950004584A (en) Manufacturing method of polycrystalline silicon thin film transistor with offset structure
KR970054379A (en) Manufacturing method of LDD MOS device
KR950021201A (en) Spacer Formation Method of Semiconductor Device
KR920015619A (en) Manufacturing method of elevated source / drain MOS FET
KR950034828A (en) Manufacturing method and gate structure of MOS transistor using copper electrode
KR970054349A (en) Method for manufacturing symmetric bipolar transistor
KR910013511A (en) Device isolation oxide film formation method of semiconductor device
KR960043051A (en) Method of manufacturing thin film transistor
KR910003786A (en) Gate electrode formation method
KR950024331A (en) Semiconductor device manufacturing method
KR960036142A (en) Thin film transistor structure and manufacturing method
KR970004037A (en) Transistor manufacturing method of semiconductor device
KR970053014A (en) Spacer Formation Method of Semiconductor Device
KR970053068A (en) Manufacturing method of semiconductor device
KR930015053A (en) Manufacturing method of high speed dipole transistor device
KR940010387A (en) Semiconductor device manufacturing method
KR970054258A (en) Method of manufacturing thin film transistor
KR960005782A (en) Contact hole formation method of semiconductor device
KR950025931A (en) Gate electrode formation method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120823

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20130821

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20140820

Year of fee payment: 17

EXPY Expiration of term