KR960036142A - Thin film transistor structure and manufacturing method - Google Patents

Thin film transistor structure and manufacturing method Download PDF

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Publication number
KR960036142A
KR960036142A KR1019950004614A KR19950004614A KR960036142A KR 960036142 A KR960036142 A KR 960036142A KR 1019950004614 A KR1019950004614 A KR 1019950004614A KR 19950004614 A KR19950004614 A KR 19950004614A KR 960036142 A KR960036142 A KR 960036142A
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South Korea
Prior art keywords
semiconductor layer
gate electrode
dummy pattern
forming
substrate
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KR1019950004614A
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Korean (ko)
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KR0161892B1 (en
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박준영
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문정환
엘지반도체 주식회사
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Priority to KR1019950004614A priority Critical patent/KR0161892B1/en
Publication of KR960036142A publication Critical patent/KR960036142A/en
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Publication of KR0161892B1 publication Critical patent/KR0161892B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 더미패던과 에치백 방법으로 자동 정렬된 옵셋영역을 형성하는데 적당하도록 한 박막트랜지스터 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a thin film transistor structure and a manufacturing method suitable for forming an offset region automatically aligned by a dummy paddle and an etch back method.

상기 목적을 달성하기 위한 박막트랜지스터 구조는 기판위에 형성된 게이트전극과 더미패턴 상기 게이트전극과 상기 데미패턴 그리고 상기 기판위에 형성된 반도체층, 상기 게이트전극과 상기 더미패턴사이의 상기 반도체층위에 형성된 절연막, 상기 게이트전극과 상기 더미패턴영역을 제외한 상기 반도체층에 형성된 불순물영역을 포함하여 구성되어지고, 본 발명의 박막 트랜지스터의 제조방법은 기판상에 게이트전극과 더미패턴을 형성하는 공정과, 상기 게이트전극과 더미패턴 그리고 상기 기판위에 제1절연막과 반도체층을 차례로 형성하는 공정과, 상기 게이트전극과 더미패턴사이의 상기 반도체층위에 제2절연막을 형성하는 공정과, 채널영역과 상기 제2절연막이 형성된 영역을 제외한 상기 반도체층이 불순물영역을 형성하는 공정을 포함하여 이루어진다.A thin film transistor structure for achieving the above object includes a gate electrode and a dummy pattern formed on a substrate, the gate electrode and the demi-pattern and a semiconductor layer formed on the substrate, an insulating film formed on the semiconductor layer between the gate electrode and the dummy pattern, And an impurity region formed in the semiconductor layer except for the dummy electrode and the dummy pattern region. The method of manufacturing a thin film transistor according to the present invention includes the steps of forming a gate electrode and a dummy pattern on a substrate; Forming a dummy pattern and a first insulating film and a semiconductor layer on the substrate in turn; forming a second insulating film on the semiconductor layer between the gate electrode and the dummy pattern; and forming a channel region and a second insulating film. Except for the step of forming an impurity region in the semiconductor layer Achieved.

Description

박막트랜지스터 구조 및 제조방법Thin film transistor structure and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 2도는 본 발명의 박막트랜지스터 공정단면도.2 is a cross-sectional view of a thin film transistor process of the present invention.

Claims (3)

기판위에 형성된 게이트전극과 더미패턴, 상기 게이트전극과 상기 더미패턴 그리고 상기 기판위에 형성된 반도체층, 상기 게이트전극과 상기 더미패턴사이의 상기 반도체층위에 형성된 절연막, 상기 게이트전극과 상기 더미패턴영역을 제외한 상기 반도체층에 형성된 불순물영역을 포함하여 이루어지는 것을 특징으로 하는 박막트랜지스터 구조Except for the gate electrode and the dummy pattern formed on the substrate, the semiconductor layer formed on the gate electrode and the dummy pattern and the substrate, the insulating film formed on the semiconductor layer between the gate electrode and the dummy pattern, except for the gate electrode and the dummy pattern region A thin film transistor structure comprising an impurity region formed in the semiconductor layer 기판상에 게이트전극과 더미패턴을 형성하는 공정과, 상기 게이트전극, 더미패턴 그리고 상기 기판위에 제 1절연막과 반도체층을 차례로 형성하는 공정과, 상기 게이트전극과 더미패턴사이의 상기 반도체층위에 제 2절연막을 형성하는 공정과, 채널영역과 상기 제 2절연막이 형성된 영역을 제외한 상기 반도체층이 불순물영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 박막트랜지스터 제조방법.Forming a gate electrode and a dummy pattern on a substrate; and sequentially forming a first insulating film and a semiconductor layer on the gate electrode, the dummy pattern, and the substrate; and forming a gate electrode and a dummy pattern on the semiconductor layer between the gate electrode and the dummy pattern. And a step of forming an impurity region in the semiconductor layer except for a channel region and a region in which the second insulating layer is formed. 2. 제 2항에 있어서, 상기 반도체층에 불순물을 형성하는 공정과, 상기 게이트전극과 중첩된 영역과 상기 더미패턴위에 마스크를 형성하고, 상기 반도체층에 불순물 이온을 주입하는 것을 특징으로 하는 박막트랜지스터 제조방법.The thin film transistor manufacturing method of claim 2, further comprising forming an impurity in the semiconductor layer, forming a mask on the region overlapping the gate electrode and the dummy pattern, and implanting impurity ions into the semiconductor layer. Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950004614A 1995-03-07 1995-03-07 Thin film transistor KR0161892B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950004614A KR0161892B1 (en) 1995-03-07 1995-03-07 Thin film transistor

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Application Number Priority Date Filing Date Title
KR1019950004614A KR0161892B1 (en) 1995-03-07 1995-03-07 Thin film transistor

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KR960036142A true KR960036142A (en) 1996-10-28
KR0161892B1 KR0161892B1 (en) 1998-12-01

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KR1019950004614A KR0161892B1 (en) 1995-03-07 1995-03-07 Thin film transistor

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KR20090114919A (en) * 2008-04-30 2009-11-04 경희대학교 산학협력단 Manufacturing method of the sameInverse staggered poly-Si TFT with centet off-set

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