KR960019603A - Manufacturing Method of Thin Film Transistor - Google Patents

Manufacturing Method of Thin Film Transistor Download PDF

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Publication number
KR960019603A
KR960019603A KR1019940031515A KR19940031515A KR960019603A KR 960019603 A KR960019603 A KR 960019603A KR 1019940031515 A KR1019940031515 A KR 1019940031515A KR 19940031515 A KR19940031515 A KR 19940031515A KR 960019603 A KR960019603 A KR 960019603A
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KR
South Korea
Prior art keywords
semiconductor layer
gate electrode
forming
insulating film
manufacturing
Prior art date
Application number
KR1019940031515A
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Korean (ko)
Other versions
KR0156116B1 (en
Inventor
한상범
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940031515A priority Critical patent/KR0156116B1/en
Publication of KR960019603A publication Critical patent/KR960019603A/en
Application granted granted Critical
Publication of KR0156116B1 publication Critical patent/KR0156116B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Abstract

본 발명은 박막 트랜지스터 제조방법에 관한 것으로, 특히 고집적 SRAM메모리 소자에 적당하도록 한 P-MOS 박막 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a P-MOS thin film transistor adapted to be suitable for a highly integrated SRAM memory device.

이와 같은 본 발명의 박막 트랜지스터의 제조방법은 기판상에 절연막과 제1반도체층을 차례로 증착하는 공정과, 상기 제1반도체층을 패터닝하여 제1게이트전극을 형성하는 공정과, 패터닝된 1차 게이트전극과 노출된 절연막상에 1차 게이트 절연막과 제2반도체층을 차례로 증착하는 공정과, 상기 제2반도체층을 에치백하여 상기 제1게이트전극 측면에 활성 반도체층을 형성하는 공정과, 전면에 2차 게이트 절연막과 제3반도체층을 형성하는 공정과, 활성 반도체층의 양측이 노출되고 활성 반도체층을 중심으로 제1게이트전극과 대향되도록 상기 제3반도체층을 선택적으로 식각하여 제2게이트전극을 형성하는 공정과, 상기 제2게이트전극을 마이크로 이용하여 활성 반도체층에 불순물 이온주입하여 소오스/드레인영역을 형성하는 공정을 포함하여 이루어진 것이다.Such a method of manufacturing a thin film transistor according to the present invention includes the steps of depositing an insulating film and a first semiconductor layer on a substrate, forming a first gate electrode by patterning the first semiconductor layer, and patterning a primary gate Depositing a first gate insulating film and a second semiconductor layer in order on an electrode and the exposed insulating film; and etching back the second semiconductor layer to form an active semiconductor layer on the side of the first gate electrode; Forming a secondary gate insulating film and a third semiconductor layer; and selectively etching the third semiconductor layer so that both sides of the active semiconductor layer are exposed and facing the first gate electrode with respect to the active semiconductor layer. Forming a source / drain region by implanting impurity ions into the active semiconductor layer using the second gate electrode as a micro; It is lost.

Description

박막 트랜지스터의 제조방법Manufacturing Method of Thin Film Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 박막 트랜지스터의 공정단면도.2 is a process cross-sectional view of the thin film transistor of the present invention.

Claims (1)

기판상에 절연막과 제1반도체층을 차례로 증착하는 공정과, 상기 제1반도체층을 패터닝하여 제1게이트전극을 형성하는 공정과, 패터닝된 1차 게이트전극과 노출된 절연막상에 1차 게이트 절연막과 제2반도체층을 차례로 증착하는 공정과, 상기 제2반도체층을 에치백하여 상기 제1게이트전극 측면에 활성 반도체층을 형성하는 공정과, 전면에 2차 게이트 절연막과 제3반도체층을 형성하는 공정과, 활성 반도체층의 양측이 노출되고 활성 반도체층을 중심으로 제1게이트전극과 대향되도록 상기 제3반도체층을 선택적으로 식각하여 제2게이트전극을 형성하는 공정과, 상기 제2게이트전극을 마이크로 이용하여 활성 반도체층에 불순물 이온주입하여 소오스/드레인영역을 형성하는 공정을 포함하여 이루어짐을 특징으로 하는 박막 트랜지스터의 제조방법.Depositing an insulating film and a first semiconductor layer on a substrate in sequence, forming a first gate electrode by patterning the first semiconductor layer, and forming a first gate electrode on the patterned primary gate electrode and the exposed insulating film And depositing a second semiconductor layer in sequence, forming an active semiconductor layer on the side of the first gate electrode by etching back the second semiconductor layer, and forming a secondary gate insulating layer and a third semiconductor layer on the entire surface. Forming a second gate electrode by selectively etching the third semiconductor layer so that both sides of the active semiconductor layer are exposed and opposed to the first gate electrode centered on the active semiconductor layer, and the second gate electrode And forming a source / drain region by implanting impurity ions into the active semiconductor layer using a micro. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940031515A 1994-11-28 1994-11-28 Method of fabricating thin film transistor KR0156116B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940031515A KR0156116B1 (en) 1994-11-28 1994-11-28 Method of fabricating thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940031515A KR0156116B1 (en) 1994-11-28 1994-11-28 Method of fabricating thin film transistor

Publications (2)

Publication Number Publication Date
KR960019603A true KR960019603A (en) 1996-06-17
KR0156116B1 KR0156116B1 (en) 1998-12-01

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ID=19399257

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031515A KR0156116B1 (en) 1994-11-28 1994-11-28 Method of fabricating thin film transistor

Country Status (1)

Country Link
KR (1) KR0156116B1 (en)

Also Published As

Publication number Publication date
KR0156116B1 (en) 1998-12-01

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