KR960026225A - Contact hole formation method of semiconductor device - Google Patents

Contact hole formation method of semiconductor device Download PDF

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Publication number
KR960026225A
KR960026225A KR1019940039115A KR19940039115A KR960026225A KR 960026225 A KR960026225 A KR 960026225A KR 1019940039115 A KR1019940039115 A KR 1019940039115A KR 19940039115 A KR19940039115 A KR 19940039115A KR 960026225 A KR960026225 A KR 960026225A
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South Korea
Prior art keywords
photoresist
etching
pattern
insulating oxide
insulating
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KR1019940039115A
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Korean (ko)
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KR0162144B1 (en
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박상훈
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 반도체 소자의 콘택홀을 형성하는 방법에 관한 것으로서, 실리콘기판 또는 도전체 상부에 제1절연체 산화막을 도포하는 단계와, 금속의 패턴을 형성하는 단계와, 금속 패턴 상부에 질화막 및 제2절연산화막을 증착하는 단계와, 사진 식각 공정에 의하여 포토레지스트의 패턴을 형성하는 단계와, 상기 포토레지스트를 플로우하는 단계와, 상기 포토레지스트 패턴을 마스크로하여 제2절연산화막을 소정의 깊이만큼 식각하는 단계와, 상기 포토리지스트 패턴과 제2절연산화막을 동시에 식각하는 단계와, 플러그 이온을 주입하는 단계와, 절연막 도포 및 이방성 식각하여 스페이서를 형성하는 단계 및 상기 스페이서를 식각 마스크 하여 질화막과 제1절연산화막을 제거하여 실리콘기판을 노출시키는 단계로 이루어진다. 이와 같은 본 발명은 초미세 콘택홀 형성시 플라즈마 식각공정에 의해 실리콘기판상에 가해지는 식각 손상을 줄이면서 이와 동시에 습식식각공정을 행하지 않고서도 경사진 측면을 형성할 수 있어 반도체 소자의 제조 수율 및 신뢰도를 개선시킬 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, comprising: applying a first insulator oxide film on a silicon substrate or a conductor, forming a pattern of a metal, a nitride film and a second on the metal pattern Depositing an insulating oxide film, forming a pattern of a photoresist by a photolithography process, flowing the photoresist, and etching the second insulating oxide film by a predetermined depth using the photoresist pattern as a mask And etching the photoresist pattern and the second insulating oxide layer at the same time, implanting plug ions, applying an insulating film and etching anisotropically to form a spacer, and etching the spacer. 1, the insulating oxide film is removed to expose the silicon substrate. As described above, the present invention can reduce the etching damage applied to the silicon substrate by the plasma etching process when forming the ultra fine contact hole, and at the same time, form the inclined side surface without performing the wet etching process. It is possible to improve the reliability.

Description

반도체 소자의 콘택홀 형성 방법.Method for forming contact holes in semiconductor device.

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (가) 는 본 발명의 반도체 소자의 콘택홀을 나타낸 도, 제2도 (나) 내지 제2도 (차) 는 본 발명의 반도체 소자의 콘택홀 형성단계를 제2도 (가) 의 B-B’선을 따라 단면으로 나타낸 공정도.2 (a) is a view showing a contact hole of the semiconductor device of the present invention, Figures 2 (b) to 2 (d) shows a contact hole forming step of the semiconductor device of the present invention (a) Process diagram shown in cross section along the line B-B 'of FIG.

Claims (10)

반도체 소자의 콘택홀 형성 방법에 있어서, 실리콘기판 또는 도전체 상부에 제1절연산화막을 도포하는 단계와, 금속의 패턴을 형성하는 단계와, 금속 패턴 상부에 질화막 및 제2절연산화막을 증착하는 단계와, 사진 식각 공정에 의하여 포토레지스트의 패턴을 형성하는 단계와, 상기 포토레지스터를 플로우하는 단계와, 상기 포토레지스터를 패턴을 마스크로하여 제2절연산화막을 소정의 깊이만큼 식각하는 단계와, 상기 포토레지스트 패턴과 제2절연산화막을 동시에 식각하는 단계와, 플러그 이온을 주입하는 단계와, 절연막 도포 및 이방성 식각하여 스페이서를 형성하는 단계 및 상기 스페이서를 식각 마스크로 하여 질화막과 제1절연산화막을 제거하여 실리콘기판을 노출시키는 단계를 구비하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.A method for forming a contact hole in a semiconductor device, the method comprising: applying a first insulating oxide film over a silicon substrate or a conductor, forming a metal pattern, and depositing a nitride film and a second insulating oxide film over the metal pattern Forming a pattern of a photoresist by a photolithography process; flowing the photoresist; etching the second insulating oxide film by a predetermined depth using the photoresist as a pattern; Etching the photoresist pattern and the second insulating oxide layer at the same time, implanting plug ions, forming an spacer by applying and anisotropically etching the insulating film, and removing the nitride layer and the first insulating oxide layer using the spacer as an etching mask. And exposing the silicon substrate to form a contact hole for a semiconductor device. 제 1항에 있어서, 상기 포토레지스터 패턴을 플로우 시키기 위하여 120 내지 180℃의 조건으로 10 내지 30분간 오븐베이킹 하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the oven is baked for 10 to 30 minutes under a condition of 120 to 180 ° C. to flow the photoresist pattern. 제1항 또는 제2항에 있어서, 상기 포토레지스트 패턴을 플로우시키는 단계에서 포토레지스트의 양 측부가 0.05 내지 0.1㎛가 되도록 플로우시킴을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein both sides of the photoresist are flowed in a range of 0.05 to 0.1 μm in the step of flowing the photoresist pattern. 제3항에 있어서, 상기 포토레지스트 패턴을 콘택홀의 크기보다 0.1 내지 0.2㎛ 더 크게 형성함을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 3, wherein the photoresist pattern is formed to be 0.1 to 0.2 μm larger than the size of the contact hole. 제1항에 있어서, 산화막에 대한 포토레지스트의 식각속도의 비율이 2 내지 4가 되도록 에치백하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.2. The method of claim 1, further comprising etching back so that the ratio of the etch rate of the photoresist to the oxide film is 2-4. 제1항에 있어서, 상기 플러그 이온을 주입하는 단계에서 플러그 이온을 도전체 내부 또는 실리콘기판에 도핑된 이온 불순물과 동일한 이온 불순물인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the plug ions are implanted with the same ionic impurities as the ionic impurities doped into the conductor or the silicon substrate in the step of implanting the plug ions. 제1항에 있어서, 상기 질화막의 두께는 500 내지 1000Å인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.2. The method of claim 1, wherein the nitride film has a thickness of 500 to 1000 GPa. 제1항에 있어서, 상기 포토레지스트 패턴을 마스크로하여 제2절연산화막이 식각되는 깊이는 상기 질화막 상부에 잔존하는 제2절연산화막의 두께가 거의 동일함을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein a depth of the second insulating oxide layer etched using the photoresist pattern as a mask is about the same thickness of the second insulating oxide layer remaining on the nitride layer. . 제1항에 있어서, 상기 절연막은 1000내지 2000Å 증착하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the insulating layer is deposited at 1000 to 2000 GPa. 제1항 또는 제9항에 있어서, 상기 절연막을 이방성 식각하는 단계에서 상기 질화막을 식각 정지층으로 이용하여 상기 제2절연산화막의 측벽에 스페이서를 형성함을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.10. The method of claim 1 or 9, wherein in the anisotropic etching of the insulating layer, spacers are formed on sidewalls of the second insulating oxide layer using the nitride layer as an etch stop layer. . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940039115A 1994-12-30 1994-12-30 Formation method of contact hole in semiconductor device KR0162144B1 (en)

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KR100505442B1 (en) * 1998-10-28 2005-10-12 주식회사 하이닉스반도체 Contact hole formation method of semiconductor device
KR100710187B1 (en) * 2005-11-24 2007-04-20 동부일렉트로닉스 주식회사 Method for fabricating semiconductor device

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