KR102023126B1 - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

The present invention discloses a thin film transistor array substrate and a method of manufacturing the same. The disclosed thin film transistor array substrate includes a substrate; Gate lines and data lines cross-arranged to define pixel regions on the substrate; A switching element disposed in an intersection region of the gate line and the data line; A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And a common electrode and a common line respectively disposed on the pixel electrode and the data line, wherein the data line is covered by an organic insulating pattern, the data line and the organic insulating film are covered by a protective film, and the protective film. A common line is formed on the phase.

Description

Thin Film Transistor Array Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device.

In general, a liquid crystal display (LCD) displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field. In the liquid crystal display, a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed are bonded to each other with a liquid crystal interposed therebetween.

Recently, in order to solve the narrow viewing angle problem of the liquid crystal display, a liquid crystal display adopting various new methods has been developed. Liquid crystal displays having a wide viewing angle include an in-plane switching mode (IPS), an optically compensated birefrigence mode (OCB), and a fringe field spooling (FFS).

The horizontal electric field type liquid crystal display device arranges the pixel electrode and the common electrode on the same substrate to generate a horizontal electric field between the electrodes. As a result, the long axes of the liquid crystal molecules are arranged in a horizontal direction with respect to the substrate, and thus have a wide viewing angle characteristic as compared with the conventional twisted nematic (TN) type liquid crystal display.

In addition, in the conventional transverse electric field type liquid crystal display, an organic insulating layer that is much thicker than the protective layer is formed to prevent an increase in parasitic capacitance between electrodes formed in the data line and the pixel region.

However, the parasitic capacitance between the data line and the common line formed on the data line is reduced due to the high thickness of the organic insulating layer. However, the distance between the pixel electrode and the common electrode in the pixel region is increased so that the pixel driving voltage increases. Occurred.

As such, when the pixel driving voltage rises, power consumption increases.

An object of the present invention is to provide a thin film transistor array substrate in which a parasitic capacitance is reduced by an organic insulating layer in a data line region, and a pixel driving voltage is reduced by forming only a passivation layer between a pixel electrode and a common electrode in a pixel region, and a method of manufacturing the same. .

Another object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, in which a pixel transmittance is improved by removing an organic insulating layer in a pixel region.

In addition, the present invention provides a thin film transistor array substrate and a method of manufacturing the same, which may implement a high resolution and low power liquid crystal display device while simplifying the process by leaving the photoresist film used in the source / drain electrode forming process as an organic insulating film on the data line. There is another purpose to serve.

The thin film transistor array substrate of the present invention for achieving the above object, the substrate; Gate lines and data lines cross-arranged to define pixel regions on the substrate; A switching element disposed in an intersection region of the gate line and the data line; A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And a common electrode and a common line respectively disposed on the pixel electrode and the data line, wherein the data line is covered by an organic insulating pattern, the data line and the organic insulating film are covered by a protective film, and the protective film. A common line is formed on the phase.

In addition, the method of manufacturing a thin film transistor array substrate of the present invention includes providing a substrate divided into a display area and a non-display area; Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad and a data pad in a non-display area; Sequentially forming a gate insulating film, a channel layer, and a source / drain metal film on the substrate on which the gate electrode or the like is formed, and then forming a channel layer, a source / drain electrode, and a data line; Performing a curing process on the substrate on which the source / drain electrodes and the like are formed to form an organic insulating film pattern on the data line and the source / drain electrodes; Forming a protective film on the substrate on which the organic insulating layer pattern is formed, and forming a second contact hole in a region corresponding to the first contact hole and a data pad region in a region corresponding to the gate pad region according to a mask process; And forming a transparent conductive material on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process.

In addition, a method of manufacturing a thin film transistor array substrate according to another embodiment of the present invention, providing a substrate divided into a display area and a non-display area; Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad and a data pad in a non-display area; Forming a gate insulating film and a semiconductor layer on the substrate on which the gate electrode and the like are formed and forming a channel layer; Forming a transparent conductive material on the substrate on which the channel layer is formed, and then forming a pixel electrode according to a mask process; Forming a source / drain metal film on the substrate on which the pixel electrode is formed, and forming a source / drain electrode and a data line; Performing a curing process on the substrate on which the source / drain electrodes and the like are formed to form an organic insulating film pattern on the data line and the source / drain electrodes; Forming a protective film on the substrate on which the organic insulating layer pattern is formed, and forming a second contact hole in a region corresponding to the first contact hole and a data pad region in a region corresponding to the gate pad region according to a mask process; And forming a transparent conductive material on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process.

According to the present invention, the parasitic capacitance is reduced by the organic insulating layer in the data line region, and only the passivation layer is formed between the pixel electrode and the common electrode in the pixel region, thereby reducing the pixel driving voltage.

In addition, the present invention has the effect of improving the pixel transmittance by removing the organic insulating film in the pixel region.

In addition, the present invention has the effect of implementing a high-resolution and low-power liquid crystal display while simplifying the process by leaving the photoresist film used in the source / drain electrode forming process as an organic insulating film on the data line as it is.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.
2A to 2I are views illustrating a manufacturing process of a thin film transistor array substrate according to a first embodiment of the present invention.
3A to 3I are views illustrating a manufacturing process of a thin film transistor array substrate according to a second embodiment of the present invention.
4A and 4B illustrate a structure of a data line region according to the related art and a structure of a data line region according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

In addition, in the description of the embodiments, each pattern, layer, film, region, or substrate is formed on or under the pattern of each pattern, layer, film, region, or substrate. In the case described, "on" and "under" include both those that are formed "directly" or "indirectly" through other components.

In addition, the criteria for the top, side or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for description, and does not mean a size that is actually applied.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.

Referring to FIG. 1, the transverse electric field type liquid crystal display according to the present invention is divided into a display area in which a plurality of pixel areas are formed and a non-display area in which a pad area is formed, and the gate line 101 and the data line 103 are divided into two parts. Cross-aligned to define a sub-pixel region.

The thin film transistor TFT, which is a switching element, is disposed in an area where the gate line 101 and the data line 103 cross each other. The thin film transistor includes a gate electrode 101a, a source / drain electrode, and a channel layer (not shown), which are wider than the gate line 101 and drawn in the pixel area direction.

The pixel electrode 129 having a plate structure is disposed in the pixel area in a direction parallel to the data line 103. In addition, the common electrodes 150 having a plurality of slit structures are alternately disposed on the pixel electrode 129. In addition, a common line 151 integrally formed with the common electrode 150 is disposed around the pixel area. The common line 151 overlaps the gate line 101 and the data line 103 along the circumference of the pixel area.

In addition, the pixel electrode 129 and the common electrode 150 of the present invention are formed in a vertically symmetrical structure along the direction of the data line 103 around the pixel center line parallel to the gate line 101. In addition, the common electrode 150 and the pixel electrode 129 are formed to have a predetermined angle in the vertical direction with respect to the pixel center line.

In addition, the pixel electrode 129 is formed in the shape of a square plate, but this is not fixed. Therefore, the plurality of slits may be formed like the common electrode 150.

In the present invention, in order to reduce parasitic capacitance in the thin film transistor region, a part of the common line 151 overlapping the thin film transistor is removed to form an open (OP) region. Therefore, the common line 151 made of a transparent conductive material does not exist on the gate electrode 101 and the source / drain electrodes.

In addition, a gate pad 110 extending from the gate line 101 is formed in the gate pad region of the liquid crystal display, and gates electrically contacted with each other through the first contact hole 231 on the gate pad 110. The pad contact electrode 310 is formed.

In addition, a data pad 120 extending from the data line 103 is formed in the data pad area of the liquid crystal display, and data electrically contacted with each other through the second contact hole 233 on the data pad 120. The pad contact electrode 320 is formed.

2A to 2I are views illustrating a manufacturing process of a thin film transistor array substrate according to a first embodiment of the present invention. A first embodiment of the present invention is a method of manufacturing a thin film transistor array substrate according to a five mask process.

Referring to FIG. 2A, a metal film is deposited on a lower substrate 100 made of a transparent insulating material by sputtering, and then a gate electrode 101a is formed in a pixel area, which is a display area, according to a first mask process, and then is non-displayed. The gate pad 110 and the data pad 120 are formed in the pad area, which is an area.

In the first mask process, a photoresist, which is a photosensitive material, is formed on the deposited metal film, and then a photoresist pattern is formed by an exposure and development process using a mask, and an etching process is performed using the photoresist pattern as a mask. .

As described above, in the first mask process, not only the gate electrode 101a, the gate pad 110, and the data pad 120 but also the gate line 101 (see FIG. 1) are formed together.

The metal film formed in the first mask process is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. It may be formed by laminating at least one of an alloy or a transparent conductive material ITO, IZO and ITZO.

In the drawing, the gate electrode 101a, the gate pad 110, and the data pad 120 are formed in a structure in which two metal layers are stacked. Can be.

As described above, when the gate electrode 101a or the like is formed on the lower substrate 100, as shown in FIGS. 2B to 2E, the gate insulating film 102, the amorphous silicon film, and the doped amorphous silicon film n + or The semiconductor layer 124 composed of p + and the source / drain metal layer 217 are sequentially formed, and then the gate insulating layer 102 on the gate electrode 101a is subjected to a second mask process using a halftone mask or a diffraction mask. The channel layer 114 is formed on it.

The photoresist used in the second mask process uses a material having low dielectric constant. The photosensitive film may be formed of an acrylic resin. The acrylic resin includes but is not limited to photo acryl. That is, the photoresist film is not limited to the photo acryl as long as it has a material having a low dielectric constant. Photo acrylics can be used.

In addition, the photosensitive film preferably has a lower dielectric constant than the protective film to be formed later. The dielectric constant may be 3.0 to 4.0, preferably, the dielectric constant of the photoresist may be 3.4 to 3.8. In the second mask process, the thickness of the photoresist layer corresponding to the non-transmissive region may be 3 to 6 μm. As such, when the photosensitive film having a low dielectric constant is used, a thickness of the protective film to be formed later may be formed to about 1000 mW.

The source / drain metal film 217 is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. Any of the alloys may be used. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the figure is formed of a single metal film, at least two or more metal films may be stacked in some cases.

When the photosensitive film is exposed and developed according to the second mask process, the first photoresist film pattern 300 and the second photoresist film pattern 300a are formed on the source / drain metal film 217. The first photoresist pattern 300 is formed in a region corresponding to the non-transmissive region and then in which a data line is formed. The semi-transmissive region and the non-transmissive region are mixed in the second photoresist pattern 300a and are formed in the region where the source / drain electrodes 117a and 117b and the channel layer 114 are formed.

The case in which the first photoresist pattern 300 and the second photoresist pattern 300a are photoresist having positive characteristics has been described as an example. Therefore, when the property of the photoresist film is negative characteristic, the photoresist film is patterned as opposed to the above positive characteristic.

As described above, when the first photoresist layer 300 and the second photoresist layer pattern 300a are formed on the lower substrate 100, an etching process is performed to source / drain electrodes 117a and 117b on the gate electrode 101a. And a channel layer 114, and a data line 103 in the data region.

Since the halftone mask or the diffraction mask is used, the channel layer pattern 114a is present under the data line 103.

As described above, when the source / drain electrodes 117a and 117b and the data line 103 are formed on the lower substrate 100, a curing process is continued.

As described above, when the curing process is performed, as illustrated in FIG. 2E, the first photoresist pattern 300 and the second photoresist pattern 300a are melted and cured to form the data line 103 and the source / drain electrodes 117a. , 117b remains on the organic insulating film pattern 250.

Then, as shown in FIG. 2F, a transparent conductive material is formed on the lower substrate 100 on which the source / drain electrodes 117a and 117b and the organic insulating layer pattern 250 are formed, and the pixel is processed according to the third mask process. The pixel electrode 129 is formed in the region. The transparent conductive material may use any one of ITO, IZO, and ITZO. The pixel electrode 129 is in direct contact with the drain electrode 117b.

As described above, when the pixel electrode 129 is formed on the lower substrate 100, as shown in FIGS. 2G and 2H, the passivation layer 119 is formed on the entire region of the lower substrate 100. Then, a photoresist film is formed on the lower substrate 100 according to the fourth mask process, and an exposure and development process are performed to form a third photoresist pattern 400.

Then, an etching process is performed using the third photoresist pattern 400 as a mask, and the first contact hole 231 and the second contact hole 233 are formed in the gate pad 110 and the data pad 120. To form.

The gate pad 110 and the data pad 120 are exposed to the outside by the first contact hole 231 and the second contact hole 233.

2I, a transparent conductive film is formed on the entire surface of the lower substrate 110, and then the common electrode 150, the common line 151, and the gate pad contact electrode 310 are formed by the fifth mask process. ) And the data pad contact electrode 320. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

The common line 151 is formed on the passivation layer 119 surrounding the data line 103, and in the region where the gate electrode 101a is formed, an open (OP) region is formed by removing the transparent conductive layer. This open area is to reduce parasitic capacitance that may be generated between the thin film transistor and the common line 151.

Therefore, in the present invention, the protective film 119 is secondarily wrapped while the data line 103 is completely covered by the organic insulating film pattern 250. Therefore, the common line 151 formed on the passivation layer 119 and the parasitic capacitance may be reduced to cover the data line 103.

In addition, since only the passivation layer 119 exists between the pixel electrode 129 and the common electrode 150 in the pixel area of the present invention, the pixel driving voltage may be lowered while improving the vertical transmittance of the pixel area.

3A to 3I are views illustrating a manufacturing process of a thin film transistor array substrate according to a second embodiment of the present invention.

Unlike the first embodiment, the second embodiment of the present invention is a method of manufacturing a thin film transistor array substrate according to a six mask process. Therefore, the same reference numerals refer to the same components, and thus, the portions omitted in the following description may be applied as described in the first embodiment.

As shown in FIG. 3A, a metal film is deposited on the lower substrate 100 made of a transparent insulating material, and then a gate electrode 101a is formed in a pixel area, which is a display area, according to a first mask process, and then a non-display area. The gate pad 110 and the data pad 120 are formed in the in pad area.

3B, a semiconductor layer including a gate insulating film 102, an amorphous silicon film, and a doped amorphous silicon film (n + or p +) is formed on the lower substrate 100 on which the gate electrode 101a and the like are formed. After forming 124, the channel layer 114 is formed on the gate insulating layer 102 on the gate electrode 101a according to the second mask process.

3C, a transparent conductive material is formed on the lower substrate 100, and then the pixel electrode 129 is formed by the third mask process. The pixel electrode 129 is in electrical contact with a portion of the channel layer 114.

As described above, when the pixel electrode 129 is formed, as shown in FIGS. 3D to 3F, the source / drain metal layer 217 is formed, and then on the source / drain electrode 217 according to a fourth mask process. The fourth photoresist pattern 500 is formed on the substrate. One side of the pixel electrode 129 is formed to be in direct contact with the lower side and the upper side by the channel layer 114 and the drain electrode 117b.

The photoresist used in the fourth mask process uses a material having low dielectric constant. The photosensitive film may be formed of an acrylic resin. The acrylic resin includes but is not limited to photo acryl. That is, the photoresist film is not limited to the photo acryl as long as it has a material having a low dielectric constant. Photo acrylics can be used.

In addition, the photosensitive film preferably has a lower dielectric constant than the protective film to be formed later. The dielectric constant may be 3.0 to 4.0, preferably, the dielectric constant of the photoresist may be 3.4 to 3.8. In the second mask process, the thickness of the photoresist layer corresponding to the non-transmissive region may be 3 to 6 μm. As such, when the photosensitive film having a low dielectric constant is used, a thickness of the protective film to be formed later may be formed to about 1000 mW.

The source / drain metal film 217 is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. Any of the alloys may be used. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the figure is formed of a single metal film, at least two or more metal films may be stacked in some cases.

An etching process is performed using the fourth photoresist pattern 500 as a mask, and source / drain electrodes 117a and 117b and a data line 103 are formed.

Subsequently, a curing process is performed to form an organic insulating pattern 250 on the data line 103 and the source / drain electrodes 117a and 117b.

That is, in the first and second embodiments of the present invention, the organic insulating film pattern 250 is formed by using the organic insulating film as the photoresist film used in the mask process without a separate organic film forming process.

3G to 3I, the passivation layer 119 and the photoresist layer are sequentially formed on the entire region of the lower substrate 100. Thereafter, the exposure and development processes are performed according to the fifth mask process to form the fifth photoresist pattern 600.

Thereafter, an etching process is performed using the fifth photoresist pattern 600 as a mask, and the first contact hole 231 and the second contact hole 233 are formed in the gate pad 110 and the data pad 120. To form.

The gate pad 110 and the data pad 120 are exposed to the outside by the first contact hole 231 and the second contact hole 233.

3I, a transparent conductive film is formed on the entire surface of the lower substrate 110, and then the common electrode 150, the common line 151, and the gate pad contact electrode 310 are formed by the sixth mask process. ) And the data pad contact electrode 320. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

The common line 151 is formed on the passivation layer 119 surrounding the data line 103, and in the region where the gate electrode 101a is formed, an open (OP) region is formed by removing the transparent conductive layer. This open area is to reduce parasitic capacitance that may be generated between the thin film transistor and the common line 151.

Therefore, in the present invention, the protective film 119 is secondarily wrapped while the data line 103 is completely covered by the organic insulating film pattern 250. Therefore, the common line 151 formed on the passivation layer 119 and the parasitic capacitance may be reduced to cover the data line 103.

In addition, since only the passivation layer 119 exists between the pixel electrode 129 and the common electrode 150 in the pixel area of the present invention, the pixel driving voltage may be lowered while improving the vertical transmittance of the pixel area.

4A and 4B illustrate a structure of a data line region according to the related art and a structure of a data line region according to the present invention.

Referring to FIG. 4A, in the related art, a data line DL is formed on a substrate S with a gate insulating layer GI interposed therebetween, and a passivation layer PAS and an organic insulating layer PA are formed on the data line DL. These are formed, respectively. The common line CL is formed on the organic insulating layer PA corresponding to the data line DL, and the pixel electrode PE is disposed in the pixel region adjacent to the data line DL with the organic insulating layer PA therebetween. The common electrode CE is formed, respectively.

As shown in FIG. 4A, since the organic insulating layer PA is uniformly formed on the substrate S, the gap between the pixel electrode P and the common electrode CE is large in the pixel area. . As a result, the transmittance of the pixel region is lowered and the pixel driving voltage is increased.

However, in the present invention as shown in FIG. 4B, by using the organic insulating film PA having a low dielectric constant for the photosensitive film used in the mask process, the data line DL is covered with the organic insulating film PA, and a protective film on the upper side. The PL is further covered to reduce parasitic capacitance in the data line region.

In the present invention, the organic insulating film PA does not exist in the pixel region, so that the transmittance of the pixel region is improved. In addition, since the organic insulating layer PA does not exist in the pixel region, the distance between the pixel electrode P and the common electrode CE is close, thereby reducing the pixel driving voltage.

Although described above with reference to the embodiment is only an example and is not intended to limit the invention, those of ordinary skill in the art to which the present invention does not exemplify the above within the scope not departing from the essential characteristics of this embodiment It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

101: gate line 150: common electrode
151: common line 103: data line
129: pixel electrode 250: organic insulating film pattern
119: shield OP: open area

Claims (12)

Board;
Gate lines and data lines cross-arranged to define pixel regions on the substrate;
A switching element disposed at an intersection of the gate line and the data line and including a channel layer;
A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And
A common electrode and a common line disposed on the pixel electrode and the data line, respectively;
The data line is covered by an organic insulating layer pattern, a channel layer pattern made of the same material as the channel layer is disposed below the data line, the data line and the organic insulating layer pattern are surrounded by a protective film, The common line is formed on the protective film,
And a dielectric constant of the organic insulating layer pattern is lower than that of the passivation layer.
The thin film transistor array substrate of claim 1, wherein the pixel electrode and the data line are formed on a gate insulating layer. The thin film transistor array substrate of claim 1, wherein one side of the pixel electrode is directly contacted from an upper side and a lower side by a channel layer and a drain electrode of the switching element. Providing a substrate divided into a display area and a non-display area;
Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad and a data pad in a non-display area;
A gate insulating film, a channel layer, and a source / drain metal film are sequentially formed on a substrate on which the gate electrode and the like are formed, and then a channel layer, a source / drain electrode, a data line, and a material disposed under the data line and the same material as the channel layer Forming a channel layer pattern consisting of;
Performing a curing process on the substrate on which the source / drain electrodes and the like are formed to form an organic insulating film pattern on the data line and the source / drain electrodes;
Forming a protective film on the substrate on which the organic insulating layer pattern is formed, and forming a second contact hole in a region corresponding to the first contact hole and a data pad region in a region corresponding to the gate pad region according to a mask process; And
Forming a transparent conductive material on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process;
And a dielectric constant of the organic insulating layer pattern is lower than that of the passivation layer.
The method of claim 4, wherein
Forming the channel layer, the source / drain electrode, the data line and the channel layer pattern, and then forming a pixel electrode,
And the pixel electrode and the drain electrode are in direct contact with each other.
The method of claim 4, wherein the passivation layer has a thickness of 1000 ns.
The method of claim 4, wherein in the forming of the organic insulating layer pattern,
The photoresist pattern is cured by removing the patterned photoresist pattern to form the source / drain electrodes, and the photoresist pattern is cured to form an organic insulating pattern on the data line and the source / drain electrodes. Method of manufacturing a thin film transistor array substrate.
5. The method of manufacturing a thin film transistor array substrate according to claim 4, wherein a diffraction mask or a halftone mask is used in the step of forming the source / drain electrodes.
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