KR20120003771A - Thin film transistor array substrate and method for fabricating the same - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate and a method for fabricating the same are provided to prevent the failure of pixel electrode which is formed on the same layer with a data line. CONSTITUTION: The gate electrode(101a) of a switching device, a gate pad(110), and a pixel electrode(129) are formed on a substrate(100). A common electrode(150) is arranged on the pixel electrode between gate insulating film(102). A data line and a pixel electrode are formed on the same layer. The data line is covered with a protective film(119). A common line(151) is formed on the top of the data line between an organic insulating film(250).

Description

Thin Film Transistor Array Substrate and Manufacturing Method Thereof {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a liquid crystal display device.

In general, a liquid crystal display (LCD) displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field. In the liquid crystal display, a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor (TFT) array is formed are bonded to each other with a liquid crystal interposed therebetween.

Recently, in order to solve the narrow viewing angle problem of the liquid crystal display, a liquid crystal display adopting various new methods has been developed. Liquid crystal displays having a wide viewing angle include an in-plane switching mode (IPS), an optically compensated birefrigence mode (OCB), and a fringe field spooling (FFS).

The horizontal electric field type liquid crystal display device arranges the pixel electrode and the common electrode on the same substrate to generate a horizontal electric field between the electrodes. As a result, the long axis of the liquid crystal molecules is arranged in a horizontal direction with respect to the substrate, and thus has a wide viewing angle characteristic as compared with a conventional twisted nematic (TN) type liquid crystal display.

However, in the conventional transverse type liquid crystal display device, the pixel electrode and the common electrode are disposed up and down with a passivation layer interposed therebetween, wherein the pixel electrode is formed on the same layer as the source / drain metal layer of the thin film transistor.

As such, when the pixel electrode and the source / drain metal layer are formed on the same layer, both edges of the pixel electrode and the data line are positioned close to each other, and thus short circuit failure frequently occurs. In particular, when foreign matter is placed between the pixel electrode and the data line during the process, the process proceeds while the data line and the pixel electrode are short-circuited and the product yield is also lowered.

In addition, when the pixel electrode and the common electrode are disposed with the passivation layer interposed therebetween, a parasitic capacitance between the common electrode and the data line increases, resulting in deterioration of screen quality.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, which completely prevent a short circuit with pixel electrodes formed on the same layer by completely enclosing a data line with a protective film.

In addition, another object of the present invention is to provide a thin film transistor array substrate and a method of manufacturing the same, by forming a pixel electrode in a lift-off process to reduce short-circuit defects caused by foreign substances.

Another object of the present invention is to provide a thin film transistor array substrate having a low dielectric constant organic insulating layer and a black matrix width of a color filter substrate, thereby improving an aperture ratio and a method of manufacturing the same.

The thin film transistor array substrate of the present invention for achieving the above object, the substrate; Gate lines and data lines cross-arranged to define pixel regions on the substrate; A switching element disposed in an intersection region of the gate line and the data line; A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And a common electrode and a common line respectively disposed on the pixel electrode and the data line, wherein a gate electrode, a gate pad, and a pixel electrode of a switching element are formed on the substrate, and the common electrode is disposed on the pixel electrode with a gate insulating film interposed therebetween. An electrode is disposed, the data line and the pixel electrode are formed on the same layer, the data line is covered by a protective film, and a common line is formed on the data line covered by the protective film with an organic insulating film therebetween. It is characterized by that.

In addition, the method of manufacturing a thin film transistor array substrate of the present invention includes providing a substrate divided into a display area and a non-display area; Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad in a non-display area; Sequentially forming a gate insulating film, a channel layer, and a source / drain metal film on the substrate on which the gate electrode and the like are formed, and simultaneously forming source / drain electrodes, data lines, and data pads using a diffraction mask or a halftone mask; Forming a protective film on all regions of the substrate on which the source / drain electrodes are formed, and then forming a photosensitive film pattern, and then forming a first transparent conductive film on all regions of the substrate; Forming a pixel electrode on the substrate on which the first transparent conductive film is formed by removing a photoresist pattern according to a lift-off process; An organic insulating layer is formed on the substrate on which the pixel electrode is formed, and then an exposure and development process is performed to form a first contact hole in a region corresponding to the gate pad region and a second contact hole in a region corresponding to the data pad region. step; And forming a first transparent conductive film on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process.

The present invention has the effect of completely preventing the short circuit with the pixel electrode formed on the same layer by completely covering the data line with a protective film.

In addition, the present invention has the effect of reducing the short-circuit defect between the elements due to the foreign matter by forming the pixel electrode in the lift-off process.

In addition, the present invention has the effect of improving the aperture ratio by reducing the width of the black matrix of the color filter substrate using a low dielectric constant organic insulating film.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.
2A to 2I are views illustrating a manufacturing process of a thin film transistor array substrate according to the present invention.
3A and 3B show a comparison of a data line region according to the prior art and a data line region according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

In addition, in the description of the embodiments, each pattern, layer, film, region, or substrate is formed on or under the pattern of each pattern, layer, film, region, or substrate. In the case described, "on" and "under" include both those that are formed "directly" or "indirectly" through other components.

In addition, the criteria for the top, side or bottom of each component will be described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 is a view illustrating a pixel area of a thin film transistor array substrate according to the present invention.

Referring to FIG. 1, a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention is divided into a display area in which a plurality of pixel areas are formed and a non-display area in which a pad area is formed, and the gate line 101 and the data line 103 are separated from each other. Cross-aligned to define a sub-pixel region.

The thin film transistor TFT, which is a switching element, is disposed in an area where the gate line 101 and the data line 103 cross each other. The thin film transistor includes a gate electrode 101a, a source / drain electrode, and a channel layer (not shown), which are wider than the gate line 101 and drawn in the pixel area direction.

The pixel electrode 129 having a plate structure is disposed in the pixel area in a direction parallel to the data line 103. In addition, the common electrodes 150 having a plurality of slit structures are alternately disposed on the pixel electrode 129. In addition, a common line 151 integrally formed with the common electrode 150 is disposed around the pixel area. The common line 151 overlaps the gate line 101 and the data line 103 along the circumference of the pixel area.

In addition, the pixel electrode 129 and the common electrode 150 of the present invention are formed in a vertically symmetrical structure along the direction of the data line 103 around the pixel center line parallel to the gate line 101. In addition, the common electrode 150 and the pixel electrode 129 are formed to have a predetermined angle in the vertical direction with respect to the pixel center line.

In addition, the pixel electrode 129 is formed in the shape of a square plate, but this is not fixed. Therefore, the plurality of slits may be formed like the common electrode 150.

In the present invention, in order to reduce parasitic capacitance in the thin film transistor region, a part of the common line 151 overlapping the thin film transistor is removed to form an open (OP) region. Therefore, the common line 151 made of a transparent conductive material does not exist on the gate electrode 101 and the source / drain electrodes.

In addition, a gate pad 110 extending from the gate line 101 is formed in the gate pad region of the liquid crystal display, and gates electrically contacted with each other through the first contact hole 231 on the gate pad 110. The pad contact electrode 310 is formed.

In addition, a data pad 120 extending from the data line 103 is formed in the data pad area of the liquid crystal display, and data electrically contacted with each other through the second contact hole 233 on the data pad 120. The pad contact electrode 320 is formed.

2A to 2I are views illustrating a manufacturing process of a thin film transistor array substrate according to the present invention.

Referring to FIG. 2A, a metal film is deposited on a lower substrate 100 made of a transparent insulating material by sputtering, and then a gate electrode 101a is formed in a pixel area, which is a display area, according to a first mask process, and then is non-displayed. The gate pad 110 is formed in the pad region which is the region.

In the first mask process, a photoresist, which is a photosensitive material, is formed on the deposited metal film, and then a photoresist pattern is formed by an exposure and development process using a mask, and an etching process is performed using the photoresist pattern as a mask. .

As described above, in the first mask process, not only the gate electrode 101a and the gate pad 110 but also the gate line 101 (see FIG. 1) are formed together.

The metal film formed in the first mask process is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. It may be formed by laminating at least one of an alloy or a transparent conductive material ITO, IZO and ITZO.

In the drawing, the gate electrode 101a, the gate pad 110, and the data pad 120 are formed in a structure in which two metal layers are stacked. Can be.

As described above, when the gate electrode 101a or the like is formed on the lower substrate 100, as shown in FIGS. 2B and 2C, the gate insulating film 102, the amorphous silicon film, and the doped amorphous silicon film n + or The semiconductor layer 124 composed of p + and the source / drain metal film 217 are sequentially formed, and then a second mask process using a halftone mask or a diffraction mask is performed. In the second mask process, since a mask having a transflective region, a non-transmissive region, and a transmissive region is used, as shown in FIG. 2B, the second photoresist layer pattern 300a having a different thickness from that of the first photoresist layer pattern 300. ) Is formed.

The etching process is performed by using the first photoresist pattern 300 and the second photoresist pattern 300a as a mask, and the channel layer 114 and the source / source are formed on the gate insulating layer 102 on the gate electrode 101a. Drain electrodes 117a and 117b are formed.

The source / drain metal film 217 is formed from molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), or a combination thereof. Any of the alloys may be used. In addition, a transparent conductive material such as indium tin oxide (ITO) may be used. In addition, although the figure is formed of a single metal film, at least two or more metal films may be stacked in some cases.

In addition, the data line 103 and the data pad 120 are formed together. Since a process using a diffraction mask or a halftone mask, a channel layer pattern 114a exists below the data line 103 and the data pad 120.

When the source / drain electrodes 117a and 117b are formed as described above, as shown in FIGS. 2D to 2F, the passivation layer 119 is formed on the entire region of the lower substrate 100.

Then, a photoresist film is formed on the lower substrate 100, and a third photoresist pattern 400 is formed on the passivation layer 119 according to a third mask process. In addition, the third photoresist pattern 400 does not cover a part of the drain electrode 117b in the pixel region direction. A portion of the protective film 119 in the drain electrode 117b region is exposed.

When the third photoresist layer pattern 400 is formed, an etching process for removing the passivation layer 119 of the pixel area is performed using the third photoresist layer pattern 400 as a mask. Therefore, the protective film 119 in the pixel region and the drain electrode 117b region is removed.

Then, the transparent conductive film 229 is formed on the entire area of the lower substrate 100 in a state where the third photoresist pattern 400 is present on the lower substrate 100.

The transparent conductive film 229 is formed on the third photoresist pattern 400, on the gate insulating layer 102 and the exposed drain electrode 117b of the pixel region.

Then, as shown in FIG. 2F, when the third photoresist pattern 400 is removed by a lift-off process, the pixel electrode 129 is formed on the gate insulating layer 102 of the pixel region.

The pixel electrode 129 is in direct contact with the drain electrode 117b which is a switching element.

Next, referring to FIGS. 2G to 2I, the organic insulating layer 250 is formed on the entire region of the lower substrate 100 on which the pixel electrode 129 is formed, and then the organic insulating layer 250 is formed by the fourth mask process. The first contact hole 231 and the second contact hole 233 are formed.

The organic insulating layer 250 is made of a material having low dielectric constant. The organic insulating layer 250 may be formed of an acrylic resin. The acrylic resin includes but is not limited to photo acryl. That is, the organic insulating layer 250 is not limited to the photo acrylic as long as the material has a low dielectric constant. Photo acrylics can be used.

In addition, the organic insulating layer 250 preferably has a lower dielectric constant than the protective layer 119. The dielectric constant may be 3.0 to 4.0, and preferably, the dielectric constant of the organic insulating layer 250 may be 3.4 to 3.8. The organic insulating layer 250 may have a thickness of about 3 μm to about 6 μm. As such, when the organic insulating layer 250 having the low dielectric constant is used, the thickness of the protective layer 119 can be formed to about 1000 mW.

Thereafter, an etching process is performed using the first contact hole 231 and the second contact hole 233 as a mask, whereby the gate pad 110 and the second contact hole 233 in the first contact hole 231 region. ) Respectively expose the data pads 120 of the region.

As described above, when the first and second contact holes 231 and 233 are formed in the organic insulating layer 250, as shown in FIG. 2H, the transparent conductive film 350 is continuously formed on the entire surface of the lower substrate 110. After the formation, a photosensitive film is formed. The fourth photoresist pattern 600 is formed according to a mask process. The transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO).

Portions of the fourth photoresist pattern 600 are filled in the first and second contact holes 231 and 233. This is to form the gate pad contact electrode 310 and the data pad contact electrode 320 by preventing the transparent conductive layer 350 from being removed by the etching process.

Then, the transparent conductive film 350 is etched using the fourth photoresist pattern 600 as a mask. The common electrode 150 and the common line 151 are formed on the lower substrate 100. In addition, a gate pad contact electrode 310 is formed in an area of the first contact hole 231, and a data pad contact electrode 320 is formed in an area of the second contact hole 233.

Therefore, in the present invention, the data line 103 is covered with the protective film 119, and is electrically insulated from the pixel electrode 129 formed on the adjacent same layer. Therefore, even if foreign matters are generated during the process, short circuit defects of the data line 103 and the pixel electrode 129 can be prevented.

In addition, in the present invention, the passivation layer 119 and the organic insulating layer 250 having the low dielectric constant characteristics are formed on the data line 103, thereby eliminating parasitic capacitance generated between the data line 103 and the common line 151. Can be reduced.

In addition, in the present invention, the etching process is not performed after the protective layer 119 is formed, and the etching process is not performed even when the pixel electrode 129 is formed, thereby reducing the etching loss and securing the interlayer margin.

3A and 3B show a comparison of a data line region according to the prior art and a data line region according to the present invention.

Referring to FIG. 3A, in the related art, a channel layer pattern CP is formed below the data line DL and the data line DL with a gate insulating layer GI interposed therebetween. The passivation layer PL and the common line CL are formed on the data line DL, respectively. The pixel electrode P is formed in the pixel region adjacent to the data line DL, and both the data line DL and the pixel electrode P are formed on the same layer.

Therefore, when foreign matter occurs between the data line DL and the channel layer pattern CP and the pixel electrode P during the process, the data line DL and the pixel electrode P are electrically shorted.

However, in the present invention as shown in FIG. 3B, the data line DL is completely covered by the passivation layer PL, and is electrically insulated from the adjacent pixel electrode P. In FIG. In addition, since the organic insulating layer PA is formed on the passivation layer PL on the data line DL, parasitic capacitance that may be generated between the common line CL and the data line DL may be reduced.

Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains should not be exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

101: gate line 150: common electrode
151: common line 103: data line
129: pixel electrode 250: organic insulating film
119: shield OP: open area

Claims (8)

Board;
Gate lines and data lines cross-arranged to define pixel regions on the substrate;
A switching element disposed in an intersection region of the gate line and the data line;
A pixel electrode in a direction parallel to the data line in the pixel area, and having a symmetrical structure up and down with respect to the center of the pixel area; And
A common electrode and a common line disposed on the pixel electrode and the data line, respectively;
A gate electrode, a gate pad, and a pixel electrode of a switching element are formed on the substrate, and a common electrode is disposed on the pixel electrode with a gate insulating film interposed therebetween.
The data line and the pixel electrode are formed on the same layer, the data line is covered by a protective film,
And a common line formed over the data line covered by the passivation layer with an organic insulating layer interposed therebetween.
The thin film transistor array substrate of claim 1, wherein the pixel electrode and the data line are formed on a gate insulating film, and the pixel electrode and the data line are electrically insulated by a protective film. The thin film transistor array substrate of claim 1, wherein an organic insulating layer is formed on the passivation layer on the data line and the pixel electrode. Providing a substrate divided into a display area and a non-display area;
Forming a metal film on the substrate, forming a gate electrode and a gate line in a display area according to a mask process, and forming a gate pad in a non-display area;
Sequentially forming a gate insulating film, a channel layer, and a source / drain metal film on the substrate on which the gate electrode and the like are formed, and simultaneously forming source / drain electrodes, data lines, and data pads using a diffraction mask or a halftone mask;
Forming a protective film on all regions of the substrate on which the source / drain electrodes are formed, and then forming a photosensitive film pattern, and then forming a first transparent conductive film on all regions of the substrate;
Forming a pixel electrode on the substrate on which the first transparent conductive film is formed by removing a photoresist pattern according to a lift-off process;
Forming an organic insulating layer on the substrate on which the pixel electrode is formed, and then performing exposure and development processes to form a first contact hole in a region corresponding to the gate pad region and a second contact hole in a region corresponding to the data pad region step;
Forming a first transparent conductive film on the substrate on which the first and second contact holes are formed, and then forming a common electrode, a common line, a data pad contact electrode, and a gate pad contact electrode according to a mask process Array substrate manufacturing method.
The method of claim 4, wherein the first transparent conductive film is formed on the photoresist pattern, the pixel electrode of the pixel region, and the exposed channel layer.
5. The method of claim 4, wherein the pixel electrode and the drain electrode are in direct contact.
The method of claim 4, wherein the passivation layer is covered on the data line and electrically insulated from adjacent pixel electrodes.
The method of claim 4, wherein after forming the protective film, in forming a photoresist pattern,
And etching the protective film formed on a portion of the pixel region and the drain electrode using the photoresist pattern as a mask.

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