KR20060067281A - Thin film transistor substrate and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate and a method of manufacturing the same which can improve the image quality of a liquid crystal panel by increasing the capacity of a storage capacitor.

The present invention provides a semiconductor device comprising: a gate line and a data line crossing each other with a gate insulating film interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; And a storage capacitor formed by the pixel electrode and the gate line positioned with the gate insulating layer interposed therebetween, and the gate insulating layer included in the storage capacitor has a thickness lower than that of the gate insulating layer in the peripheral region of the storage capacitor.

Description

Thin Film Transistor Substrate And Method For Fabricating The Same             

1 is a plan view partially showing a conventional thin film transistor substrate.

FIG. 2 is a cross-sectional view taken along the line II ′ of the thin film transistor substrate illustrated in FIG. 1.

3A through 3D are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 2.

4 is a waveform diagram illustrating a voltage supplied to a liquid crystal display panel.

5 is a plan view partially showing a thin film transistor substrate of the present invention.

FIG. 6 is a cross-sectional view according to a first embodiment of the present invention taken along the line II-II ′ of FIG. 5.

7A to 7E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

8A to 8C are diagrams illustrating in detail a process of forming the gate insulating film of FIG. 7B.

9A to 9C are diagrams illustrating in detail a process of forming the protective film of FIG. 7D.

FIG. 10 is a cross-sectional view according to a second exemplary embodiment of the present invention taken along the line II-II ′ of FIG. 5.

11A through 11B are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

2, 102: gate line 4, 104: data line

6, 106 thin film transistor 8, 108 gate electrode

10, 110: source electrode 12, 102: drain electrode

14, 114: active layer 16, 116: contact hole

18, 118: pixel electrodes 20, 120: storage capacitor

42, 142: lower substrate 44, 144: gate insulating film

50, 150: protective film 180, 182, 184: diffraction mask

190, 192, 194 photoresist

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate capable of improving the image quality of a liquid crystal panel by increasing the capacity of a storage capacitor and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel (hereinafter, referred to as a "liquid crystal panel") in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a thin film transistor substrate and a color filter substrate facing each other, a liquid crystal injected between the two substrates, and a spacer for maintaining a cell gap between the two substrates.

The thin film transistor substrate is composed of a pixel electrode formed at each liquid crystal cell region defined by the intersection of the gate line and the data line, a thin film transistor connected between the gate line and the data line and the pixel electrode, a plurality of insulating films, and an alignment film applied thereon.

The color filter substrate includes a color filter formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode for supplying a reference voltage to the liquid crystal in common, and an alignment layer applied thereon.

The liquid crystal panel may combine the thin film transistor substrate and the color filter substrate to inject and encapsulate the liquid crystal to complete the liquid crystal panel, or to form a liquid crystal on any one of the two substrates and then attach the liquid crystal panel.

1 is a plan view illustrating a conventional thin film transistor substrate, and FIG. 2 is a cross-sectional view taken along line II ′ of the thin film transistor substrate illustrated in FIG. 1.                         

Referring to FIGS. 1 and 2, a typical thin film transistor substrate includes a gate line 2 and a data line 4 intersecting each other with a gate insulating layer 44 interposed therebetween on a lower substrate 42, and at each intersection thereof. A thin film transistor (hereinafter referred to as " TFT ") 6 and a pixel electrode 18 formed in a cell region provided in an intersecting structure. The TFT substrate also includes a storage capacitor 20 formed at an overlapping portion of the pixel electrode 18 and the previous gate line 2.

The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to the pixel electrode 18, The active layer 14 overlaps the gate electrode 8 and forms a channel between the source electrode 10 and the drain electrode 12. The active layer 14 is formed to overlap the data line 4, the source electrode 10, and the drain electrode 12, and further includes a channel portion between the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 for ohmic contact with the data line 4, the source electrode 10, and the drain electrode 12 is further formed on the active layer 14.

The TFT 6 causes the pixel voltage signal supplied to the data line 4 to be charged and held in the pixel electrode 18 in response to the gate signal supplied to the gate line 2.

The pixel electrode 18 is connected to the drain electrode 12 of the TFT 6 through the contact hole 16 penetrating the protective film 50. The pixel electrode 18 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal located between the TFT substrate and the color filter substrate is rotated by dielectric anisotropy and transmits light incident through the pixel electrode 18 from the light source (not shown) to the upper substrate.

The storage capacitor 20 is formed by the front gate line 2 and the pixel electrode 18. The gate insulating layer 44 and the passivation layer 50 are positioned between the gate line 2 and the pixel electrode 18. The storage capacitor 20 helps the pixel voltage charged in the pixel electrode 18 to be maintained until the next pixel voltage is charged.

Hereinafter, a method of manufacturing a TFT substrate will be described with reference to FIGS. 3A to 3D.

First, the gate metal layer is formed on the lower substrate 42 through a deposition method such as a sputtering method, and then the gate metal layer is patterned by a photolithography process and an etching process, so that the gate line 2 and the gate electrode (as shown in FIG. Gate patterns including 8) are formed.

The gate insulating layer 44 is formed on the lower substrate 42 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. An amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed on the lower substrate 42 on which the gate insulating layer 44 is formed.

A source / drain including a data line 4, a source electrode 10, and a drain electrode 12 as shown in FIG. 3B using a photolithography process and an etching process using a diffraction mask on the source / drain metal layer. A semiconductor pattern 45 including an ohmic contact layer 48 and an active layer 14 is formed under the pattern and the source drain pattern.

The semiconductor pattern 45 may be formed separately from the source / drain pattern using a separate mask process.

After the protective film 50 is entirely formed on the gate insulating film 44 on which the source / drain patterns are formed by deposition, such as PECVD or sputtering, the contact hole 16 is patterned by a photolithography process and an etching process. Is formed. The contact hole 16 penetrates through the passivation layer 50 to expose the drain electrode 12.

After the transparent electrode material is entirely deposited on the passivation layer 50 by a deposition method such as sputtering, the transparent electrode material is patterned through a photolithography process and an etching process to form the pixel electrode 18 as illustrated in FIG. 3D. The pixel electrode 18 is electrically connected to the drain electrode 12 through the contact hole 16. In addition, the pixel electrode 18 is formed to overlap the front gate line 2 with the gate insulating layer 44 and the passivation layer 50 interposed therebetween to form the storage capacitor 20.

In this TFT substrate, the gate voltage Vg is supplied to the gate electrode 8 of the TFT 6 as shown in FIG. 4, and the data voltage Vd is supplied to the source electrode 10. When a gate voltage Vg equal to or greater than the threshold voltage of the TFT 6 is applied to the gate electrode 8 of the TFT 6, a channel is formed between the source electrode 10 and the drain electrode 12, and the data voltage Vd is increased. The liquid crystal cell Clc and the storage capacitor 20 (Cst) are charged via the source electrode 10 and the drain electrode 12 of the TFT.

The data voltage Vd and the voltage Vlc charged in the liquid crystal cell Clc have a difference equal to the feed through voltage ΔVp, and the feed through voltage ΔVp is represented by Equation 1 below. Is defined as                         

Here, Cgd is a parasitic capacitor formed between the gate terminal and the drain terminal of the TFT, and ΔVg is the difference voltage between the Vgh voltage and the Vgl voltage.

The feed through voltage DELTA Vp is a cause of deterioration of image quality such as afterimages such as flicker. Accordingly, studies to reduce image quality deterioration by maximizing the storage capacitor 120 capacity Cst in order to minimize the feed through voltage ΔVp by Equation 1 have been actively conducted.

The capacity Cst of the storage capacitor is defined by Equation 2.

Is the dielectric constant of the material forming the gate insulating film 44 and the protective film 50, A is the area of the gate electrode 8 of the storage capacitor 20, and D is the gate insulating film 44 and the protective film 50. Is the thickness.

That is, in order to increase the capacity Cst of the storage capacitor, the material forming the gate insulating film 44 and the protective film 50 of the storage capacitor 20 is changed to increase the dielectric constant?, Or the storage capacitor 20 Increase the area A of the gate electrode 8 of the gate electrode 8 or the thickness D of the gate insulating film 44 and the protective film 50, that is, the gate electrode 8 and the pixel electrode 18 of the storage capacitor 20. The gap between them should be reduced.

However, in order to increase the dielectric constant ε of the insulating film 44 and the protective film 50, the change of the material of the gate insulating film 44 and the protective film 50 becomes additional costs due to the increase of other processes and the change of the material, and the storage capacitor An increase in the area A of 20 results in a decrease in the aperture ratio of the liquid crystal panel. In addition, in order to reduce the thickness D of the gate insulating film 44 and the passivation layer 50, the thickness D of the gate insulating layer 44 and the passivation layer 50 of the liquid crystal panel is reduced in addition to the storage capacitor. Since there is a problem that the capacity of the parasitic capacitor is increased, there is a lot of difficulty in increasing the capacity (Cst) of the storage capacitor 20.

Accordingly, an object of the present invention is to provide a thin film transistor substrate and a method of manufacturing the same, which can improve the image quality of a liquid crystal panel by increasing the capacity of a storage capacitor.

In order to achieve the above object, a thin film transistor substrate according to an embodiment of the present invention includes a gate line and a data line crossing each other with a gate insulating film interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; And a storage capacitor formed by the pixel electrode and the gate line positioned with the gate insulating layer interposed therebetween, and the gate insulating layer included in the storage capacitor has a thickness lower than that of the gate insulating layer in the peripheral region of the storage capacitor.

The thin film transistor substrate may further include a passivation layer disposed on the gate insulating layer and protecting the thin film transistor and the data line, and the passivation layer positioned on the storage capacitor may have a thickness lower than that of a peripheral region of the storage capacitor.

The passivation layer further includes a contact hole exposing the drain electrode of the thin film transistor, and the pixel electrode is connected to the drain electrode of the thin film transistor through the contact hole.

Method of manufacturing a thin film transistor substrate according to an embodiment of the present invention comprises the steps of forming a gate line; Forming a gate insulating film covering the gate line; Forming a data line crossing the gate line with the gate insulating layer interposed therebetween; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a pixel electrode connected to the thin film transistor; And forming a storage capacitor including the pixel electrode and the gate line positioned with the gate insulating layer interposed therebetween, wherein forming the gate insulating layer includes: determining a thickness of the gate insulating layer included in the storage capacitor; And forming a thickness lower than that of the gate insulating film in the peripheral region of the capacitor.

The forming of the gate insulating layer may include forming a photoresist pattern on the gate insulating layer, the photoresist pattern having a height lower than a peripheral area of the storage capacitor in a region of the storage capacitor using a diffraction mask; Etching the photoresist pattern to expose a gate insulating film in a formation region of the storage capacitor; Partially removing the exposed gate insulating layer using the ashed photoresist pattern as a mask; Removing the ashed photoresist pattern.

The method of manufacturing the thin film transistor substrate further includes forming a passivation layer on the gate insulating layer and included in the storage capacitor, and forming the passivation layer included in the storage capacitor includes: a passivation layer included in the storage capacitor. The thickness of the storage capacitor is formed to have a thickness lower than that of the passivation layer of the peripheral area of the storage capacitor.

The forming of the passivation layer included in the storage capacitor may further include forming a contact hole exposing the drain electrode of the thin film transistor.

The forming of the passivation layer included in the storage capacitor may include forming a photoresist pattern on the passivation layer, the photoresist pattern having a height lower than a peripheral area of the storage capacitor in the formation region of the storage capacitor using a diffraction mask; Patterning the passivation layer using the photoresist pattern as a mask to form the contact hole; Etching the photoresist pattern to expose a protective film to be included in the storage capacitor; Partially removing the exposed protective film using the ashed photoresist pattern as a mask; Removing the ashed photoresist pattern.

The pixel electrode is connected to the drain electrode of the thin film transistor through the contact hole.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 through 11C.

5 is a plan view partially illustrating a TFT substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view according to the first exemplary embodiment of the present invention taken along line II-II ′ of FIG. 5.

5 and 6, a TFT substrate according to an embodiment of the present invention includes a gate line 102 and a data line 104 formed to intersect on a lower substrate 142 with a gate insulating layer 144 therebetween; A TFT 106 formed at each intersection thereof and a pixel electrode 118 formed at a cell region provided with the intersection structure. In addition, the TFT substrate includes a storage capacitor 120 formed at an overlapping portion of the pixel electrode 118 and the previous gate line 102.

The TFT 106 includes a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, a drain electrode 112 connected to the pixel electrode 118, The active layer 114 overlaps the gate electrode 108 and forms a channel between the source electrode 110 and the drain electrode 112. The active layer 114 is formed to overlap the data line 104, the source electrode 110, and the drain electrode 112, and further includes a channel portion between the source electrode 110 and the drain electrode 112. An ohmic contact layer 148 for ohmic contact with the data line 104, the source electrode 110, and the drain electrode 112 is further formed on the active layer 114.                     

The TFT 106 allows the pixel voltage signal supplied to the data line 104 to be charged and held in the pixel electrode 118 in response to the gate signal supplied to the gate line 102.

The pixel electrode 118 is connected to the drain electrode 112 of the TFT 106 through the contact hole 116 penetrating the protective film 150. The pixel electrode 118 generates a potential difference from the common electrode formed on the upper substrate (not shown) by the charged pixel voltage. Due to this potential difference, the liquid crystal located between the TFT substrate and the color filter substrate is rotated by dielectric anisotropy, and the light incident through the pixel electrode 118 from the light source (not shown) is transmitted to the upper substrate.

The storage capacitor 120 is formed by the front gate line 102 and the pixel electrode 118. The gate insulating layer 144 and the passivation layer 150 are positioned between the gate line 102 and the pixel electrode 118. The storage capacitor 120 helps to maintain the pixel voltage charged in the pixel electrode 118 until the next pixel voltage is charged.

Here, the gate insulating layer 144 and the passivation layer 150 of the storage capacitor 120 have a thickness that is relatively lower than that of the gate insulating layer 144 and the passivation layer 150 in the peripheral region of the storage capacitor 120 using a diffraction mask. Is formed.

As a result, the distance between the pixel electrode 118 and the gate line 102 is reduced, thereby increasing the capacitance Cst of the storage capacitor 120 and improving the image quality of the liquid crystal panel.

Hereinafter, a method of manufacturing a TFT substrate according to a first embodiment of the present invention will be described with reference to FIGS. 7A to 7E.

First, as the gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method, and then the gate metal layer is patterned by a photolithography process and an etching process, as shown in FIG. 7A, the gate line 102 and the gate electrode. Gate patterns comprising 108 are formed.

Subsequently, the gate insulating layer 144 and the photoresist are deposited on the lower substrate 142 on which the gate patterns are formed by deposition, for example, PECVD and sputtering, and using a diffraction mask including a blocking region and a semi-transmissive region. By patterning the photolithography process and the etching process, as shown in FIG. 7B, the gate insulating layer 144 included in the storage capacitor 120 is relatively lower than the height of the gate insulating layer 144 in the peripheral region of the storage capacitor 120. It is formed to have a thickness.

Subsequently, an amorphous silicon layer, an n + amorphous silicon layer, and a source / drain metal layer are sequentially formed on the lower substrate 142 on which the gate insulating layer 144 is formed. A source / drain including a data line 104, a source electrode 110, and a drain electrode 112 as shown in FIG. 7C by using a photolithography process and an etching process using a diffraction mask on the source / drain metal layer. A semiconductor pattern 145 including an ohmic contact layer 148 and an active layer 114 is formed under the pattern and the source drain pattern.

The semiconductor pattern 145 may be formed separately from the source / drain pattern using a separate mask process.

Subsequently, the passivation layer 150 and the photoresist are entirely deposited on the lower substrate 142 on which the source / drain electrodes 110 and 112 and the semiconductor pattern 145 are formed by a deposition method such as PECVD and sputtering. And a contact hole 116 exposing the drain electrode 112 as shown in FIG. 7D by patterning the photolithography process and the etching process using a diffraction mask including a blocking region and a semi-transmissive region, as well as storage. The passivation layer 150 included in the capacitor 120 is formed to have a thickness relatively lower than the height of the passivation layer 150 in the peripheral region of the storage capacitor 120.

Then, the transparent electrode material is entirely deposited on the passivation layer 150 by a deposition method such as sputtering, and then the transparent electrode material is patterned through a photolithography process and an etching process, thereby forming the pixel electrode 118 as shown in FIG. 7E. Is formed. The pixel electrode 118 is electrically connected to the drain electrode 112 through the contact hole 116. In addition, the pixel electrode 118 is formed to overlap the front gate line 102 with the gate insulating layer 144 and the passivation layer 150 interposed therebetween to form the storage capacitor 120.

A method of forming the gate insulating layer 144 according to the first embodiment of the present invention will be described with reference to FIGS. 8A to 8C.

The gate insulating layer 144 and the photoresist are entirely deposited on the lower substrate 142 on which the gate patterns are formed through a deposition method such as PECVD or sputtering. Then, the diffraction mask 180 including the blocking region 180a and the semi-transmissive region 180b is aligned on the photoresist 190, and an exposure process and a developing process are performed to thereby form a photoresist pattern as shown in FIG. 8A. 190a is formed.

In this case, the photoresist pattern 190a may have a thickness lower than that of the gate insulating layer 144 in the peripheral region of the storage capacitor 120. The gate insulating layer 144 of the region where the gate insulating layer 144 of the storage capacitor 120 is to be formed is relatively thin. It is formed to have.

Subsequently, the ashing process is performed to expose the gate insulating layer 144 to be included in the storage capacitor 120 by the remaining photoresist pattern 190b as shown in FIG. 8B. Thereafter, the exposed gate insulating layer 144 is etched (dry etched) using the remaining photoresist pattern 190b as a mask, so that the gate insulating layer 144 included in the storage capacitor 120 is illustrated in FIG. 8C. The storage capacitor 120 is formed to have a thickness relatively lower than the height of the gate insulating layer 144 in the peripheral region.

Here, the height of the gate insulating film 144 is adjusted by the etching time. Thereafter, the photoresist pattern 190b remaining by the strip process is removed.

In addition, a method of forming the protective film 150 according to the first embodiment of the present invention will be described with reference to FIGS. 9A to 9C.

The passivation layer 150 and the photoresist are entirely deposited on the lower substrate 142 on which the source / drain electrodes 110 and 112 and the semiconductor pattern 145 are formed through PECVD, sputtering, and the like. Then, the diffraction mask 182 including the transmission region 182a, the blocking region 182b, and the semi-transmissive region 182c is aligned, and then an exposure process and a developing process are performed, as shown in FIG. 9A. The resist pattern 192a is formed. Here, the photoresist pattern 192a exposes the passivation layer 150 of the region where the contact hole 116 is to be formed, and also surrounds the storage capacitor 120 in the region where the passivation layer 150 of the storage capacitor 120 is to be formed. It is formed to have a relatively lower height than the passivation layer 150 in the region.

Subsequently, the passivation layer 150 is patterned using the photoresist pattern 192a as a mask to form a contact hole 116 exposing the drain electrode 112. Thereafter, the ashing process is performed to expose the passivation layer 150 to be included in the storage capacitor 120 by the remaining photoresist pattern 192b as shown in FIG. 9B. Thereafter, the exposed protective film 150 is etched (drain etched) using the remaining photoresist pattern 192b as a mask to expose the drain electrode 112 as shown in FIG. 9C. In addition, the passivation layer 150 including the passivation layer 150 included in the storage capacitor 120 has a thickness lower than that of the passivation layer 150 in the peripheral region of the storage capacitor 120.

Here, the thickness of the remaining protective film 150 is controlled by the etching time. Thereafter, the remaining photoresist pattern 192b is removed by the strip process.

FIG. 10 is a cross-sectional view according to a second exemplary embodiment of the present invention taken along the line II-II ′ of FIG. 5.

Referring to FIG. 10, the thin film transistor substrate according to the second embodiment of the present invention has a structure in which the passivation layer 150 positioned between the front gate line 102 of the storage capacitor 120 and the pixel electrode 118 is removed. Have That is, the storage capacitor 120 of the thin film transistor according to the second embodiment of the present invention has a structure in which only the gate insulating layer 144 is positioned between the front gate line 102 and the pixel electrode 118 of the storage capacitor 120. Have                     

In addition, the gate insulating layer 144 positioned between the front gate line 102 of the storage capacitor 120 and the pixel electrode 118 is relatively larger than the gate insulating layer 144 in the peripheral region of the storage capacitor 120 using a diffraction mask. It is formed to have a low thickness.

As a result, the distance between the pixel electrode 118 and the gate line 102 becomes smaller, thereby increasing the capacitance Cst of the storage capacitor 120 and improving the image quality of the liquid crystal panel.

Hereinafter, a method of manufacturing a TFT substrate according to a second embodiment of the present invention will be described with reference to FIGS. 11A through 11C.

Here, the manufacturing method of the TFT substrate according to the second embodiment of the present invention is the same except for the process of forming a protective film in the manufacturing method of the TFT substrate according to the first embodiment of the present invention will not be described herein. .

After the passivation layer 150 is entirely formed on the lower substrate 142, the photoresist is entirely coated. Thereafter, after the mask 180 including the transmission region 180a and the blocking region 180b is aligned, a photolithography process is performed to form the photoresist pattern 190a as illustrated in FIG. 11A. Thereafter, the passivation layer 150 is patterned using the photoresist pattern 190a as a mask, thereby forming a contact hole 116 exposing the drain electrode 112 of the thin film transistor 106 as shown in FIG. 11B. In addition, the passivation layer 150 is formed in the region where the storage capacitor 120 is to be disposed to expose the gate insulating layer 144.                     

Subsequently, after the transparent electrode material is entirely deposited on the passivation layer 150 by a deposition method such as sputtering, the pixel electrode 118 is formed by patterning the transparent electrode material through a photolithography process and an etching process. The pixel electrode 118 is electrically connected to the drain electrode 112 through the contact hole 116. In addition, the pixel electrode 118 is formed to overlap the front gate line 12 with the gate insulating layer 144 interposed therebetween to form the storage capacitor 120.

As described above, the thin film transistor substrate and the method of manufacturing the same according to the present invention are formed such that the thickness of the gate insulating film and the protective film positioned between the gate line of the storage capacitor and the pixel electrode is lower than the thickness of the peripheral region of the storage capacitor. This can increase the capacity of the storage capacitor. In addition, by removing the passivation layer disposed between the gate line and the pixel electrode of the storage capacitor, only the gate insulating layer is provided between the gate line and the pixel electrode of the storage capacitor, thereby increasing the capacity of the storage capacitor and also the gate insulating layer of the storage capacitor. The capacitance of the storage capacitor may be further increased by forming the thickness of the storage capacitor to be lower than that of the gate insulating layer in the peripheral region of the storage capacitor.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A gate line and a data line crossing each other with the gate insulating layer interposed therebetween; A thin film transistor formed at an intersection of the gate line and the data line; A pixel electrode connected to the thin film transistor; A storage capacitor formed by the pixel electrode and the gate line positioned with the gate insulating layer interposed therebetween, The gate insulating film included in the storage capacitor has a thickness lower than that of the gate insulating film of the peripheral region of the storage capacitor. The method of claim 1, A passivation layer on the gate insulating layer and protecting the thin film transistor and the data line; The passivation layer disposed on the storage capacitor has a thickness lower than that of the passivation layer of the peripheral area of the storage capacitor. The method of claim 2, The passivation layer further includes a contact hole exposing a drain electrode of the thin film transistor, The pixel electrode is connected to the drain electrode of the thin film transistor through the contact hole. Forming a gate line; Forming a gate insulating film covering the gate line; Forming a data line crossing the gate line with the gate insulating layer interposed therebetween; Forming a thin film transistor at an intersection of the gate line and the data line; Forming a pixel electrode connected to the thin film transistor; Forming a storage capacitor including the pixel electrode and the gate line, having the gate insulating layer interposed therebetween, Forming the gate insulating film, And forming a thickness of the gate insulating layer included in the storage capacitor to have a thickness lower than that of the gate insulating layer in the peripheral region of the storage capacitor. The method of claim 4, wherein Forming the gate insulating film, Forming a photoresist pattern on the gate insulating layer, the photoresist pattern having a height lower than a peripheral area of the storage capacitor in a region of the storage capacitor using a diffraction mask; Etching the photoresist pattern to expose a gate insulating film in a formation region of the storage capacitor; Partially removing the exposed gate insulating layer using the ashed photoresist pattern as a mask; Removing the ashed photoresist pattern. The method of claim 5, wherein Forming a passivation layer on the gate insulating layer and included in the storage capacitor; Forming the passivation layer included in the storage capacitor, And forming a thickness of the passivation layer included in the storage capacitor to have a thickness lower than that of the passivation layer of the peripheral region of the storage capacitor. The method of claim 6, Forming the passivation layer included in the storage capacitor, And forming a contact hole exposing the drain electrode of the thin film transistor. The method of claim 7, wherein Forming the passivation layer included in the storage capacitor, Forming a photoresist pattern on the passivation layer using a diffraction mask, the photoresist pattern having a height lower than a peripheral region of the storage capacitor in a region of forming the storage capacitor; Patterning the passivation layer using the photoresist pattern as a mask to form the contact hole; Ashing the photoresist pattern to expose a protective film to be included in the storage capacitor; Partially removing the exposed passivation layer using the ashed photoresist pattern as a mask; Removing the ashed photoresist pattern. The method of claim 7, wherein The pixel electrode is connected to the drain electrode of the thin film transistor through the contact hole.

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