JPH0697298A - Forming method of semiconductor device insulating film - Google Patents

Abstract

PURPOSE:To provide a method of forming an interlayer insulating film used for insulating an upper wiring from a lower wiring of a semiconductor and flattening the surface, where a flattening coating material (SOG film) is lessened in base pattern dependency and set uniform in thickness on a wiring. CONSTITUTION:An insulating film is formed to cover an insulating layer 2 on a semiconductor substrate and wirings 3 and 4 formed on the insulating layer through such a method that ceramic filler whose grain diameter is half to 1.5 times as large as the thickness of the wirings is mixed into SOG film source solution 5, and the mixed solution concerned is applied for the formation of an insulating film. The mixed solution is applied by a spin coater or a roll coater, and ceramic filler is restrained from being located on the wirings 3 and 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming an interlayer insulating film for insulating and flattening a lower wiring and an upper wiring of a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device such as LSI or VLSI, a multi-layer wiring structure is used. An insulating film (interlayer insulation) not only maintains insulation between wirings but also smoothes and flattens uneven bases. The formation of the film) is important. In recent flattening technology, an SOG (Spin On Glass) film is often used for this insulating film. The SOG film is basically formed by applying a solution of SiO _x dissolved in a solvent onto a substrate by a spin coating method, drying it, and heating it to change it into silicon oxide.

[0003]

[Problems to be Solved by the Invention] However, SOG
Since the film is a coating film formed by spin coating, the film thickness varies depending on the density of the underlying wiring pattern. For example, various aluminum patterns (small patterns of 4 × 4 μm to 128 × 128) are previously formed on the insulating layer of the semiconductor substrate.
(large pattern of μm) is formed, general SOG is spin-coated on it, and heat-treated to measure the thickness of the SOG film on the pattern. It is obtained as shown in FIG.

Note that the underlying pattern dependency = film thickness on pattern / film thickness on flat plate × 100 [%] is illustrated in FIG. 2, in which a large pattern is formed on the insulating layer 2 on the semiconductor substrate 1. 3 and small pattern 4
The G film 5 covers it. And the SOG on the large pattern 3
The film is thicker than the SOG film on the small pattern 4.

As can be seen from FIGS. 1 and 2, the disadvantage is that the film thickness is unevenly formed on a wide pattern and thinly formed on an isolated narrow pattern. is there. Such a difference in the film thickness on the wiring due to the underlying pattern causes obstacles such as a focus depth in subsequent lithography, under-etching or over-etching in etching for forming a contact hole, and variation in interlayer capacitance.

When the thickness of the SOG film is increased in consideration of the high flatness, the underlying pattern dependency is further promoted and becomes large. Therefore, it is required to eliminate this dependency. Therefore, the following methods (1) to (4) can be considered as methods of reducing the dependency of the SOG film on the underlayer.

(1) A method in which, after the SOG film is formed, a thickened portion on a wide pattern is etched to minimize the difference in film thickness. (2) A method of arranging a dummy wiring pattern between wirings to eliminate the pattern density itself. (3) A method in which the coating film thickness is made thin to suppress the underlying pattern dependence.

(4) A method of suppressing fluidity by adding fine powder to the SOG solution. However, the methods (1) and (2) are effective, but the process becomes complicated. In particular, the method (2) causes a problem in wiring capacitance. The method (3) sacrifices the function of flattening and cannot be used in the case of a large step. The method (4) is effective for flattening, but has little effect on the underlying pattern dependency.

An object of the present invention is to provide an insulating film forming method capable of reducing the dependency of the flattening coating material (SOG film) on the underlying pattern and making the SOG film thickness on the wiring more uniform than the above method. It is to provide reliability, thereby improving reliability in interlayer capacitance, contact hole formation, focus depth in lithography, and the like.

[0010]

In the method of forming an insulating film for covering an insulating layer on a semiconductor substrate and a wiring formed on the insulating layer, the above-mentioned object is to provide a source solution of an SOG film with a wiring. Of a ceramic filler having a diameter not less than ½ and not more than 1.5 times the height of the same, and applying the mixed solution to form an insulating film. Achieved by

The mixed solution is applied by the spin coating method so that the ceramic filler does not exist on the wiring at that time, and therefore the ratio of the filler to the source solution of the SOG film in the mixed solution is 9: 1 to. It is preferably 7: 3. Further, it is preferable that the mixed solution is applied by using a roll coater so that the ceramic filler does not exist on the wiring.

Then, it is preferable to use silica or boron nitride as the ceramic filler.

[0013]

In the method according to the present invention, the SOG solution mixed with the ceramic filler is used, but the ceramic filler is arranged only in the recesses between the wirings and the ceramic filler is not present on the wirings. This ceramic filler is not only for flattening but also for S in small wiring patterns.
This contributes to forming the OG film thicker than before. Therefore, the diameter of the ceramic filler depends on the wiring height (step).
1/2 to 1.5 times, and if it is smaller than 1/2, the amount of SOG accumulated in the recesses is small and the flatness is deteriorated. On the other hand, if it is larger than 1.5 times, this filler is It causes a new step and also deteriorates the flatness.

The SOG solution mixed with the ceramic filler can be applied by a spin coating method. However, if the ratio of the ceramic filler and the SOG solution is not set appropriately, the filler will adhere to the wiring. Therefore, the range of 9: 1 to 7: 3 is preferable.
Further, the SOG solution mixed with the ceramic filler may be applied by using a roll coater while extruding the filler from above the wiring.

As the material of the ceramic filler, alumina, titania, silica, boron nitride, etc. can be used. However, considering compatibility with SOG solution and low dielectric constant, silica and boronite can be used. Ride is preferred. Further, boron nitride is desirable because it has good thermal conductivity and a lower dielectric constant.

[0016]

EXAMPLES The present invention will be described in detail below with reference to the accompanying drawings by way of example embodiments and comparative examples of the present invention. Example 1 (in the case of spin coating method) First, the source solution of SOG film (alcohol solution of hydrolyzate of alkoxysilane) and ceramic filler (ceramic filler manufactured from tetraethoxysilane)
And mix the filler with the source solution. The mixing ratio is shown in Table 1 below.

[0017]

[Table 1]

As a substrate for spin-coating the filler-mixed SOG solution, as shown in FIGS. 3 (a) to 3 (c), the silicon semiconductor substrate 1 is thermally oxidized according to a normal process to form an insulating layer (SiO ₂ layer) 2 And a large pattern 3 and a small pattern 4 of aluminum wiring formed thereon are prepared. While rotating the substrate, the filler-mixed SOG solution is dropped on the substrate. Since the rotation speed is low at the beginning of dropping, the filler 7 and the SOG solution 5 are applied to the entire surface, as shown in FIG. When the rotation speed is set to a predetermined value, the wiring pattern 3
The filler 7 is removed from above and 4 by centrifugal force.
Fillers 7 are SOG solution 5 in the recesses between the wiring patterns.
It remains with. Then, when the dropping is stopped and the rotation of the substrate is also stopped, as shown in FIG. 3C, only the SOG solution 5 remains on the wiring patterns 3 and 4, and the filler 7 and the SOG solution 5 remain between the wiring patterns. . And
SOG solution thickness on large pattern 3 and S on small pattern 4
It is almost equal to the OG solution thickness. Next, it is dried and heat-treated (400 to 700 ° C.) to form an SOG film. In this way, flattening of the interlayer insulating film and uniformity of the wiring pattern can be achieved.

In the case of FIGS. 3 (a) to 3 (c), the coating was performed according to the method according to the present invention, but when the ratio of the SOG solution becomes high (6: 4 or more), as shown in Table 1. In addition, the filler will be present on the wiring pattern. In such a state, the SOG film cannot be flattened. Example 2 (In the case of coating by a roll coater) The same substrate as in Example 1 is used, and a roller coater is used as a coating device instead of the spin coater. As shown in FIG. 4 (a), while the roll 9 is rotated, the filler-mixed SOG solution dropped on the front side of the roll is spread out, the filler 7 is pushed toward the front side of the roll 9, and the SOG solution 5 is formed on the rear side of the large pattern 3 Leave on. Between wiring patterns 3 and 4,
As shown in FIG. 3B, the filler 7 and the SOG solution 5 are embedded in the recess. Then, as shown in FIG. 3 (c), the filler 7 is present only in the recesses without any filler on the wiring pattern by rolling over the entire substrate, and S
Apply OG solution. Also in this case, S on the large pattern 3
The OG solution thickness and the SOG solution thickness on the small pattern 4 are almost equal. Next, it is dried and heat treated (400-
700 ° C.) to form an SOG film.
In this way, flattening of the interlayer insulating film and uniformity of the wiring pattern can be achieved.

[0020]

As described above, in the method of forming an interlayer insulating film (SOG film) according to the present invention, not only the ceramic filler is arranged only in the recesses between the wiring patterns to improve the flatness, It is possible to increase the SOG film thickness on the small (narrow) wiring pattern to about the SOG film thickness on the large (wide) pattern. Therefore, the dependency on the underlying pattern in the conventional coating / planarizing material is eliminated, and the interlayer insulating film (SOG film) having a substantially uniform thickness can be formed on the wiring regardless of the width (size) of the wiring. It is possible to stabilize the focus depth and contact hole formation in lithography. Further, a material having a low dielectric constant can be used for the ceramic filler, and the performance and reliability of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a graph showing the underlying pattern dependence of an SOG film.

FIG. 2 is a schematic sectional view of a semiconductor substrate having an SOG coating film formed by a conventional spin coating method.

3A is a schematic cross-sectional view of the semiconductor substrate at the beginning of dropping the filler-mixed SOG solution in the forming method according to the present invention, and FIG. 3B is a state in which the filler on the wiring pattern is blown by rotation. It is a schematic sectional drawing of a semiconductor substrate, (c) is a schematic sectional drawing of a semiconductor substrate which has an SOG film at the time of coating completion.

4A is a schematic cross-sectional view of a semiconductor substrate in a state where a filler on a wiring pattern is extruded by roll rotation from a filler-mixed SOG solution by a roll coater in the forming method according to the present invention, FIG. FIG. 3 is a schematic cross-sectional view of a semiconductor substrate in which a wiring pattern recess is filled with a filler and an SOG solution by roll rotation, and (c) is a schematic cross-sectional view of a semiconductor substrate having an SOG film at the end of coating.

[Explanation of symbols]

 1 ... Semiconductor substrate 2 ... Insulating layer 3 ... Large pattern 4 ... Small pattern 5 ... SOG solution 7 ... Filler 9 ... Roll

Claims (5)

[Claims] 1. A method of forming an insulating film covering an insulating layer on a semiconductor substrate and a wiring formed on the insulating layer, wherein a source solution of an SOG film has a half of the height of the wiring. From the above, a method for forming an insulating film of a semiconductor device, which comprises mixing a ceramic filler having a diameter of 1.5 times or less and applying the mixed solution to form an insulating film. 2. The method according to claim 1, wherein the mixed solution is applied by spin coating, and the ceramic filler is not present on the wiring. 3. The filler and SOG in the mixed solution
The method according to claim 2, wherein the ratio of the film to the source solution is 9: 1 to 7: 3. 4. The method according to claim 1, wherein the mixed solution is applied using a roll coater, and the ceramic filler is not present on the wiring. 5. The method according to claim 1, wherein silica or boron nitride is used as the ceramic filler.