JPH04214536A - Thin film transistor matrix - Google Patents
Thin film transistor matrixInfo
- Publication number
- JPH04214536A JPH04214536A JP2401495A JP40149590A JPH04214536A JP H04214536 A JPH04214536 A JP H04214536A JP 2401495 A JP2401495 A JP 2401495A JP 40149590 A JP40149590 A JP 40149590A JP H04214536 A JPH04214536 A JP H04214536A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- interlayer insulating
- intersection
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims description 13
- 239000010409 thin film Substances 0.000 title claims description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010408 film Substances 0.000 claims description 58
- 239000012212 insulator Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005530 etching Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は薄膜トランジスタマトリ
ックスに関する。近年，液晶ディスプレイ，エレクトロ
ルミネッセンス等の駆動素子として，薄膜トランジスタ
（以下，ＴＦＴと称する）マトリックスが使用されるよ
うになった。このようなＴＦＴマトリックスにおいては
，数十万箇のＴＦＴを無欠陥で作製する必要があり，製
造歩留りの向上が強く要望されている。FIELD OF THE INVENTION This invention relates to thin film transistor matrices. In recent years, thin film transistor (hereinafter referred to as TFT) matrices have come to be used as driving elements for liquid crystal displays, electroluminescence, and the like. In such a TFT matrix, it is necessary to fabricate hundreds of thousands of TFTs without defects, and there is a strong demand for improvement in manufacturing yield.
【０００２】0002
【従来の技術】図４（ａ）， （ｂ）はＴＦＴマトリ
ックスの従来例を説明するための図で，ＴＦＴマトリッ
クスの交叉部とそこに接続する１箇のＴＦＴを示し，（
ａ） は上面図，（ｂ） はＡ−Ａ断面図であり，１は
基板，２Ａはゲートバス，３Ａはドレインバス，４はゲ
ート絶縁膜，５は層間絶縁膜，６はゲート電極，７はソ
ース電極，８はドレイン電極，９はチャネル保護膜を表
す。[Prior Art] FIGS. 4(a) and 4(b) are diagrams for explaining conventional examples of TFT matrices, showing a crossing part of the TFT matrix and one TFT connected thereto.
a) is a top view, (b) is a sectional view taken along line A-A, where 1 is a substrate, 2A is a gate bus, 3A is a drain bus, 4 is a gate insulating film, 5 is an interlayer insulating film, 6 is a gate electrode, and 7 8 represents a source electrode, 8 represents a drain electrode, and 9 represents a channel protective film.
【０００３】まず基板１上にゲートバス２Ａとゲート電
極６が形成される。ゲート絶縁膜４を介して活性層とな
る非晶質Ｓｉ層，ソース電極７，ドレイン電極８，チャ
ネル保護膜９が形成される。ドレイン電極８に接続する
ドレインバス３Ａとの交叉部になるゲートバス２Ａの部
分を覆う層間絶縁膜５が形成される。First, a gate bus 2A and a gate electrode 6 are formed on a substrate 1. An amorphous Si layer serving as an active layer, a source electrode 7, a drain electrode 8, and a channel protection film 9 are formed with a gate insulating film 4 interposed therebetween. An interlayer insulating film 5 is formed to cover a portion of the gate bus 2A that intersects with the drain bus 3A connected to the drain electrode 8.
【０００４】ドレインバス３Ａは，次のようにして形成
される。全面に導電膜を形成し，その導電膜をマスクを
用いてエッチングし，ドレインバス３Ａの形状に加工す
る。
エッチングは通常ウエットエッチングで行う。The drain bus 3A is formed as follows. A conductive film is formed on the entire surface, and the conductive film is etched using a mask to form the shape of the drain bus 3A. Etching is usually performed by wet etching.
【０００５】ところが，この時，導電膜と層間絶縁膜５
との段差部からエッチング液がしみこんで，エッジに沿
ってエッチングが進行し，ドレインバス３Ａが切断され
てしまうことがある。However, at this time, the conductive film and the interlayer insulating film 5
The etching solution may seep in from the step between the drain bus 3A and the etching progresses along the edge, resulting in the drain bus 3A being cut.
【０００６】このような事故の生じる確率は必ずしも高
くはないが，数十万箇のＴＦＴを含むＴＦＴマトリック
スの製造においては歩留り低下の一要因となっていた。[0006] Although the probability of such an accident occurring is not necessarily high, it has been a factor in reducing yield in the manufacture of TFT matrices containing hundreds of thousands of TFTs.
【０００７】[0007]
【発明が解決しようとする課題】本発明は上記の問題に
鑑み，たとえ導電膜と層間絶縁膜の段差部からエッチン
グ液がしみこんだとしても断線に到らない構造を有する
ＴＦＴマトリックスを提供することを目的とする。SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a TFT matrix having a structure that does not lead to disconnection even if an etching solution seeps into the step between the conductive film and the interlayer insulating film. With the goal.
【０００８】[0008]
図１（ａ）， （ｂ）は，本発明の原理を説明するため
の図である。上記課題は，基板１上に形成された帯状の
第１の配線２Ａと， それに直交する帯状の第２の配線
３Ａと， 該第１の配線２Ａと該第２の配線３Ａの交叉
部に形成された層間絶縁膜５とを有し，該交叉部におい
て該基板１上に第１の配線２Ａ，層間絶縁膜５，第２の
配線３Ａの順に積層され，該層間絶縁膜５は該交叉部を
含み且つ該第２の配線３Ａ下に延びる凸状の突起を有す
るＴＦＴマトリックスによって解決される。FIGS. 1(a) and 1(b) are diagrams for explaining the principle of the present invention. The above problem is caused by a first strip-shaped wiring 2A formed on the substrate 1, a second strip-shaped wiring 3A perpendicular to the strip-shaped first wiring 2A formed on the substrate 1, and a strip-shaped second wiring 3A formed at the intersection of the first wiring 2A and the second wiring 3A. The first interconnect 2A, the interlayer insulating film 5, and the second interconnect 3A are laminated in this order on the substrate 1 at the intersection, and the interlayer insulating film 5 is formed at the intersection. The problem is solved by a TFT matrix having a convex projection extending below the second wiring 3A.
【０００９】また，基板１上に形成された互いに平行な
第１の配線群２Ａ， ２Ｂと， それに直交する第２の
配線群３Ａ， ３Ｂと， 該第１の配線群２Ａ， ２Ｂ
と該第２の配線群３Ａ， ３Ｂの交叉部に形成された層
間絶縁膜５とを有し，該交叉部において該基板１上に第
１の配線群２Ａ， ２Ｂ，層間絶縁膜５，第２の配線群
３Ａ， ３Ｂの順に積層され，該層間絶縁膜５は該交叉
部を含み且つ該第２の配線群３Ａ， ３Ｂ下に延びて隣
の交叉部の層間絶縁膜に連結し，該交叉部間の層間絶縁
膜５は該第２の配線群３Ａ， ３Ｂで覆われているＴＦ
Ｔマトリックスによって解決される。[0009] Furthermore, a first wiring group 2A, 2B parallel to each other formed on the substrate 1, a second wiring group 3A, 3B orthogonal thereto, and the first wiring group 2A, 2B.
and an interlayer insulating film 5 formed at the intersection of the second wiring groups 3A and 3B, and the first wiring groups 2A and 2B, the interlayer insulating film 5, and the interlayer insulating film 5 formed on the substrate 1 at the intersection. The second wiring groups 3A and 3B are stacked in this order, and the interlayer insulating film 5 includes the crossing portion and extends below the second wiring group 3A and 3B to connect to the interlayer insulation film of the adjacent crossing portion. The interlayer insulating film 5 between the intersections is a TF covered with the second wiring group 3A, 3B.
Solved by T matrix.
【００１０】また，前記第１の配線或いは配線群２Ａ，
２Ｂ及び前記第２の配線或いは配線群３Ａ， ３Ｂが
，それぞれ，ＴＦＴマトリックスのゲートバス及びドレ
インバスであるＴＦＴマトリックスによって解決される
。[0010] Also, the first wiring or wiring group 2A,
2B and the second wiring or wiring groups 3A and 3B are solved by a TFT matrix, which is a gate bus and a drain bus of the TFT matrix, respectively.
【００１１】[0011]
【作用】第１の配線２Ａと該第２の配線３Ａの交叉部に
形成される層間絶縁膜５を第２の配線３Ａ下に延びる凸
状の突起を持つように（図１（ａ） ）形成すれば，層
間絶縁膜５と第２の配線３Ａとの段差部におけるエッジ
の総延長が長くなる。したがって，段差部の端からエッ
チング液がしみこんでエッチングが進行したとしても，
第２の配線のエッチング加工が終了するまでに第２の配
線が断線に到る確率を従来よりも低下させることができ
る。[Operation] The interlayer insulating film 5 formed at the intersection of the first wiring 2A and the second wiring 3A has a convex projection extending below the second wiring 3A (FIG. 1(a)). If formed, the total length of the edge at the stepped portion between the interlayer insulating film 5 and the second wiring 3A becomes longer. Therefore, even if the etching solution seeps in from the edge of the step and etching progresses,
The probability that the second wiring will be disconnected before the etching process for the second wiring is completed can be reduced compared to the conventional method.
【００１２】さらに，第２の配線３Ａ下に延びる層間絶
縁膜の凸状の突起をさらに延ばして，隣の交叉部の層間
絶縁膜と連結するように（図１（ｂ） ）すれば，第２
の配線が断線に到る確率はさらに減少する。この時，交
叉部間の層間絶縁膜は第２の配線で覆われているから，
第２の配線の幅は層間絶縁膜の幅より大きく，交叉部間
で基板１上に形成された素子と接続することが可能とな
る。Furthermore, if the convex protrusion of the interlayer insulating film extending below the second wiring 3A is further extended and connected to the interlayer insulating film at the adjacent intersection (FIG. 1(b)), the 2
The probability that the wiring will break is further reduced. At this time, since the interlayer insulating film between the intersections is covered with the second wiring,
The width of the second wiring is larger than the width of the interlayer insulating film, and it is possible to connect to the elements formed on the substrate 1 between the crossing parts.
【００１３】また，上述の層間絶縁膜の構造を採用すれ
ば，ＴＦＴマトリックスの製造歩留りを向上させること
ができる。Furthermore, by employing the above-described structure of the interlayer insulating film, the manufacturing yield of the TFT matrix can be improved.
【００１４】[0014]
【実施例】図２（ａ）， （ｂ）は第１の実施例を説明
するための図で，（ａ） は上面図，（ｂ）は断面図を
示す。製造工程の概略は次の如くである。Embodiment FIGS. 2(a) and 2(b) are diagrams for explaining the first embodiment, in which (a) shows a top view and (b) shows a sectional view. The outline of the manufacturing process is as follows.
【００１５】基板１としてガラス基板を用い，その上に
幅が例えば２０μｍ，厚さが例えば３０００ÅのＡｌの
ゲートバス２Ａと， 幅が例えば５０００Å，厚さが例
えば８００ ÅのＴｉのゲート電極６を形成する。A glass substrate is used as the substrate 1, and thereon an Al gate bus 2A having a width of, for example, 20 μm and a thickness of, for example, 3000 Å, and a Ti gate electrode 6 having a width of, for example, 5000 Å and a thickness of, for example, 800 Å are provided. Form.
【００１６】次に，厚さが例えば３０００Åのゲート絶
縁膜を形成し， その上に活性層として厚さが例えば１
５０ Åの非晶質Ｓｉ膜， チャネル保護膜９として厚
さが例えば１４００ÅのＳｉＯ２ 膜を形成する。ゲー
ト電極６をマスクにして，チャネル保護膜９をセルフア
ラインでパターニングした後，チャネル保護膜９の両側
の非晶質Ｓｉ膜上にソース電極７，ドレイン電極８を形
成する。Next, a gate insulating film with a thickness of, for example, 3000 Å is formed, and an active layer with a thickness of, for example, 1 Å is formed on it.
An amorphous Si film with a thickness of 50 Å and a SiO2 film with a thickness of 1400 Å, for example, are formed as the channel protective film 9. After patterning the channel protection film 9 by self-alignment using the gate electrode 6 as a mask, a source electrode 7 and a drain electrode 8 are formed on the amorphous Si film on both sides of the channel protection film 9.
【００１７】ドレイン電極８上にゲートバス２Ａと直交
するドレインバス３Ａを形成するのであるが，その前に
ドレインバス３Ａと交叉するゲートバス２Ａ上に，厚さ
が１μｍ程度のＳｉＯ２ の層間絶縁膜５を形成する。
層間絶縁膜５はゲートバス２Ａとドレインバス３Ａの交
叉部を覆い，さらにドレインバス３Ａの下に延びる凸状
に形成する。層間絶縁膜５が交叉部を覆いゲートバス２
Ａの方向に延びる方向の幅はゲートバス２Ａの幅より広
く，例えば３０μｍとし，ドレインバス３Ａの下に凸状
に延びる方向の幅はドレインバス３Ａの幅より狭く，例
えば１０μｍとし，ドレインバス３Ａの下に例えば３０
μｍほど突き出るように形成する。A drain bus 3A that intersects with the gate bus 2A is formed on the drain electrode 8, but before that, an interlayer insulating film of SiO2 with a thickness of about 1 μm is formed on the gate bus 2A that intersects with the drain bus 3A. form 5. The interlayer insulating film 5 covers the intersection of the gate bus 2A and the drain bus 3A, and is formed in a convex shape extending below the drain bus 3A. An interlayer insulating film 5 covers the intersection and gate bus 2.
The width in the direction extending in the direction A is wider than the width of the gate bus 2A, for example 30 μm, and the width in the direction extending convexly below the drain bus 3A is narrower than the width of the drain bus 3A, for example 10 μm. For example, under 30
It is formed to protrude by about μm.
【００１８】全面に厚さが例えば６０００ÅのＡｌ膜を
形成し，マスクを用いてＡｌ膜をエッチングして幅２０
μｍのドレインバス３Ａを形成する。エッチング液とし
ては，例えば硝酸と燐酸と酢酸の水溶液を用いる。ドレ
インバス３Ａはゲートバス２Ａと直交し，先に形成した
層間絶縁膜５により，ゲートバス２Ａと絶縁される。An Al film having a thickness of, for example, 6000 Å is formed on the entire surface, and the Al film is etched using a mask to form a width of 20 Å.
A drain bus 3A of μm is formed. As the etching solution, for example, an aqueous solution of nitric acid, phosphoric acid, and acetic acid is used. The drain bus 3A is orthogonal to the gate bus 2A, and is insulated from the gate bus 2A by the interlayer insulating film 5 formed previously.
【００１９】ドレインバス３Ａに断線は見られなかった
。
図３（ａ）， （ｂ）は第２の実施例を説明するための
図で，（ａ） は上面図，（ｂ）は断面図を示し，１は
基板，２Ａ， ２Ｂはゲートバス，３Ａ はドレインバ
ス， ４はゲート絶縁膜，５は層間絶縁膜，６はゲート
電極，７はソース電極，８はドレイン電極，９はチャネ
ル保護層を表す。No disconnection was found in the drain bus 3A. 3(a) and (b) are diagrams for explaining the second embodiment, in which (a) is a top view and (b) is a cross-sectional view, 1 is a substrate, 2A, 2B are gate buses, 3A is a drain bus, 4 is a gate insulating film, 5 is an interlayer insulating film, 6 is a gate electrode, 7 is a source electrode, 8 is a drain electrode, and 9 is a channel protective layer.
【００２０】製造工程は層間絶縁膜５の形成以外は第１
の実施例と同じである。層間絶縁膜５は幅２０μｍのド
レインバス３Ａの下を幅１０μｍでもって延びており，
隣の層間絶縁膜に連結するように形成する。ドレインバ
ス３Ａは層間絶縁膜５を覆い，両側の部分でドレイン電
極８に接続する。The manufacturing process is the first step except for the formation of the interlayer insulating film 5.
This is the same as the embodiment. The interlayer insulating film 5 extends under the drain bus 3A having a width of 20 μm and has a width of 10 μm.
It is formed so as to be connected to the adjacent interlayer insulating film. The drain bus 3A covers the interlayer insulating film 5 and is connected to the drain electrode 8 on both sides.
【００２１】この場合もＡｌ膜をエッチング加工してド
レインバス３Ａを形成する時，ドレインバス３Ａに断線
は見られなかった。In this case as well, when the drain bus 3A was formed by etching the Al film, no disconnection was observed in the drain bus 3A.
【００２２】[0022]
【発明の効果】以上説明したように，下層配線と上層配
線の交叉部に形成する層間絶縁膜の形状を本発明のよう
にすれば，上層配線を形成するときの断線を防ぐことが
できる。本発明はＴＦＴマトリックスの製造歩留りを顕
著に向上するという効果を奏するものである。As explained above, if the shape of the interlayer insulating film formed at the intersection of the lower layer wiring and the upper layer wiring is as in the present invention, disconnection when forming the upper layer wiring can be prevented. The present invention has the effect of significantly improving the manufacturing yield of TFT matrices.
【図１】本発明の原理を説明するための図である。FIG. 1 is a diagram for explaining the principle of the present invention.
【図２】第１の実施例を説明するための図で，（ａ）
は上面図，（ｂ）はＡ−Ａ断面図である。[Fig. 2] A diagram for explaining the first embodiment, (a)
is a top view, and (b) is a sectional view taken along line A-A.
【図３】第２の実施例を説明するための図で，（ａ）
は上面図，（ｂ）はＡ−Ａ断面図である。[Fig. 3] A diagram for explaining the second embodiment, (a)
is a top view, and (b) is a sectional view taken along line A-A.
【図４】従来例を説明するための図で，（ａ） は上面
図，（ｂ） はＡ−Ａ断面図である。FIG. 4 is a diagram for explaining a conventional example, in which (a) is a top view and (b) is a sectional view taken along line A-A.
１は基板であってガラス基板
２Ａ， ２Ｂは第１の電極であってゲートバス３Ａ，
３Ｂは第２の電極であってドレインバス４はゲート絶縁
膜
５は層間絶縁膜
６はゲート電極
７はソース電極
８はドレイン電極
９はチャネル保護膜1 is a substrate, which is a glass substrate 2A, 2B is a first electrode, which is a gate bus 3A,
3B is a second electrode, a drain bus 4, a gate insulating film 5, an interlayer insulating film 6, a gate electrode 7, a source electrode 8, a drain electrode 9, a channel protective film.
Claims (3)
１の配線（２Ａ）と， それに直交する帯状の第２の配
線（３Ａ）と， 該第１の配線（２Ａ）と該第２の配線
（３Ａ）の交叉部に形成された層間絶縁膜（５） とを
有し，該交叉部において該基板（１） 上に第１の配線
（２Ａ），層間絶縁膜（５） ，第２の配線（３Ａ）の
順に積層され，該層間絶縁膜（５） は該交叉部を含み
且つ該第２の配線（３Ａ）下に延びる凸状の突起を有す
ることを特徴とする薄膜トランジスタマトリックス。[Claim 1] A first strip-shaped wiring (2A) formed on a substrate (1), a second strip-shaped wiring (3A) perpendicular to the first wiring (2A), and a first wiring (2A) and a second wiring (3A) formed on a substrate (1). an interlayer insulating film (5) formed at the intersection of the second wiring (3A), and a first wiring (2A), an interlayer insulating film (5), The thin film transistor matrix is characterized in that the interlayer insulating film (5) has a convex projection that includes the intersection and extends below the second wiring (3A). .
行な第１の配線群（２Ａ， ２Ｂ）と， それに直交す
る第２の配線群（３Ａ， ３Ｂ）と， 該第１の配線群
（２Ａ， ２Ｂ）と該第２の配線群（３Ａ， ３Ｂ）の
交叉部に形成された層間絶縁膜（５） とを有し，該交
叉部において該基板（１） 上に第１の配線群（２Ａ，
２Ｂ），層間絶縁膜（５） ，第２の配線群（３Ａ，
３Ｂ）の順に積層され，該層間絶縁膜（５） は該交
叉部を含み且つ該第２の配線群（３Ａ， ３Ｂ）下に延
びて隣の交叉部の層間絶縁膜に連結し，該交叉部間の層
間絶縁膜（５） は該第２の配線群（３Ａ， ３Ｂ）で
覆われていることを特徴とする薄膜トランジスタマトリ
ックス。[Claim 2] A first wiring group (2A, 2B) parallel to each other formed on a substrate (1), a second wiring group (3A, 3B) orthogonal thereto, and the first wiring group. (2A, 2B) and an interlayer insulating film (5) formed at the intersection of the second wiring group (3A, 3B), and a first wiring on the substrate (1) at the intersection. Group (2A,
2B), interlayer insulating film (5), second wiring group (3A,
3B), and the interlayer insulating film (5) includes the intersection, extends below the second wiring group (3A, 3B), and connects to the interlayer insulator of the adjacent intersection. A thin film transistor matrix characterized in that an interlayer insulating film (5) between the parts is covered with the second wiring group (3A, 3B).
２Ｂ）及び前記第２の配線或いは配線群（３Ａ， ３
Ｂ）が，それぞれ，薄膜トランジスタマトリックスのゲ
ートバス及びドレインバスであることを特徴とする請求
項１或いは請求項２記載の薄膜トランジスタマトリック
ス。3. The first wiring or wiring group (2A,
2B) and the second wiring or wiring group (3A, 3
3. The thin film transistor matrix according to claim 1 or claim 2, wherein B) are respectively a gate bus and a drain bus of the thin film transistor matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40149590A JP2871101B2 (en) | 1990-12-12 | 1990-12-12 | Thin film transistor matrix |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40149590A JP2871101B2 (en) | 1990-12-12 | 1990-12-12 | Thin film transistor matrix |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04214536A true JPH04214536A (en) | 1992-08-05 |
| JP2871101B2 JP2871101B2 (en) | 1999-03-17 |
Family
ID=18511320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40149590A Expired - Lifetime JP2871101B2 (en) | 1990-12-12 | 1990-12-12 | Thin film transistor matrix |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871101B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006215086A (en) * | 2005-02-01 | 2006-08-17 | Sharp Corp | Active matrix substrate and display device equipped with the same |
| US7795796B2 (en) | 2005-01-18 | 2010-09-14 | Seiko Epson Corporation | Wiring substrate, electro optic device and electronic equipment |
| US8878175B2 (en) | 2008-12-25 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-12-12 JP JP40149590A patent/JP2871101B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7795796B2 (en) | 2005-01-18 | 2010-09-14 | Seiko Epson Corporation | Wiring substrate, electro optic device and electronic equipment |
| JP2006215086A (en) * | 2005-02-01 | 2006-08-17 | Sharp Corp | Active matrix substrate and display device equipped with the same |
| US8878175B2 (en) | 2008-12-25 | 2014-11-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US9768280B2 (en) | 2008-12-25 | 2017-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US10483290B2 (en) | 2008-12-25 | 2019-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US10720451B2 (en) | 2008-12-25 | 2020-07-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US11158654B2 (en) | 2008-12-25 | 2021-10-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US11996416B2 (en) | 2008-12-25 | 2024-05-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2871101B2 (en) | 1999-03-17 |
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