JP2570255B2 - Thin film transistor matrix array panel and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor matrix array panel used for an active matrix liquid crystal display device and the like, and a method of manufacturing the same.

[Conventional technology]

A thin film transistor (TFT) has an advantage that it can be formed on an insulating substrate such as glass at a low temperature, and various device applications are considered. In particular, in recent years, TFTs using amorphous silicon (a-Si) or polysilicon (p-Si) are formed in a matrix array and are often used as switching arrays of liquid crystal display elements.

FIG. 4 (a) shows a schematic plan view of a part of a matrix array panel using an a-Si TFT, and FIG. 4 (b)
FIG. 3A is a schematic cross-sectional view taken along the line AA ′ of FIG.

Conventionally, an a-Si TFT matrix array panel has been created and configured as follows. That is, in FIGS. 4 (a) and 4 (b), a wiring metal such as chromium is deposited on an insulating substrate 401 such as glass, and is patterned to form a gate electrode 402. Next, a gate insulating film 403 such as silicon nitride (SiN) and an a-Si semiconductor film 404 are formed on the substrate 401 on which the gate electrode 402 is formed by plasma CVD.
Are sequentially deposited. The a-Si film has two layers in which an n ⁺ layer (n ⁺ semiconductor layer 405) is provided on a non-doped layer. The n ⁺ semiconductor layer 405 is provided for improving the ohmic contact with the source / drain electrodes, and may not be provided. Next, in order to form the TFTs into a matrix, the deposited semiconductor film 404 is masked, etched away, and planarly insulated and separated at each location where the TFTs are provided. As a result, the gate insulating film 403 remains in the deposited region, but the region where the semiconductor film 404 exists is the semiconductor region 413 where the TFT 412 is to be formed. Note that an etching residue 415 may occur at the end of the deposited region due to a mask pattern. In addition, if the semiconductor region 413 is expanded to the point where the gate electrode 402 and the drain bus line 416 intersect, the inter-electrode insulation can be improved. As a next step, a metal 406 for drain electrode wiring is deposited, and patterning for forming a source electrode 410, a drain electrode 408, and a drain bus line 416 is performed. Next, an indium tin oxide film (ITO
A conductive film such as a film 407 is deposited to be the display electrode 411, and patterning is performed so that the matrix-shaped display electrode 411 is connected to the source electrode 410 of the TFT 412. The TFT matrix array panel produced through the above steps has a sectional structure as shown in FIG. 4 (b).

[Problems to be solved by the invention]

However, the TFT matrix array panel having the structure and the manufacturing method as described above has a drawback that the manufacturing process is complicated and requires a lot of man-hours, and has a drawback that a line defect in display due to disconnection of wiring is likely to occur due to the structure. These drawbacks are due to the drawback of increasing the number of steps for patterning each thin film one by one and the drawback of separating and insulating the semiconductor film in a planar manner because the TFTs are arranged in a matrix array. there were.

In the structure of the conventional TFT matrix array panel as described above, at least an etching step using a mask pattern for forming a gate electrode, an etching step using a mask pattern for isolating and insulating a semiconductor in a plane, and an etching step using a mask pattern for wiring a drain electrode An etching process using a mask pattern for forming a display electrode, an etching process using a mask pattern for forming a transistor channel portion, and patterning (masking process) 5 to 6 times are required. Was a factor of high. In addition, one drain bus line must be connected to each of the semiconductor film steps of the number of TFTs provided separately in a plane, and there is a problem that the wiring is liable to be cut. When such a TFT matrix array panel is used as a display device, a disconnection of a wiring appears as a line defect of a display, resulting in an extremely low display quality.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor matrix array panel having a small number of manufacturing steps and a high manufacturing yield, and a method of manufacturing the same.

[Means for solving the problem]

According to a first aspect of the present invention for solving the above-mentioned problems, a plurality of gate electrode wirings and drain electrode wirings are insulated from each other and arranged in a matrix array on an insulating substrate,
In a panel in which thin film transistors are arranged in the vicinity of the intersection of the two wires, all of the deposited semiconductor film region under one drain electrode wire and the semiconductors of all thin film transistors connected to the one drain electrode wire The film is provided integrally in common without being insulated and separated in a plane. The electrode wiring is composed of two layers of a metal film and a transparent conductive film, and the transparent conductive film on the source electrode wiring extends to form a display electrode. A thin film transistor matrix array panel characterized in that:

In order to solve the above-mentioned problem, a method provided by the second invention is to provide a plurality of gate electrode wirings and drain electrode wirings in a matrix form insulated from each other, and to provide a thin film transistor near an intersection of the two wirings. A step of sequentially laminating and depositing a three-layer film of a gate insulating film, a semiconductor film, and a metal film for wiring on a surface of the insulating substrate on which the gate electrode wiring is formed; and a drain electrode wiring region and a source electrode region. Using a mask including: a metal film for a wiring and a semiconductor film over a region where all thin film transistors to be connected to one drain electrode wiring are provided and a region under the wiring where the lamination is deposited; A step of sequentially removing the layer film by etching; and, after depositing a wiring film of the display electrode, forming a wiring pattern of the display electrode and separating the source electrode and the drain electrode. The wiring film of the display electrode is etched using a single mask having a channel pattern of the thin film transistor, and the drain electrode wiring metal film of the channel portion is partially etched with an unnecessary film such as a doped layer of a semiconductor film. 3
And a step of etching a layer film.

In the laser panel, the above means does not affect the characteristics between the individual thin film transistors due to the leakage current from the gate because the gate insulating film is left entirely.

Further, in the thin film transistor matrix array panel of the present invention, the semiconductor film is commonly present in the drain electrode wiring region without being separated by the above means, so that a step corresponding to the number of elements is reduced and the drain electrode wiring is significantly reduced. It is flattened, and the defect rate due to disconnection can be greatly improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Example 1) FIG. 1A is a schematic plan view of a part of a TFT matrix array panel showing a configuration of an example of the present invention, and FIG.
FIG. 2 is a schematic cross-sectional view taken along line AA ′ of FIG.

1 (a) and 1 (b), a gate electrode 102 of Cr is formed on an insulating substrate 101 of soda glass coated with SiO.
Are provided by patterning. SiN gate insulating films 103 and i formed thereon by using plasma CVD.
-Si: H semiconductor film 1 composed of a layer and an n ⁺ (semiconductor) layer 105
04 is provided. Furthermore, a drain electrode 10
8. A Cr wiring metal 106 for the source electrode 110 is provided. The Cr wiring metal 106 is also formed on the insulating substrate 101 in a region where the semiconductor film 104 is not provided, and the drain electrode 108
Are also provided continuously as a drain terminal electrode 109 on an extension of the above. The semiconductor film other than the region serving as the TFT 112 and the semiconductor region 113 including the drain electrode wiring region (the region indicated by the broken line in the drawing) is etched away. Cr wiring metal
An ITO film 107 is provided on 106 and on a gate insulating film 103 of SiN remaining in a region to become the display electrode 111, and a desired pattern is formed. The pattern of the ITO film 107 is such that the source electrode 110 of the display electrode 111 and the TFT 112 are connected, and the drain electrode 108 and the drain terminal electrode 109 are continuous.
The channel portion of T112 has a gap between the source electrode 110 and the drain electrode. In addition, the ITO film 107, the Cr wiring metal 106, and the n ⁺ semiconductor layer 105 are removed from the channel portion of the TFT 112, and the TFT 112 becomes the semiconductor film 104 with the i-layer exposed.

As a result of measuring the characteristics of the individual TFTs of the TFT matrix array panel of the present invention having the above-described structure, it was confirmed that there was no influence between the TFTs in the matrix and that the TFTs could be operated for each display electrode. . This is because the insulating film that remains with the gate insulating film
Because it covers the gate electrode and gate wiring of the TFT,
The effect of preventing leakage current from the gate to the source and drain and the positional correlation between the gate electrode and TFT for TFT switching operation show that the semiconductor film is separated from the TFT on the gate electrode wiring. Thus, the TFT on the drain electrode wiring had the effect that the gate electrode was independent. The display result of the liquid crystal display using this TFT matrix array panel was almost the same as that of the insulation separation method in which all TFTs were isolated in a matrix. This is a so-called line-sequential system in which a display timing signal is sequentially input to each gate line in a liquid crystal display, and switching is performed.Therefore, even if a TFT is commonly provided in the drain direction, the switching timing is different, so there is no problem at all. Absent.

As described above, the TFT matrix array panel according to the present embodiment, in which equivalent operations can be obtained without completely isolating and separating individual TFTs in the matrix array, has the following advantages. First, there is no need for a mask and a patterning step for individually providing TFTs in an isolated island shape by insulating and isolating them, so that manufacturing costs can be reduced accordingly.
In addition, it is not necessary to perform drain electrode wiring on an isolated island-shaped TFT, and since the semiconductor film under one drain electrode wiring is continuous, there are few steps and the disconnection of the wiring is remarkably reduced. Improvement can be achieved.

(Example 2) FIGS. 2 (a) to 2 (d) are schematic cross-sectional views of a part of a TFT matrix array panel in a manufacturing process thereof, and FIGS. 3 (a) to 3 (d) are views in the process. It is a schematic plan view of a part of panel. 2 (a) to (d) are opposed to each other, and FIG.
-A 'illustrates a cross section taken along the breaking line.

2A and 3A, Cr for the gate electrodes 202 and 302 is deposited on an insulating substrate 201 made of glass or the like at a thickness of 1000 [deg.] And patterning is performed [step (a)]. Thereafter, in FIG. 2 (b) and FIG. 3 (b), the plasma CV
Using D, 3000N of SiN for the gate insulating film 203 is deposited, and a-Si: H i for the semiconductor film 204 is continuously formed in the same apparatus.
Layer 300Å and n ⁺ and phosphorus-doped into the semiconductor layer a-Si: H layer 5
Then, two layers of a gate insulating layer and a semiconductor layer (i-layer and n + are both semiconductor layers) are deposited [step (b)]. The surface is formed of n ⁺ semiconductor layers 205 and 305 in the plasma CVD stacked deposition region 314 of the gate insulating film and the semiconductor film and the n ⁺ layer.
The area which is the surface and becomes a terminal portion around the insulating substrate is the substrate surface. Next, in FIG. 2C and FIG. 3C, a wiring metal 20 for a drain electrode is formed on this surface in a separate step.
2000 6, of Cr, which becomes 6,306, is deposited.
Three layers are deposited on the entire surface together with the semiconductor film, and also includes a TFT region in which the drain electrode wiring and the drain electrode terminal are continuous and the drain electrode and the source electrode are continuous as shown in FIG. 3 (c). Cr is etched using such a mask pattern (hatched portion) of the wiring metals 206 and 306. N of the a-Si: H film of the semiconductor film 204 deposited by plasma CVD [step (b)] using the same mask pattern.
⁺ (Semiconductor) layers 205 and 305 and the i layer are removed by etching [step (c)]. As a result, the semiconductor film in which the a-Si: H film (the n ⁺ layer + the i layer) remains in the gate insulating film and the semiconductor film deposited by the plasma CVD [step (b)] and the n ⁺ layer laminated deposition region 314 Region 313 is the same as Cr wiring metal 306,
This is a hatched area in FIG. 2 (d) and 3 (d), ITO films 207 and 307 are deposited on this surface as a conductive film for the display electrode 311, and a pattern as shown in FIG. 3 (d), that is, The display electrode 311 and the source electrode 310 are continuous, and the drain electrode 308 and the drain terminal electrode
309 are continuous and the channel portions of the TFT 312 are separated, and the ITO films 207 and 307 are etched. Subsequently, using one mask, the wiring metal 306 existing in the channel portion of the TFT 312 is formed.
A-Si: H of n ⁺ (semiconductor) layer 305 of Cr film and semiconductor film 304
Unnecessary films such as the n + layer are etched, and a total of three layers including ITO are continuously removed by etching. Even when there is no n ⁺ layer, it is desirable to etch the interface between the metal film and the semiconductor in order to prevent leakage of transistor OFF characteristics. [Step (d)]. In these etching steps, the etchant of ITO and the etchant of Cr and the etchant of the a-Si: H film or their etching gas have a sufficient selectivity with respect to SiN.
It remains in all areas deposited by VD. In the TFT 312 region, the i-layer of the a-Si: H film of the semiconductor film 304 is exposed in the channel portion.

As described above, in the case of this embodiment, basically, the patterning step (a) of the gate electrode, the patterning step (c) in which the drain electrode and the TFT are integrated, and the surface electrode and the TF
Only three masking steps in the T-channel patterning step (d) are required, and a mask in the conventional TFT matrix separation step becomes unnecessary, resulting in a remarkable reduction in man-hour and manufacturing cost.

Furthermore, although the ITO film on the drain electrode is essentially unnecessary, the use of the above-described mask allows the drain electrode 20 to be formed.
8,308 and the drain terminal electrodes 209,309 are n ⁺ a-Si films, Cr
It consists of a three-layer film consisting of a film and an ITO film, and contributes to lowering the resistance of wiring and reducing disconnection. In addition, the semiconductor films 204 and 304 of the TFT 312 connected to the single drain electrode 208 and 308 wiring are not individually separated but exist in common under the drain electrode. As a result, the steps and the number of steps of the drain electrode wiring are significantly reduced. Therefore, in contrast to the conventional method of isolating and separating each TFT, a step of about 3,000 mm of the semiconductor film thickness is generated, whereas in the present embodiment, the gate film thickness of about 1,000 mm is sufficient, resulting in the disconnection of the drain electrode wiring. Can be extremely small.

In addition, since both the semiconductor i-layer and the gate insulating film remain below the drain electrode wiring, the insulating property at the matrix intersection between the gate electrode wiring and the drain electrode wiring is high.

〔The invention's effect〕

As described in detail above, in the method of manufacturing a TFT matrix array panel according to the present invention, the TFTs are not independently insulated and separated, but the step of integrally etching the TFT semiconductor film in the direction of one drain electrode wiring, Since the step of digging the channel portion integrally with the drain electrode formation pattern or the step of digging the channel portion integrally with the display electrode formation pattern is performed, the mask step can be reduced and the manufacturing cost can be reduced. In addition, since the steps and the number of steps of the drain electrode wiring are significantly reduced, the number of disconnections is extremely small, so that the production yield and the quality of display devices and the like can be improved. Furthermore, since the TFT is not separated in the direction of the drain electrode, separated in the direction of the gate electrode, and the insulating film integrated with the gate insulating film is left in the matrix, there is no influence between the matrix-shaped TFTs. Since the semiconductor i-layer and the gate insulating film both remain under the drain electrode wiring, the insulating property at the matrix intersection between the gate electrode wiring and the drain electrode wiring is also high.

[Brief description of the drawings]

FIG. 1A is a schematic plan view of a part of one embodiment of the present invention, FIG. 1B is a schematic sectional view taken along the line AA ′ of FIG. 1A, and FIGS. (D) schematically shows a part of a panel showing the embodiment of the manufacturing method of the present invention in the order of the manufacturing process, and is a cross-sectional view taken along line AA 'of FIGS. 3 (a) to 3 (d), respectively. FIGS. 2A to 2D are schematic plan views of a part of the panel in the process relatively shown in FIGS. 2A to 2D, and FIG. FIG. 2B is a schematic plan view of a part of the panel for performing the above operation, FIG.
It is the typical sectional view seen from a break line. In the figure, 101 and 201 are insulating substrates, 102, 202 and 302 are gate electrodes, 103, 203 and 303 are gate insulating films, 104, 204 and 304 are semiconductor films, 105, 205 and 305 are n ⁺ semiconductor layers, 106, 206 and 306 are wiring metals, 107, 207 and 307 are ITO films, 108, 208 and 308 are drain electrodes, and 109, 209 and 309 are terminals. Electrodes, 110 and 310 are source electrodes, 11
Reference numerals 1 and 311 indicate display electrodes, 112 and 312 indicate TFTs, 113 and 313 indicate semiconductor film regions, 314 indicates a plasma CVD laminated deposition region, and 415 indicates etching residues.

Claims (2)

(57) [Claims] 1. A panel in which a plurality of gate electrode wirings and drain electrode wirings are insulated from each other and arranged in a matrix array on an insulating substrate, and a thin film transistor is arranged near an intersection of the two wirings. All of the semiconductor film regions deposited under the one drain electrode wiring, and the semiconductor films of all the thin film transistors connected to the one drain electrode wiring are provided integrally in common without planar insulation. A thin-film transistor matrix array panel, wherein the electrode wiring comprises two layers of a metal film and a transparent conductive film, and the transparent conductive film on the source electrode wiring extends to form a display electrode. 2. A method according to claim 1, wherein a plurality of gate electrode wirings and drain electrode wirings are provided in a matrix form insulated from each other, and a thin film transistor is provided near an intersection of the two wirings. A step of sequentially laminating and depositing a three-layer film of a gate insulating film, a semiconductor film, and a metal film for wiring on the surface, and connecting to one drain electrode wiring by using a mask including a drain electrode wiring region and a source electrode region A step of sequentially etching and removing the two-layer film of the wiring metal film and the semiconductor film over the entire area where all the thin film transistors to be provided and the stacked and deposited area below the wiring are provided; After the deposition, it has a wiring pattern of the display electrode and a channel portion pattern of the thin film transistor formed to separate the source electrode and the drain electrode. Etching a wiring film of a display electrode using a single mask, and etching a three-layer film of the drain electrode wiring metal film of the channel portion and a partially unnecessary film such as a doped layer of a semiconductor film; A method of manufacturing a thin film transistor matrix array panel, comprising: