JPS6246574A - Manufacture of active matrix array - Google Patents
Manufacture of active matrix arrayInfo
- Publication number
- JPS6246574A JPS6246574A JP60186114A JP18611485A JPS6246574A JP S6246574 A JPS6246574 A JP S6246574A JP 60186114 A JP60186114 A JP 60186114A JP 18611485 A JP18611485 A JP 18611485A JP S6246574 A JPS6246574 A JP S6246574A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- picture element
- element electrode
- electrode
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000011159 matrix material Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000008280 blood Substances 0.000 claims description 3
- 210000004369 blood Anatomy 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims description 3
- 150000003839 salts Chemical class 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000428 dust Substances 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- BYGOPQKDHGXNCD-UHFFFAOYSA-N tripotassium;iron(3+);hexacyanide Chemical compound [K+].[K+].[K+].[Fe+3].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-].N#[C-] BYGOPQKDHGXNCD-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 29
- 238000005553 drilling Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000003491 array Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶パネルの、駆動スイッチングアレー等へ
の応用が有望なアクティブマトリクスアレーの製造方法
に係り、特にシリコンを主成分とする非単結晶半導体膜
を用いた薄膜電界効果トランジスタ（ＴＰＴ）アレーの
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an active matrix array, which is promising for application to drive switching arrays, etc. of liquid crystal panels, and particularly relates to a method for manufacturing an active matrix array, which is promising for application to drive switching arrays, etc. The present invention relates to a method of manufacturing a thin film field effect transistor (TPT) array using a film.
従来の技術
液晶パネルの駆動スイッチングアレーの応用例の要部平
面図を第２図に示す。ゲート電極２２ａｇ。FIG. 2 shows a plan view of a main part of an application example of a driving switching array for a conventional liquid crystal panel. Gate electrode 22ag.
２２ｂｇ及びゲートバス２２ａ、２２ｂとソース電極２
７ａｓ、２７ｂｓ及びソースパス２７ａ、２７ｂに囲ま
れた部分に絵素電極として透明な導体２９があり、ソー
ス電極２７ａ８とドレイン電極２８ａ。22bg, gate buses 22a, 22b and source electrode 2
There is a transparent conductor 29 as a picture element electrode in a portion surrounded by 7as, 27bs and source paths 27a, 27b, and a source electrode 27a8 and a drain electrode 28a.
２８ｂは半導体膜２４ａ 、２４ｂとゲート電極２２ａ
ｇ、２２ｂｇ上で一部重り合う様に形成されている。ゲ
ート電極２２ａｇ 、２２ｂｇはゲートバス２２＆、２
２ｂ と一体のものであり、ソース電極２７ａｓ
はソースバス２７ａと一体である。ドレイン電極２８ａ
は絵素電極２９とＣの部分でオーミック接続されている
。絵素電極２９は、Ｄの部分でゲート絶縁膜３３（第３
図に示す）を介して一部ゲートバス２２ｂと重り合う様
に形成され、ゲートバス２２ｂと絵素電極２９の重り合
いにより容量が形成されている。28b is the semiconductor film 24a, 24b and the gate electrode 22a
g and 22bg so as to partially overlap each other. Gate electrodes 22ag and 22bg are connected to gate buses 22&, 2
2b, and the source electrode 27as
is integrated with the source bus 27a. Drain electrode 28a
is ohmically connected to the picture element electrode 29 at the portion C. The picture element electrode 29 has a gate insulating film 33 (third
The pixel electrode 29 is formed so as to partially overlap the gate bus 22b via the gate bus 22b (shown in the figure), and a capacitance is formed by the overlap of the gate bus 22b and the picture element electrode 29.
以上、図を用いて説明したＴＰＴアレーのＡ −Ａ線部
分での断面図を第３図に示す。この構造は、テレビジョ
ン学会技術報告Ｉ Ｐ Ｄ ７５−ｅ （１９８３）Ｐ
２９にも示されている。基板３１上に、ゲート電極２２
ａｇを選択的に被着形成し全面にゲート絶縁膜３３を被
着形成した後に、半導体膜２４ａ１パツシベーシヨン膜
３６を選択的に被着形成し、オーミック層３６を介して
ゲート電極２２ａｇと半導体膜２４ａと一部重り合う様
にソース電極２７ａ ｓ、ドレイン電極２８ａが形成さ
れ、しかる後に絵素電極２９が選択的に被着形成されて
いる。FIG. 3 shows a cross-sectional view taken along line A--A of the TPT array described above with reference to the drawings. This structure is described in the Technical Report of the Television Society of Japan, IPD 75-e (1983)
29 is also shown. On the substrate 31, the gate electrode 22
After selectively depositing the gate electrode 22ag and depositing the gate insulating film 33 on the entire surface, a passivation film 36 is selectively deposited on the semiconductor film 24a1, and the gate electrode 22ag and the semiconductor film 24a are formed via the ohmic layer 36. A source electrode 27as and a drain electrode 28a are formed so as to partially overlap with each other, and then a picture element electrode 29 is selectively formed.
発明が解決しようとする問題点
しかしながらＴＰＴアレーの製法に於ける欠点はドレイ
ン電極２８ａの段差部Ｆに於ける絵素電極３９の段切れ
を生じる他に、第２図で示す絵素電極２９とゲートバス
２２ｂの重り合う部分りでのショートの確率が大きく、
液晶パネルへ応用した場合点欠陥不良となった。これは
、ソース、ドレイン電極２７ａｓ、２８ａの形成前に、
ゲートバス２２ｂを電気的に外部へ取り出すだめのゲー
ト絶縁膜３３への穴あけ工程に於いて、レジストのピン
ホールやゴミによるゲート絶縁膜３３のピンホールの発
生が主な原因であっだ０
問題点を解決するための手段
本発明は、これら従来のＴＰＴアレーの欠点を改善する
ためになされたものである。つまり、本発明は、複数ケ
以上のゲートとソース、ドレイン及び絵素電極を基板上
に形成してなるＴＰＴアレーの製造に於いて、絵素電極
をゲート絶縁膜形成工程より後でゲートと一部重り合う
ように選択的に被着形成し、かつゲートを外部へ電気的
に取り出すための穴あけ工程を、絵素電極形成後に行な
うことにより、ゲートと絵素電極間の層間絶縁性劣化を
おさえＴＰＴアレー〇点欠陥不良の発生率を低下させる
。Problems to be Solved by the Invention However, there are drawbacks in the manufacturing method of the TPT array, in addition to the step breakage of the picture element electrode 39 at the stepped portion F of the drain electrode 28a. There is a high probability of a short circuit at the overlapping part of the gate bus 22b,
When applied to liquid crystal panels, point defects occurred. This is done before forming the source and drain electrodes 27as and 28a.
In the process of drilling a hole in the gate insulating film 33 for electrically taking out the gate bus 22b to the outside, pinholes in the gate insulating film 33 caused by resist pinholes and dust were the main cause. Means for Solving the Problems The present invention has been made to improve these drawbacks of conventional TPT arrays. In other words, in manufacturing a TPT array in which a plurality of gates, sources, drains, and pixel electrodes are formed on a substrate, the present invention enables the pixel electrode to be integrated with the gate after the gate insulating film formation step. Deterioration of the interlayer insulation between the gate and the pixel electrode is suppressed by selectively depositing the parts so that they overlap, and by performing the drilling process to electrically take out the gate to the outside after forming the pixel electrode. Reduces the incidence of TPT array point defects.
作 用
穴あけ工程に於ける絶縁膜のエツチングに於いて、レジ
ストのピンホール、ゴミ等により不用な部分に穴がおい
てしまうことがよくある。ゲートと絵素電極との一部重
り合った部分で以上の様な不用な穴があくとショートし
てしまってＴＰＴアレーとしては点欠陥不良となる。し
かるに、本発明のごとく、絵素電極形成を絶縁膜の穴あ
け工程以前に行なった場合穴あけ工程でのレジストに万
が一ゲートと絵素電極の重り合った部分でピンホールが
あったとしても、エツチング液は絵素電極でストップさ
れ、ゲート電極と絵素電極の間のショート不良にはつな
がらない。つまり、本発明は、層間絶縁に用いる膜のエ
ツチング液程を、層間絶縁を必要とする２ｐの導体膜の
形成工程の間に入れないＴＰＴアレーの製造方法である
。Function: During the etching of the insulating film in the hole-drilling process, holes are often left in unnecessary areas due to resist pinholes, dust, etc. If an unnecessary hole like the one described above is formed in the part where the gate and the picture element electrode partially overlap, a short circuit will occur, resulting in a point defect failure in the TPT array. However, if the pixel electrode is formed before the insulating film drilling step as in the present invention, even if there is a pinhole in the resist during the drilling step where the gate and pixel electrode overlap, the etching solution will is stopped at the picture element electrode and does not lead to a short circuit between the gate electrode and the picture element electrode. In other words, the present invention is a method of manufacturing a TPT array in which the etching solution for the film used for interlayer insulation is not used during the process of forming the 2p conductor film that requires interlayer insulation.
実施例
以下、本発明のＴＰＴアレー〇製造方法について要部断
面図（第１図）を用いて詳細に説明する。EXAMPLE Hereinafter, the method for manufacturing a TPT array 〇 of the present invention will be explained in detail using a cross-sectional view of main parts (FIG. 1).
本発明のＴＰＴアレーの平面図は従来例と説明した第２
図と同じものであり、製造方法としてソースおよびドレ
イン電極を形成する前に絵素電極を形成するものが本発
明のＴＰＴアレーである。The plan view of the TPT array of the present invention is the same as that of the conventional example.
The TPT array of the present invention is the same as the one shown in the figure, and the manufacturing method is to form the picture element electrodes before forming the source and drain electrodes.
実施例１
ガラス基板１上にゲート電極２及びゲートバス配線とな
る導体をＣｒ、ＣｒＭｏＳｉ２の２層金属等で形成する
。続いて１３．５６ＭＨｚの高周波プラズマ化学気相堆
積法（ＰＣＶＤ法）によりシリコン窒化膜、非晶質シリ
コン膜、シリコン窒化膜の３層をそれぞれゲート絶縁膜
３、チャンネル部を形成する半導体膜４及びパッシベー
ション膜５として連続堆積する。Example 1 On a glass substrate 1, a gate electrode 2 and a conductor serving as a gate bus wiring are formed using a two-layer metal such as Cr and CrMoSi2. Subsequently, three layers of a silicon nitride film, an amorphous silicon film, and a silicon nitride film are formed using a 13.56 MHz high-frequency plasma chemical vapor deposition method (PCVD method), respectively, to form a gate insulating film 3, a semiconductor film 4 for forming a channel portion, and a silicon nitride film. The passivation film 5 is continuously deposited.
パッシベーション膜６をゲートと一部重り合う様に不要
部分を除去した後に、リン等を含むｎ＋型の非晶質シリ
コン膜をオーミック層６としてＰＣＶＤ法によシ全面に
堆積し、半導体膜４と同じ形状に不要部分を除去しパタ
ーニングする。更に、Ｉｎ５ｎＯを絵素電極９として所
望の形状（第２図の絵素電極２９に相当）にパターニン
グした後に、ゲート絶縁膜３にゲートバス取り出しのだ
めの穴（図示せず）を選択的に形成した後にＪす（アル
ミ）を全面に被着形成し、赤血塩を用いてフォトリング
ラフ法によりＡｌを選択的に除去しパターニングするこ
とによシ、ソース、ドレイン電極７，８を形成する。After removing unnecessary parts of the passivation film 6 so as to partially overlap the gate, an n+ type amorphous silicon film containing phosphorus etc. is deposited as an ohmic layer 6 over the entire surface of the passivation film 6 by PCVD, and the semiconductor film 4 and Remove unnecessary parts and pattern into the same shape. Furthermore, after patterning In5nO into a desired shape as the picture element electrode 9 (corresponding to the picture element electrode 29 in FIG. 2), a hole (not shown) for taking out the gate bus is selectively formed in the gate insulating film 3. After that, JS (aluminum) is deposited on the entire surface, and the source and drain electrodes 7 and 8 are formed by selectively removing and patterning Al using red blood salt using the photolithographic method. .
本実施例の特徴は、絵素電極９であるＩｎ５ｎＯ上のＡ
ｌを除去するのに赤血塩を用いることにより、Ｉｎ５ｎ
Ｏにダメージを与えることなくソース。The feature of this embodiment is that A on In5nO, which is the picture element electrode 9,
By using red blood salt to remove In5n
Source without damaging O.
ドレイン電極７，８のパターニングが行なえる。Patterning of the drain electrodes 7 and 8 can be performed.
又ゲート絶縁膜３の穴あけ工程時に、既に絵素電極９と
ゲート電極２が形成されているため、第２図のＤの部分
に、穴あけ工程に用いるレジストにピンホール、ゴミ等
が存在したとしても、Ｉｎ５ｎＯでゲート絶縁膜のエツ
チング液がしゃ断され、第２図のＤの部分における絵素
電極２９とゲートバス２２ｂのごときショートは発生し
ない。更に従来の第３図Ｆで示すドレイン部の段差によ
る絵素電極２９の段切れ現象が、本発明の第１図Ｇの部
分では絵素電極９の段切れは発生しない。Furthermore, since the pixel electrode 9 and the gate electrode 2 have already been formed during the hole-drilling process for the gate insulating film 3, it is assumed that there are pinholes, dust, etc. in the resist used for the hole-drilling process at the portion D in FIG. In this case, the etching solution for the gate insulating film is blocked by In5nO, and a short circuit such as that between the picture element electrode 29 and the gate bus 22b at the portion D in FIG. 2 does not occur. Furthermore, unlike the conventional phenomenon in which the pixel electrode 29 is broken due to the level difference in the drain portion shown in FIG. 3F, the pixel electrode 9 does not break in the portion shown in FIG. 1G in the present invention.
実施例２
実施例１に於いて、ソース、ドレイン電極７゜８をＭｏ
、Ｔｉ、Ｔａ、Ｗ等の高融点金属又はそれらのシリサイ
ドとＡｌの２層金属で形成する。これらの金属を２回の
エツチング液程に分けてソース。Example 2 In Example 1, the source and drain electrodes 7°8 were made of Mo.
, Ti, Ta, W, etc., or their silicides, and a two-layer metal layer of Al. Divide these metals into two etching solutions and source.
ドレインを選択的にパターニングする。１回目は、リン
酸を用いてＡｌをパターニングし続いて同じレジストパ
ターンを用いてＨＦ又はＨＦとＨＮＯ３の混合液で高融
点金属又はシリサイドをパターニングする。Selectively patterning the drain. In the first step, Al is patterned using phosphoric acid, and then a high melting point metal or silicide is patterned using HF or a mixed solution of HF and HNO3 using the same resist pattern.
本実施例は、Ｉｎ５ｎＯ上のＡ７のパターニングに際し
、リン酸等のＡｌｌのエツチング時間の制御が容易なエ
ツチング液が使用出来、宜Ｉｎ５ｎＯは高融点金属又は
それらのシリサイドで覆われているため消失しないで行
なえる効果がある。In this example, when patterning A7 on In5nO, an etching solution such as phosphoric acid that can easily control the etching time of All can be used, and since In5nO is covered with high melting point metals or their silicides, it does not disappear. There is an effect that can be done with.
発明の効果
本発明は、液晶パネル等の応用に際し絵素電極とゲート
バスのショートによる点欠陥の発生を低減する効果を有
する。Effects of the Invention The present invention has the effect of reducing the occurrence of point defects due to short circuits between picture element electrodes and gate buses when applied to liquid crystal panels and the like.
更に、ゲートバスと絵素電極を一部重ね合せて容量を形
成する構成の薄膜トランジスタ（アクティブマトリクス
）アレーに於いて上記効果ははなはだしい。Further, the above-mentioned effect is remarkable in a thin film transistor (active matrix) array having a structure in which a gate bus and a picture element electrode are partially overlapped to form a capacitor.
以上液晶パネル応用に関して述べたが他のスイッチング
アレーに於ける信号保持電極を上記絵素電極と同じ構成
にすれば、本発明は同様の効果を有する。The above description has been made regarding application to a liquid crystal panel, but if the signal holding electrodes in other switching arrays have the same structure as the picture element electrodes, the present invention will have similar effects.
第１図は本発明の一実施例によるアクティブマトリクス
アレーの要部断面図、第２図はアクティブマドリスアレ
ーの平面図、第３図は第２図のＡＡ／線断面図である。
２・・・・・・ゲート電極、３・・・・・・ゲート絶縁
膜、７゜８・・・・・・ソース、ドレイン電極、９・・
・・・・絵素電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図 ２−Ｙ−）、電極
３−、・ 特訪頑
第２図
ゴ５３図FIG. 1 is a sectional view of a main part of an active matrix array according to an embodiment of the present invention, FIG. 2 is a plan view of the active matrix array, and FIG. 3 is a sectional view taken along line AA/2 in FIG. 2...Gate electrode, 3...Gate insulating film, 7゜8...Source, drain electrode, 9...
...Picture element electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2-Y-), Electrode 3-, Tokuba Gun Figure 2 Go53
Claims (3)
を形成する第１の工程、全面に渡ってゲート絶縁膜を堆
積する第２の工程、半導体膜を選択的に被着形成する第
３の工程、ソース、ドレイン電極として第２の導体膜を
形成する第４の工程、前記ゲート絶縁膜の特定の部分に
穴をあける第６の工程、透明な第３の導体膜を選択的に
被着形成する第６の工程を含むアクティブマトリクスア
レーの製造方法に於いて、前記第ｅの工程を、前記第２
の工程又は第３の工程より後で行ない前記第５の工程よ
り前に行なうことを特徴とするアクティブマトリクスア
レーの製造方法。(1) A first step of forming a first conductor film as a gate electrode on one main surface of the substrate, a second step of depositing a gate insulating film over the entire surface, and selectively depositing a semiconductor film. a fourth step of forming a second conductive film as the source and drain electrodes; a sixth step of forming a hole in a specific portion of the gate insulating film; and selecting a transparent third conductive film. In the method for manufacturing an active matrix array including a sixth step of depositing the active matrix array, the e-th step is performed in the second step.
A method for manufacturing an active matrix array, characterized in that the step is performed after the step or the third step and before the fifth step.
を堆積し、赤血塩等の透明な第３の導体膜をエッチング
しない液によって選択除去することによりソース、ドレ
イン電極を形成することを特徴とする特許請求の範囲第
１項記載のアクティブマトリクスアレーの製造方法。(2) In the fourth step, source and drain electrodes are formed by depositing aluminum as a second conductor film and selectively removing a transparent third conductor film such as red blood salt with a non-etching solution. A method of manufacturing an active matrix array according to claim 1, characterized in that:
金属又はそれらのシリサイドとアルミとを連続堆積して
、選択的に除去することによりソース、ドレインを形成
することを特徴とする特許請求の範囲第１項記載のアク
ティブマトリクスアレーの製造方法。(3) In the fourth step, a source and a drain are formed by sequentially depositing high-melting point metals or their silicides and aluminum as the second conductive film and selectively removing them. A method for manufacturing an active matrix array according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60186114A JPH07112068B2 (en) | 1985-08-24 | 1985-08-24 | Manufacturing method of active matrix array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60186114A JPH07112068B2 (en) | 1985-08-24 | 1985-08-24 | Manufacturing method of active matrix array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6246574A true JPS6246574A (en) | 1987-02-28 |
| JPH07112068B2 JPH07112068B2 (en) | 1995-11-29 |
Family
ID=16182605
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60186114A Expired - Lifetime JPH07112068B2 (en) | 1985-08-24 | 1985-08-24 | Manufacturing method of active matrix array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07112068B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5210045A (en) * | 1987-10-06 | 1993-05-11 | General Electric Company | Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
| US6184963B1 (en) | 1987-06-10 | 2001-02-06 | Hitachi, Ltd. | TFT active matrix LCD devices employing two superposed conductive films having different dimensions for the scanning signal lines |
| JP2015200901A (en) * | 2005-01-31 | 2015-11-12 | 株式会社半導体エネルギー研究所 | display device |
-
1985
- 1985-08-24 JP JP60186114A patent/JPH07112068B2/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7450210B2 (en) | 1987-06-10 | 2008-11-11 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US6184963B1 (en) | 1987-06-10 | 2001-02-06 | Hitachi, Ltd. | TFT active matrix LCD devices employing two superposed conductive films having different dimensions for the scanning signal lines |
| US6384879B2 (en) | 1987-06-10 | 2002-05-07 | Hitachi, Ltd. | Liquid crystal display device including thin film transistors having gate electrodes completely covering the semiconductor |
| US6839098B2 (en) | 1987-06-10 | 2005-01-04 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US6992744B2 (en) | 1987-06-10 | 2006-01-31 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US7196762B2 (en) | 1987-06-10 | 2007-03-27 | Hitachi, Ltd. | TFT active matrix liquid crystal display devices |
| US5210045A (en) * | 1987-10-06 | 1993-05-11 | General Electric Company | Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
| JP2015200901A (en) * | 2005-01-31 | 2015-11-12 | 株式会社半導体エネルギー研究所 | display device |
| US10573705B2 (en) | 2005-01-31 | 2020-02-25 | Semiconductor Energy Laboratory Co., Ltd. | Display device with defective pixel correction |
| US9613988B2 (en) | 2005-01-31 | 2017-04-04 | Semiconductor Energy Laboratory Co., Ltd. | Display device having narrower wiring regions |
| JP2016177305A (en) * | 2005-01-31 | 2016-10-06 | 株式会社半導体エネルギー研究所 | Display device |
| US10700156B2 (en) | 2005-01-31 | 2020-06-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US11362165B2 (en) | 2005-01-31 | 2022-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US11910676B2 (en) | 2005-01-31 | 2024-02-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07112068B2 (en) | 1995-11-29 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |