JP3302475B2 - Method for manufacturing thin film transistor array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a method of manufacturing a thin film transistor array.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (hereinafter, referred to as TFTs) have been used.
And an active matrix type liquid crystal display device (hereinafter, referred to as TFT-LCD) using a thin film transistor array in which display electrodes are arranged in a matrix.

In general, a TFT array is arranged on a transparent substrate such that a plurality of address wirings and data wirings intersect each other at right angles in a row direction and a column direction. A plurality of thin film transistors, each having a gate electrode connected to an address line and a drain electrode connected to a data line, are arranged, and a plurality of display electrodes connected to a source electrode of the thin film transistor are arranged in a matrix.

FIG. 6 shows a TFT of such a conventional TFT array.
FIG. 7 is a sectional view taken along line AA of FIG.

The above-mentioned TFT array is manufactured in accordance with a sectional view (part 1) of a TFT array manufacturing process shown in FIG. 8 and a sectional view (part 2) of a TFT array manufacturing process shown in FIG.

(1) First, as shown in FIG. 8A, a gate electrode 2 made of Al, an Al-based alloy, Ta, a Ta alloy, Cr or the like is placed on an insulating transparent substrate 1 such as a glass substrate.
Is formed by sputtering and a predetermined processing method.

A silicon nitride film (SiN film) 3 serving as a gate insulating film is deposited over the gate electrode, and a non-doped n ^- a-Si (amorphous silicon) layer 4 is formed on the silicon nitride film (SiN film). Was successively deposited by plasma CVD. After the deposition, the etching stopper layer (blocking layer) 5 is processed into a predetermined shape.

(2) Next, after removing the surface oxide film on the n ^- a-Si layer 4 by NH ₄ F treatment or the like, FIG.
As shown in (B), an n ⁺ a-Si film 6 containing an n-type impurity is deposited by a plasma CVD method or the like. Furthermore, n
^After the surface oxide film on the ⁺ a-Si film 6 is similarly removed by NH ₄ F treatment or the like,
A Cr film 7 is deposited.

(3) Next, as shown in FIG. 8C, the Cr film 7 and n ⁺ a-
The Si layer 6 and the n ^- a-Si layer 4 are continuously processed to form a contact layer 6a, a source electrode 7a and a contact layer 6b,
A drain electrode 7b is formed.

(4) Next, as shown in FIG. 8D, an ITO film 8 is deposited by using a sputtering method or the like.

(5) Next, as shown in FIG. 9A, the ITO film 8 is processed by a wet etching process to form a pixel electrode 8a.

(6) Next, as shown in FIG. 9B, the Al-based metal film 9 and the barrier C
An r film 10 is deposited. This barrier Cr film 10 is used in a photoresist developing step during data wiring processing described later.
This is to prevent a battery reaction between the Al-based metal film 9 and the ITO film 8 from occurring.

(7) Next, as shown in FIG. 9C, the barrier Cr film 1 is formed by a wet etching process.
0, the Al-based metal film 9 is continuously processed to form a source electrode wiring 9a, a drain electrode 9b, and a data wiring 9c (see FIG. 7).

(8) Next, as shown in FIG. 9D, the barrier Cr film 10 remaining after the data wiring is completely removed by a wet etching process.

(9) Next, as shown in FIG. 7, the surface protection film 11 made of SiN is removed except for the opening of the pixel electrode 8a.
To form

Thus, a thin film transistor array for a liquid crystal display is completed.

[0017]

The dry etching process of the Cr film 7, the n ⁺ a-Si layer 6 and the n ^- a-Si layer 4 in the above (3) is a conventional process of mixing CCl ₄ (carbon tetrachloride). This was done using gas. However, recent regulations on CFCs have made it impossible to use CCl _{4, and} there has been a demand for the development of a process using a CFC-free gas that does not use a CFC-based gas.

However, the surface of the gate insulating film (SiN film) is roughened by a dry etching process using an HCl-based etching gas instead of a Freon-based gas.
To form the ITO formed in the subsequent conventional process (9).
Since the resistance of the pixel electrode made of a film is increased, the operating characteristics of the TFT array are extremely deteriorated, and it has been difficult to manufacture a practical TFT array.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a thin film transistor array having a high yield by reducing the number of steps and performing a dry etching process using a Freon-less gas. .

[0020]

In order to achieve the above object, the present invention provides a thin film transistor provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other; A pixel electrode connected to one of the source electrode and the drain electrode ;
In a method for manufacturing a thin film transistor array in which a plurality of the memory cells are arranged in a matrix and the address wiring is connected to a gate electrode of the thin film transistor and the data wiring is connected to the other of the source electrode and the drain electrode, a gate electrode is formed on an insulating transparent substrate. And an insulating film covering the gate electrode;
N no impurities on the insulating film ^- amorphous silicon film and sequentially laminated, said n ^- forming a blocking layer in correspondence to the channel portion of the transistor on the amorphous silicon film, the n ^- amorphous silicon
N ⁺ amorphous silicon on the film and the blocking layer
A silicon film is deposited, and the n ⁺
An amorphous silicon film and the n ^- amorphous film
The recon film is processed, and electricity is mutually applied on the blocking layer.
Forming a pair of contact layers and a semiconductor layer which are separated from each other, and forming the pair of contact layers and the semiconductor layer on the separated one contact layer.
Forming a drain electrode wiring made of a metal layer;
Form source electrode wiring made of metal layer on contact layer
And the transparent electrode connected to the source electrode wiring
And forming a pixel electrode .

[0021]

According to the present invention, n ⁺ a-Si
Compared with the source / drain electrodes formed by continuously depositing a Cr film on the film, the Cr film and the n ⁺ a-Si film are formed by depositing the Cr film after patterning the contact layer of the n ⁺ a-Si film. By eliminating the step of etching the stacked film with the above, the gate insulating film serving as the base film of ITO can be exposed by dry-etching only the two layers of the n ⁺ a-Si film and the n ^- a-Si film. . Therefore, S
Since the steps of depositing and etching Cr on the i-based film are not required, the surface of the gate insulating film forming ITO becomes smooth.

Therefore, the source / drain electrodes can be formed by a dry etching process using a Freon-less gas without increasing the resistance of the ITO formed on the gate insulating film. Therefore, the yield can be improved without leaving any etching residue.

Also, a contact made of an n ⁺ a-Si film
Including on the layer , the wiring metal is changed to Cr film / Al-based metal film / C
After laminating in a three-layer structure of an r film, the film is etched so as to be connected to the source / drain electrodes made of the n ⁺ a-Si film, and the data wiring, the drain electrode wiring and the source electrode wiring are formed.
Since the line was formed , it is a contact layer for the drain electrode
n ⁺ a-Si film and a good electrical contact between the Al-based metal film is the main current path of the drain electrodes and data lines, and a contact layer of the source electrode n ⁺ a-
Al-based gold which is the main current path of Si film and source electrode wiring
Good electrical contact with the metal film can be secured.

[0024]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
Sectional view of manufacturing process of LCD TFT array (Part 1), figure
2 is a TFT of a TFT-LCD showing the first embodiment of the present invention.
Sectional view of the array manufacturing process (part 2), and FIG.
FIG. 4 is a plan view of the TFT array of the LCD, and FIG.
It is a line sectional view.

(1) First, as in the conventional process, as shown in FIG. 1A, an Al, Al-based alloy, Ta, Ta alloy, C
A gate electrode 22 made of r or the like is formed by sputtering and a predetermined processing method.

Next, a SiN film 23 serving as a gate insulating film is formed, and an n ^- a-Si film 24 in which an impurity serving as a semiconductor layer is non-doped is deposited by plasma CVD, followed by depositing a SiN film. Then, the etching stopper layer (blocking layer) 25 is processed into a predetermined shape.

(2) Next, after removing the surface oxide film on the n ^- a-Si film 24 (by NH ₄ F treatment or the like), as shown in FIG.
⁺ Only the a-Si film 26 is deposited.

(3) Next, as shown in FIG. 1C, a dry etching process using a Freon-less gas (eg, chlorine only, chlorine + helium gas, etc.)
^{The +} a-Si film 26 and the n ^- a-Si film 24 are continuously processed to form a semiconductor layer including the contact layers 26a and 26b and the n ^- a-Si film.

(4) Next, as shown in FIG. 1D, an ITO film 27 is deposited by using a sputtering method or the like.

(5) Next, as shown in FIG. 2A, the ITO film 27 is processed by a wet etching process to form a pixel electrode 27a.

(6) Next, as shown in FIG.
The Cr film 28, the Al-based metal film 29, and the barrier Cr film 30 are deposited by using a sputtering method or the like.

(7) Next, as shown in FIG. 2C, a barrier Cr film 30 is formed by a wet etching process.
/ Al-based metal film 29 is continuously processed to form source electrode wiring 29a, drain electrode wiring 29b, and data wiring 29c.
(See FIG. 3). At this time, the source electrode wiring 29
a, the Cr film 28 remains on the entire surface under the drain electrode wiring 29b.

(8) Next, as shown in FIG. 2D, the entire Cr metal film exposed on the surface is removed by a wet etching process. That is, at this time, of the barrier Cr film 30 and the Cr film 28, the source electrode wiring 2
9a, portions not covered by the drain electrode wiring 29b are removed at the same time.

(9) Next, as shown in FIG. 4, a surface protection film 31 made of SiN is formed except for the openings of the pixel electrodes.

Thus, a thin film transistor for a liquid crystal display is completed.

As described above, in the first embodiment, n ⁺
After the contact layers 26a and 26b made of the a-Si film 26 are formed, an ITO film 27 is deposited on the entire surface and source / drain regions are formed by etching, and a C / C region is formed thereon.
After sequentially depositing an r film, an Al film, and a Cr film, the three metal films were etched to form a source electrode, a drain electrode, and a drain electrode wiring, so that the n ⁺ a-Si film 26 was formed.
No etching is performed on the portion where the ITO film and the Cr film are in contact with each other. Therefore, the smoothness of the surface of the SiN film as the base film on which the ITO film is formed can be maintained, and the IN formed on the SiN film can be maintained.
The resistance of the TO film can be kept low. Also, since the photoresist is not exposed to the Cr film dry etching process,
Deterioration of the photoresist is eliminated, the resist is easily stripped after etching, and the data wiring has a structure in which a Cr film is laid over the entire lower surface of the Al-based metal film. Then, the terminal part also has C
Underlay of the r-film enters. Therefore, the corrosion resistance of the terminal is improved. Further, the ITO film 27 is formed of n ⁺ a-Si / n ^- a
-Si, it is sufficient to ride over the step between the two films, and C
Since the r film does not run, the height of the step is reduced, and the overhang due to the etching of the Cr film is reduced, so that the disconnection failure at the step is reduced.

FIG. 5 shows a TFT according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a manufacturing process of a TFT array of an LCD.

The first half of the process is the same as that of the first embodiment shown in FIG.
This is the same as the steps from (A) to FIG. 1 (D), and the description is omitted here.

(1) After the steps shown in FIGS. 1A to 1D , a wet etching process
As shown in (A), the pixel electrode 27b is formed so as to be spatially separated so as not to overlap with the contact layer 26a.

(2) Next, as shown in FIG. 5B, a Cr film 41 is deposited on the entire surface of the substrate including the space between the pixel electrode 27b and the contact layer 26a by a sputtering method or the like. An Al-based metal film 42 and a barrier Cr film 43 are sequentially deposited.

(3) Next, the barrier Cr film 43 / Al-based metal film 42 is continuously processed by a wet etching process to form a source electrode wiring 42a and a drain electrode wiring as shown in FIG. 42b is formed. At this time, substantially the Cr film 41 remains on the entire surface under the source electrode wiring 42a and the drain electrode wiring 42b.

(4) Next, as shown in FIG. 5D, the barrier Cr film 43 and the Cr film 41 all exposed on the surface are removed by a wet etching process.

In the second embodiment, the pixel ITO (display electrode) 27b and the source electrode 26a are spatially separated, and the space therebetween is electrically connected by a two-layer metal film of a Cr film 41 and an Al-based metal film 42. To be connected.

Therefore, since the pixel ITO 27b does not need to ride over the step of the source electrode 26a, there is no disconnection defect at the step.

It is needless to say that the source electrode in the above embodiment can be replaced with a drain electrode and the drain electrode can be replaced with a source electrode.

The present invention is not limited to the above-described embodiment, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

[0048]

Effect of the Invention] As described above in detail, according to the present invention, such that dry etching the both membranes conventional Cr film, such as the portion in contact with the n ⁺ a-Si film Kunar < br /> so, be applied dry etching process using a chlorofluorocarbon-free gas, the SiN film surface of the underlying layer ITO is formed Ru can be maintained smooth. Thereby , the sheet resistance of the ITO film formed on the SiN film is not increased, and the dry etching is used.
There is no etching residue of the Si film. And
Further, since the step of etching only the Cr film for forming the source / drain electrodes is not required, the number of manufacturing steps can be reduced . Therefore, the TFT array can be manufactured with good yield by dry etching using a Freon-less gas.

[Brief description of the drawings]

FIG. 1 is a diagram showing a TFT of a TFT-LCD according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view (No. 1) of a manufacturing process of the FT array.

FIG. 2 shows a TFT of a TFT-LCD showing a first embodiment of the present invention.
FIG. 11 is a sectional view of the manufacturing process of the FT array (part 2).

FIG. 3 is a graph showing a TFT of a TFT-LCD according to a first embodiment of the present invention;
It is a top view of an FT array.

FIG. 4 is a sectional view taken along line BB of FIG. 3;

FIG. 5 shows a TFT of a TFT-LCD according to a second embodiment of the present invention.
It is a manufacturing process sectional view of an FT array.

FIG. 6 is a plan view of a TFT array of a conventional TFT-LCD.

FIG. 7 is a sectional view taken along line AA of FIG. 6;

FIG. 8 is a sectional view (part 1) illustrating a manufacturing process of a TFT array of a conventional TFT-LCD.

FIG. 9 is a sectional view (part 2) of a process for manufacturing a TFT array of a conventional TFT-LCD.

[Description of Signs] 21 Insulating transparent substrate 22 Gate electrode 23 SiN film 24 n ^- a-Si film 25 Etching stopper layer (blocking layer) 26 n ⁺ a-Si film 26a, 26b Contact layer 27 ITO film 27a, 27b Pixel Electrodes 28, 41 Cr film 29, 42 Al-based metal film 29a, 42a Source electrode wiring 29b, 42b Drain electrode wiring 29c Data wiring 30, 43 Barrier Cr film 31 Surface protective film

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-179366 (JP, A) JP-A-2-42761 (JP, A) JP-A-4-253342 (JP, A) JP-A-2-253 51128 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/1362 G02F 1/1343 H01L 29/78

Claims (4)

(57) [Claims] 1. A thin film transistor provided at each intersection of a plurality of address wirings and a plurality of data wirings arranged to cross each other, and a pixel electrode connected to one of a source electrode and a drain electrode of the thin film transistor. but,
A method of manufacturing a thin film transistor array, wherein a plurality of the thin film transistors are arranged in a matrix, and the address wiring is connected to a gate electrode of the thin film transistor, and the data wiring is connected to the other of the source electrode and the drain electrode. An electrode is formed, an insulating film covering the gate electrode, and an n ^- amorphous silicon film containing no impurities are sequentially stacked on the insulating film, and the n ^- amorphous silicon film is formed on the n ^- amorphous silicon film so as to correspond to a channel portion of a transistor. forming a blocking layer, (b) said the n ^- n ⁺ amorphous silicon film is deposited on the amorphous silicon film and the blocking layer
Then, the n ⁺ amorphous silicon
Processing the silicon film and the n ^- amorphous silicon film
And electrically separated from each other on the blocking layer.
Forming a pair of contact layers and a semiconductor layer ; and (c) forming a metal layer on the separated one contact layer.
Forming a drain electrode wiring made of
When a source electrode wiring made of a metal layer is formed on the
, The method of manufacturing a thin film transistor array, characterized by a step of forming a pixel electrode made of a transparent electrode connected to the source electrode wiring. 2. The step of forming the source electrode wiring and the pixel electrode includes forming a transparent electrode by bringing the pixel electrode into contact with the other contact layer, and forming the transparent electrode into a predetermined shape. Patterning into a shape, and the other
Contacting the contact layer on the tact layer and the pixel electrode
2. The method according to claim 1 , further comprising the step of forming the source electrode wiring on a portion to be touched . 3. The drain electrode wiring and the source electrode.
The step of forming the wiring and the pixel electrode includes the step of forming the pixel electrode and the step of forming a Cr / Al
Forming a three-layer metal wiring layer composed of a base metal / Cr; etching the upper Cr / Al-based metal layer of the three metal wiring layers to form the drain electrode wiring and the source;
Patterning into the shape of the electrode wiring; and forming a lower Cr film exposed on the surface and a lower portion of the pair of contact layers.
2. The method for manufacturing a thin film transistor array according to claim 1, further comprising the step of simultaneously removing the Cr films of the layers . Wherein the step of forming the source electrode wiring and the pixel electrode includes a step of forming the pixel electrode said other contact layer spatially separated, and the pixel electrode
2. The method according to claim 1, further comprising: connecting the other contact layer with the metal layer.