JP2550692B2 - Method of manufacturing thin film transistor array - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film transistor array used in a liquid crystal display device or the like, and particularly, to prevent a short circuit accident and to manufacture a thin film transistor array with a high yield. Manufacturing method.

[Prior Art] Various types of thin film transistors (hereinafter, referred to as TFTs) are known. Among them, a so-called electrode having an inverted staggered structure in which a gate electrode is a lower layer and having source / drain contact holes opened The digging type is most widely used because of characteristics such as high on / off ratio and low leakage current.

The manufacturing method of this type of TFT array is shown in FIG.
This will be described with reference to FIG. First, the gate electrode 11 and the gate bus line (not shown) are formed on the insulating substrate 10 [FIG. 2 (a)]. Then, a three-layer film including a gate insulating film 12, a non-doped amorphous silicon (hereinafter referred to as a-Si) film 13 and a protective insulating film 14a is continuously formed by using a plasma CVD method. −Si
These films are patterned so that the film 13 and the protective insulating film 14a remain in the same island shape only in the TFT formation region [FIG. 2 (b)]. Subsequently, a transparent conductive film is formed and patterned to form the pixel electrode 15 [second
Figure (c)]. Next, the protective insulating film 14a is subjected to a photoetching method to open the source contact hole 18 and the drain contact hole 19 [FIG. 2 (d)]. Then, using a plasma CVD method, n ^{+ a} − heavily doped with phosphorus is used.
The Si film 20 is formed, and then the metal film 21 is formed [FIG. 2 (e)]. Finally, the metal film 21 and the n ⁺ a-Si film 20 are patterned to form the source electrode 22, the drain electrode 23, and the wiring connecting the source electrode and the pixel electrode 15 [FIG. 2 (f)].

[Problems to be Solved by the Invention] In the TFT array obtained by the above-described conventional manufacturing method, as shown in FIG.
Since the drain electrode 23 and the drain electrode 23 are formed on the same plane, the drain electrode 23 and the pixel electrode 15 of the adjacent pixel (D-
(Between P) 24, there is a high probability that a short circuit will occur due to a patterning defect.

If this D-P short circuit exists, it appears as a white or black point defect due to erroneous lighting or non-lighting in the display characteristic inspection process after the manufacturing of the liquid crystal display device is completed. And if there are more than one of these point defects on the display screen, the product must be rejected.
This point is a serious defect item. However, with the conventional method, it is difficult to keep this point below a certain level, and therefore, conventionally, after being assembled as a display device,
As much as 30% of products were considered defective.

[Means for Solving the Problems] A method of manufacturing a TFT array according to the present invention is a method of manufacturing a TFT array having an inverted staggered structure using an a-Si film on an insulating substrate, which comprises a gate electrode and a gate. A step of forming a bus line, a step of forming a gate insulating film, a non-doped amorphous silicon film, and a first protective insulating film in this order thereon, and a step of leaving the first protective insulating film and the non-doped amorphous silicon film at a thin film transistor forming portion. Patterning, forming a pixel electrode on the gate insulating film, forming a second protective insulating film covering the entire surface, and selectively selecting the first protective insulating film and the second protective insulating film. To form a through hole on the pixel electrode and a source contact hole and a drain hole on the non-doped amorphous silicon film. Contact hole, a step of forming a two-layer film composed of an amorphous silicon film containing impurities at a high concentration and a metal film, and patterning the two-layer film to form a source electrode, a drain electrode, and a necessary wiring, And the drain electrode wiring of the thin film transistor adjacent to the electrode formed on the gate insulating film is separated by the second protective insulating film.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a TFT array showing the process sequence of one embodiment of the present invention. First, as shown in FIG. 1 (a), a Cr film having a film thickness of 1500 Å is formed on an insulating substrate 10 such as a glass substrate by sputtering, and the Cr film is patterned by using a photoetching method to form the gate electrode 11 and Gate bus lines and the like (not shown) are formed. Next, as shown in FIG. 1 (b), a gate insulating film 12 of SiN film having a film thickness of 3000Å, a non-doped a-Si film 13 having a film thickness of 1500Å, and a Si film having a film thickness of 1000Å.
A three-layer film of the N-film first protective insulating film 14 is continuously formed by the plasma CVD method, and the non-doped a-Si film 13 and the first protective film 14 are formed on the gate electrode 11 at the location where the TFT is provided. Are patterned by a dry etching method so as to leave islands in the same pattern.

Then, as shown in Fig. 1 (c), an IT with a film thickness of 1000Å
An O transparent conductive film is formed by a sputtering method, and this is patterned to form a pixel electrode 15. Next, as shown in FIG. 1 (d), a second film made of a SiN film having a thickness of 1500 Å is formed.
The protective insulating film 16 is formed by the plasma CVD method. Subsequently, as shown in FIG. 1E, a through hole 17 for the pixel electrode for making contact with the pixel electrode, a source contact hole 18 for forming the source electrode, and a drain for forming the drain electrode. Contact hole 19
The second protective insulating film 16 and the first protective insulating film 14 are continuously etched by wet etching.

Next, as shown in FIG. 1 (f), plasma CGD was performed with a 200 Å-thick n ⁺ a-Si 20 film doped with a high concentration of n-type impurities.
Formed by the method and then overlaid with a film thickness of 3000 Å
The Cr film is formed as the metal film 21 by the sputtering method. Then, as shown in FIG. 1 (g), the metal film 21 and n ⁺ a-S
The i film 20 is dry-etched to form the source electrode 22, the drain electrode 23, the wiring between the source electrode and the through hole 17, and other necessary wiring.

In this embodiment, the first protective insulating film 14 has a function of protecting the back channel of the TFT, and the second protective insulating film 16
Has a function of insulating the pixel electrode 15 and the drain electrode 23 from each other.

Compared with the conventional manufacturing method shown in FIG. 2, although the second protective insulating film forming step is increased by one step, the photoresist step and the etching step are not increased. However, according to this example, the point defect defect of the liquid crystal display device could be drastically reduced from 30% to 2%.

[Effects of the Invention] As described above, the present invention relates to a method of manufacturing an electrode engraving type TFT array having an inverted staggered structure, in which a protective film provided in a back channel of a TFT after forming an electrode wiring (pixel electrode) is used. Since the insulating film on the electrode wiring is formed, the present invention can prevent a planar short circuit between the electrode wiring (pixel electrode) and the adjacent drain electrode without increasing the number of steps. TF for display device according to the present invention
It can be used in T-arrays to dramatically reduce point defects.

[Brief description of drawings]

1 (a) to 1 (g) are sectional views of a TFT array showing the order of steps of an embodiment of the present invention, and FIGS. 2 (a) to (f) are a TFT array showing the order of steps of a conventional example. FIG. 10 ... Insulating substrate, 11 ... Gate electrode, 12 ... Gate insulating film, 13 ... Non-doped a-Si film, 14 ... First protective insulating film, 14a ... Protective insulating film, 15 ... Pixel electrode , 16 ……
Second protective insulating film, 17 ... through hole, 18 ... source contact hole, 19 ... drain contact hole, 20 ... n ⁺ a
-Si film, 21 ... Metal film, 22 ... Source electrode, 23 ... Drain electrode.

Claims (1)

(57) [Claims] 1. A step of forming a gate electrode and a gate bus line on an insulating substrate, a step of forming a gate insulating film, a non-doped amorphous silicon film, and a first protective insulating film in this order, and the first step. Patterning the protective insulating film and the non-doped amorphous silicon film so as to remain in the thin film transistor formation portion; forming a pixel electrode on the gate insulating film; forming a second protective insulating film covering the entire surface; A step of selectively etching the first protective insulating film and the second protective insulating film to form through holes on the pixel electrodes and source contact holes and drain contact holes on the non-doped amorphous silicon film; Form a two-layer film consisting of an amorphous silicon film containing impurities and a metal film The patterned source electrode, method of manufacturing a thin film transistor array, characterized by comprising a step of forming a drain electrode and wiring required, the.