JPS61145582A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device having a thin film transistor (hereinafter abbreviated as TPT) array.

[Prior Art] A liquid crystal display device generally has a structure in which a liquid crystal is sandwiched between two substrates. Electrodes and other elements are formed on the liquid crystal side of this substrate, and display is performed by controlling the state of the liquid crystal using the elements. Electrodes are uniformly formed on the surface of one of the two substrates, and a plurality of electrodes in a small block pattern (pixel) having an appropriate shape are formed on the surface of the other substrate. In recent years, a TFT array for switching each pixel has been attached to the surface of the substrate on the side of one pixel electrode. Figure 5 shows such a TF
1 is a schematic cross-sectional view of a TFT section of a liquid crystal display device having a T array, where S is a transparent substrate such as glass, 1 is a gate electrode, 2 is an insulating layer made of SiN:H or the like, and 3 is a semiconductor chip, 4 is an ohmic contact layer, 5 is a source electrode, 6 is a drain electrode, 7 is an inorganic insulating layer, 8 is an organic insulating layer, and 9 is a light shielding layer. Note that 10 is a pixel electrode for display, which is made of a transparent metal layer such as indium-tin oxide, tin oxide, or a thin gold film.

[Problems to be Solved by the Invention] FIG. 6 is a partial plan view of the TFT array, and FIG. 7 is a cross section thereof taken along line AA'.

The gate electrode 1 and the source electrode 5 are the gate line 1a and the source line 5a. Here, 20 is an intersection point 20 of the gate line la, the source line 5a, and the gate electrode l source electrode 5 or drain electrode 6, and is insulated by the insulating layer 2.

In the manufacturing of display devices as described above, defects and pinholes often occur in the insulating layer 2. If these defects occur at the crossing point 20, it will become a spot between the gate line 1a and the source line 5a, which will adversely affect the entire semiconductor 3 connected to the gate line 1a and the source line 5a from that point, and the line will be damaged. It was displayed as a defect.

The present invention has been made to solve the above problems,
The present invention provides a display device that can protect the TPT channel region at an early stage and provide good display.

[Means and effects for solving the problem] The present invention provides a gate insulating film and other inorganic insulating films between the gate line and source line of a thin film transistor array on the surface of a substrate, and a two-layer insulating film. The occurrence of short circuits between the gate line and the source line is significantly reduced because the thickness of the insulating film is increased compared to the conventional one.

Embodiment 1 FIG. 4 is a schematic cross-sectional view of a preferred embodiment of the display device of the present invention. Moreover, FIG. 4 shows the A-
This is the A' section (see Figure 5).

As the semiconductor layer 3 constituting the TPT, for example, Sf, C
dS, CdSe, CdTe, Te, etc. are used, and amorphous, polycrystalline, or fine-quality Si is particularly preferably used. Amorphous Sf can contain H atoms or l\rogen atoms (particularly Fg atoms). H atoms or halogens may be contained alone or both, and the content thereof is preferably 0.01 to 40 atomic% in total, more preferably 0.01 to 30 atomic%. .

In the device of the present invention, unlike the conventional device, as shown in FIG.
A gate insulating layer 2 and an inorganic insulating layer 7 are provided between the gate electrode 1, the source electrode 5, and the drain electrode 6, forming a two-layer living room insulating layer. This inorganic insulating layer 7 can be formed using an inorganic material such as a metal oxide, such as titanium oxide or alumina, or a silicon compound, such as silicon dioxide or silicon nitride, by a vapor deposition method, a sputtering method, a CVD method, or the like. Although it is preferable that the inorganic insulating layer is at least as thick as an interlayer insulating layer, the contact hole 11
In consideration of making contact between the ohmic contact M4 and the source electrode 5 and the drain electrode 6 through the ohmic contact M4 and protecting the channel portion of the TPT, preferably 50
It is about 0 to 3000A.

Next, an example of the manufacturing process of the above display device will be shown.

Example 1 Indiun-Tin-Oxid was placed on the glass substrate S.
After depositing E to a thickness of 0.3 microns, a pixel electrode 10 was formed by a normal photolithography process.Next, An was deposited to a thickness of 0.3 microns, and a gate electrode l was similarly formed by a normal photolithography process. Next, a Si3N4 film (insulating layer 2) was deposited to a thickness of 0.3 microns using the well-known glow discharge method.Next, an amorphous silicon layer (semiconductor layer 3) was deposited to a thickness of 0.5 microns using the same glow discharge method. After that, a 0.4 micron layer (ohmic contact layer 4) was similarly deposited and then etched using a normal photolithography process, leaving only the transistor section.

Next, Si3N4 ffI (inorganic insulating layer 7) was deposited to a thickness of 0.3 microns using a glow discharge method, and in order to conduct the ohmic contact layer 4 with the drain electrode 6, the pixel electrode 10, the source electrode 5, and the drain electrode 6, The contact hole 11 was etched using a normal photolithography process. Next, An was deposited to a thickness of 0.8 microns, and the contact hole 11 was etched using a normal photolithography process, leaving only the source electrode 5 and drain electrode 6. Next, an organic insulating layer 8 ( 1 CIDUR-110WR1 (product name) manufactured by Tokyo Ohka Co., Ltd.
Coated with micron and cured. Finally, add Al shading calendar 9 to 0.
A 1 micron layer was deposited and etched using a conventional photolithography process.

Here, as a result of investigating the occurrence rate of short circuit between the electrode 5 and the gate electrode l, it was 0.01% in the conventional TPT, but in the TPT of the present invention, o, ooot%
It was below.

Further, using the thus obtained display substrate, a liquid crystal device was fabricated through normal steps.

The thus obtained liquid crystal display device was placed in a high temperature and humid atmosphere (90℃
When operated continuously for 1000 hours at 90% R)f), it showed good display characteristics during operation.

Example 2 (Figure S2) On a glass substrate S, An was deposited to a thickness of 0.3 microns, and a gate electrode l was similarly formed using a normal photolithography process.Then, a well-known glow discharge method was used. Si3N
4 films (insulating films) were deposited to a thickness of 0.3 microns, and then an amorphous silicon layer 3 was formed using the same glow discharge method.
After forming a 0.3 micron thick film, a 0.1 micron film was formed in the same manner, and then an Indi film was etched by a normal photolithography process, leaving the transistor part.
After um-Tin-Uxide was deposited to a thickness of 0.3 microns, a pixel electrode 10 was formed by a normal photolithography process.Next, a Si3N4 film 7 was deposited to a thickness of 0.3 microns by a glow discharge method. In order to establish conduction between the electrode 6 and the pixel electrode 10, the source electrode 5 and the drain electrode 6, and the ohmic contact layer 4, a contact hole 11 is etched by a normal photolithography process. I left it and etched it.

Next, an organic insulating layer 8 (0DUR-110E manufactured by Tokyo Osha Co., Ltd.
R (trade name)) was applied and cured. Finally, AfL light-shielding M9 was etched using 0.1 mm. By adopting such a structure, the depth of the contact hole becomes the same at a shallow location, and the film thicknesses of the source 5 and drain electrodes can be made thinner.

Example 3 (Figure 3) Al was deposited to a thickness of 0.3 microns on a glass substrate S,
Similarly, the gate electrode 1 was formed using the normal photorin process, and then Si3N was formed using the well-known glow discharge method.
4 A film 2 (insulating film) was deposited to a thickness of 0.3 microns.Next, an amorphous silicon layer 3 was formed to a thickness of 0.5 microns by the same glow discharge method, and then a n0 layer 4 was deposited in the same manner.
Then, etching was performed using a normal photolithography process, leaving only the transistor part. Next, a Si3N4 film was deposited to a thickness of 0.3 microns using a glow discharge method.

Next 1. After evaporating Indium-Tin-Owide to a thickness of 0.3 microns, a pixel electrode was formed by a normal photolithography process.Next, in order to make the source electrode 5 and drain electrode 6 conductive to the ohmic contact layer 4, , the contact hole 11 was etched by a normal photolithography process, and then the AJL was etched to a thickness of 0, and the 6 mm electrode and drain electrode were etched. )) was applied and cured. Finally, the Al light shielding layer 9 is
．． Etching was performed using a 1-mimography process. This eliminates the need for some contact holes.

Although the liquid crystal display device has been specifically described above, the present invention can also be implemented in similar display devices such as the ferroelectric liquid crystal device disclosed by Clark et al. (US Pat. No. 4,367,924). .

[Effects of the Invention] As described above, according to the present invention, the operating characteristics of the TPT can be improved, and the reliability and manufacturing yield of the TPT can also be improved.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing various embodiments of TPT-formed substrates in the display device of the present invention, FIG. 5 is a cross-sectional view showing an example of the TFT portion of a conventional liquid crystal display device, and FIG. is its plan view, and FIG. 7 is its AA' cross section. l...Gate electrode, la...Gate line 2...Insulating layer, 3...Semiconductor layer 4...Ohmic contact layer 5...Source electrode, 5a...Source line 6... Drain electrode, 7... Inorganic insulating layer 8... Organic insulating layer, 9
... Light shielding layer 10 ... Pixel electrode, 11 ... Contact hole 20
...Intersection of gate, source and drain electrodes Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5

Claims (1)

[Claims] A display device characterized in that a gate insulating film between a gate wiring and a source wiring of a thin film transistor array and another inorganic insulating layer are provided on a substrate surface to form a two-layer interlayer insulating film.