JPS6235669A - Thin film transistor matrix array panel and manufacture of the same - Google Patents

Abstract

PURPOSE:To eliminate a masking process and reduce the cost by a method wherein the semiconductor films of all the thin film transistors connected to one drain electrode wiring are not isolated planarly from each other and provided in common with the drain electrode wiring. CONSTITUTION:Gate electrodes 102 made of Cr are formed on an insulating substrate 101 made of a sodium glass coated with SiO by patterning. An SiN gate insulation film 103 and a semiconductor film 104 consisting of an I-type layer and an N<+> type 105 are formed on the substrate 101 by plasma CVD and further Cr wiring metal layers 106 for a drain electrode 108 and a source electrode 110 are formed. The Cr wiring metal layer 106 is continuously provided as far as a drain terminal electrode 109 on the extension of the drain electrode 108. The semiconductor film 104 is selectively removed by etching except the semiconductor region 113 including the region to be a TFT 112 and a drain electrode wiring region. An ITO film 107 is formed on the Cr wiring metal layers 106 and on the SiN gate electrode 103 remaining on the region to be a display electrode 111 and a required pattern is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor matrix array panel used in active matrix liquid crystal display devices and the like, and a method for manufacturing the same.

[Conventional technology]

Thin film transistors (TPTs) have the advantage of being able to be formed on insulating substrates such as glass at low temperatures, and various applications are being considered for their use in differential chairs. In particular, in recent years T
Increasingly, PT is formed into a matrix play shape and used as a switching array for liquid crystal display elements.

Fig. 4(,) shows a schematic plan view of a part of a 74-channel matrix array using a-8i TFTs, and Fig. 4(b) is a schematic cross section taken from the A-A' break line in (a). Show the diagram.

Conventionally, an a-8i TFT matrix array panel was created and constructed as follows. That is, Fig. 4 (a
), (b), an insulating substrate 401 such as glass
A wiring metal such as chromium is deposited thereon and patterned to form a gate electrode 402.

Next, silicon nitride (SIN) or the like is deposited on the substrate 401 on which the gate electrode 402 is formed by plasma CVD.
An a-St insulating film 403 and an a-St semiconductor film 404 are sequentially deposited. The a-8i film has an n+ layer (n+
It has two layers including a semiconductor layer 405). The n+ semiconductor layer 405 is provided to improve ohmic contact with the source/drain electrodes, and may not be provided in some cases. Next, to matrix TPT, each T
For each location where a PT is provided, the deposited semiconductor film 404 is masked and removed by etching to provide two-dimensional insulation isolation. As a result, the gate insulating film 403 remains in the deposited region, but the region where the semiconductor film 404 exists is T
This is a semiconductor region 413 that will become a FT 412. Note that etching residue 415 may be left at the end of the deposited region due to the mask pattern. Further, if the semiconductor region 413(f-) is extended to the toilet where the electrode 402 and the drain pass line 416 intersect, the insulation between the electrodes can be improved. As the next step, a drain electrode wiring metal 406 is deposited, and a source electrode 410, a drain electrode 408, and a drain pass line 416 are formed/turned. At this time, not only the wiring metal 406 but also the unnecessary n semiconductor layer 405 in the TPT 412 portion is etched away using the same mask.

Next, a conductive film such as an indium tin oxide film (ITO film) 407 is deposited to form a display electrode 411, and the matrix-shaped display electrode 411 serves as the source electrode 410 of the TFT 412.
Carry out 4 turnings of the shape connected to. At this time I
If the TO film 407 is removed by etching using a mask pattern that also remains on the drain electrode 408, drain pass line 416, and drain terminal [pole 409], the drain wiring resistance can be reduced. TP created through the above process
The T matrix array/mother channel has a cross-sectional structure as shown in FIG. 4(b).

[Problem that the invention seeks to solve]

However, the TPT matrix array panel having the above-described structure and manufacturing method has the disadvantage that the manufacturing process is complicated and requires a large number of man-hours, and due to the structure, display line defects due to broken wires are likely to occur. These drawbacks are due to the fact that the semiconductor film is separated and insulated in a plane due to the structure in which the TPTs are provided in a matrix array.

In the conventional TPT matrix array/4-channel structure as described above, at least a mask process for forming a gate electrode, a mask process for separating and insulating the semiconductor in a plane, a mask process for forming a drain electrode, and a mask process for forming a display electrode are performed. A masking process and four masking processes were required, which required a large number of man-hours and was complicated. Further, one drain pass line must connect the semiconductor film steps as many as the number of TFTs which are provided separately in a plane, and there is also the problem that wiring breaks are likely to occur.

When such a TPT matrix array panel is used as a display device, broken wires appear as line defects in the display, resulting in a significant deterioration in display quality.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a thin film transistor matrix array panel that requires fewer manufacturing steps and has an excellent manufacturing yield, and a method for manufacturing the same.

[Means for solving problems]

A first invention for solving the above-mentioned problems is that a plurality of gate electrode wirings and drain electrode wirings are arranged in a matrix array on an insulating substrate, insulated from each other, and a plurality of gate electrode wirings and drain electrode wirings are arranged in the vicinity of the intersection of the two wirings. 1. A panel on which thin film transistors are arranged, characterized in that the semiconductor films of all the thin film transistors connected to one drain electrode wiring are provided in common with the drain electrode wiring instead of being insulated and separated in a plane. This is a matrix array with 74 channels.

Further, in order to solve the above-mentioned problems, the method provided by the second invention includes a step of sequentially depositing a gate insulating film, a semiconductor film, and a metal film for wiring on the surface of an insulating substrate on which a gate electrode wiring is formed. , a step of sequentially etching away the metal film for wiring and the semiconductor film using a mask that includes a region where all thin film transistors to be connected to one drain electrode wiring are provided and a drain electrode wiring region; This method of manufacturing a thin film transistor matrix array panel includes the step of etching an unnecessary film in a channel portion of the thin film transistor using a mask formed with electrodes separated from each other.

[For production]

According to the method of manufacturing a thin film transistor matrix array panel of the present invention, it is possible to omit a mask process for separating and insulating semiconductors in a plane, and it is possible to significantly shorten the manufacturing process and reduce manufacturing costs.

Moreover, the thin film transistor matrix areno! of the present invention!
In the channel, by using the above method, the thin film transistors that are not isolated in a plane are connected to one drain electrode wiring, so there is no influence on the characteristics between the individual thin film transistors.

Furthermore, in the thin film transistor matrix areno (Nel) of the present invention, by using the above-mentioned means, the semiconductor film is also commonly present in the drain electrode wiring region without being separated, so that the step difference corresponding to the number of elements is reduced. The electrode wiring is significantly planarized, and the defective rate due to wire breakage can be significantly improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) Figure 1 (,) shows the configuration of an example of the present invention.
A schematic plan view of a portion of a matrix array 74 channel,
(b) is a schematic sectional view taken along the AA' break line in (,).

1(a) and 1(b), a gate electrode 102 made of Cr is formed on an insulating substrate 101 made of sio-coated soda lath. It has been turned. SiN formed on this using plasma CVD
gate insulating film 103 and 1 layer and n+ (semiconductor) layer 10
A semiconductor film 104 of a-St:H is provided. Furthermore, a Cr wiring metal 106 for a drain electrode 108 and a source electrode 110 is provided on this.

The Cr wiring metal 106 is also formed on the insulating substrate 101 in a region where the semiconductor film 104 is not provided, and is continuously provided as a drain terminal electrode 109 on an extension of the drain electrode 108. The semiconductor film other than the semiconductor region 113 (the region indicated by the broken line in the figure) including the region to become the TFT 112 and the drain electrode wiring region is removed by etching. On the Cr wiring metal 106 and the display electrode 111
An ITO film 107 is provided on the SiN gate insulating film 103 remaining in the region to form a desired pattern. The pattern of the ITO film 107 is such that the display electrode 111 and the source electrode 110 of the TFT 112 are connected, and the drain electrode 108 and the drain terminal electrode 109 are continuous. There is a gap between In addition, the channel part of TFrl12 is covered with the ITO film 10.
7. The Cr wiring metal 106 and the n+ semiconductor layer 105 are removed, leaving one layer of the semiconductor film 104 exposed.

As a result of measuring the individual TF'T% properties of the TPT matrix array i4 channel of the present invention having the above structure,
It was confirmed that there was no influence between the TPTs in the matrix, and that the TPTs could be operated for each display electrode. This is because when looking at the layout relationship between the gate electrode and the TPT for TPT switching operation, the semiconductor film of the TPT on the gate electrode wiring is separated, and the gate electrode of the TPT on the drain electrode wiring is independent. This was the effect of Furthermore, the display results of the liquid crystal display using this TPT matrix array/mother panel were exactly the same as those of the insulation separation method in which all the TPTs were isolated in a matrix. This is a so-called line-sequential method in which a display timing signal is sequentially input to each gate line for switching in a liquid crystal display, so even if a TPT is provided in common in the drain direction, the switching timing is different, causing a problem. do not have.

In this way, the TPT matrix array 11 of this embodiment can obtain equivalent operation without completely insulating and separating each TPT in the matrix array? The following advantages can be obtained in the channel. First, there is no need for a mask or a nocturning process for insulating and separating the TPTs into isolated islands, and the manufacturing cost can be reduced accordingly. In addition, there is no need to conduct drain electrode wiring on isolated island-shaped TPTs, and since the semiconductor film under one drain electrode wiring is continuous, there are fewer steps, significantly reducing wiring disconnections, and improving manufacturing yield. improvement can be achieved.

(Example 2) Figures 2 (&) to (d) are schematic cross-sectional views of a part of the mother panel in the manufacturing process of the TPT matrix array panel, and Figures 3 (,) to (d) are It is a schematic plan view of a part of Gunnel in that process. (&) to (d) in FIGS. 2 and 3 are opposed to each other, and FIG. 2 illustrates a cross section taken along the line A-A' in FIG. 3.

In FIGS. 2(a) and 3(a), Cr for the r-meter electrodes 202 and 302 is placed on an insulating substrate 201 such as glass.
10,001 layers are deposited, and - mother turning is performed [step (a)].

After that, in FIGS. 2(b) and 3(b), the SIN for the gate insulating film 203 is formed using plasma CVD.
was deposited at 3000X, and the semiconductor film 2 was subsequently deposited in the same equipment.
One layer of -81:H for 04 is deposited at 3000X and an H layer is deposited at 500X on a-8 in which the n semiconductor layer is doped with phosphorous [Step (b)]. The surface of the gate insulating film, the semiconductor film, and the n
The area on the surface of the semiconductor layers 205 and 305 that will become the terminal portion around the insulating substrate is the substrate surface. Next, in FIGS. 2(C) and 3(,), 20,001 Cr, which will become wiring metals 206 and 306 for drain electrodes, is deposited on this surface in a separate process, as shown in FIG. 3(e). Note that Cr is etched using a mask pattern (shaded area) of the wiring metals 206 and 306 that includes a TPT region where the drain electrode wiring and the drain electrode terminal are continuous and where the drain electrode and the source electrode are continuous. Using the same mask pattern, a H film is deposited on a-8 of the semiconductor film 204 deposited by plasma CVD (step (b)).

The n+ (semiconductor) layers 205, 305 and the first layer are removed by etching [Step (C)]. As a result, plasma CVD
A-8i: H film (n+
The semiconductor film region 313 where the layer + i layer) remains is Cr wiring gold J! It is the same as i 306, and is the shaded area in FIG. 3 (, ).

In FIG. 2(d) and FIG. 3(d), an ITO film 207 is then placed on this surface as a conductive film for the display electrode 311.
307 is deposited to form a pattern as shown in FIG. The ITO films 207 and 307 are etched using a material separated by a distance. Subsequently, using the same mask, the Cr film of the wiring metal 306 existing in the channel part of the TFT 312 and the semiconductor film 3 are removed.
Unnecessary films such as the a-8i:Hn+ layer of the n+ (semiconductor) layer 305 of 04 are removed by etching [step (d)]. In these etching steps, ITO etchant and C
Since the r etchant and the a-Si:H film etchant or their etching have a sufficient selectivity with respect to 5iN (C), the gate insulating film 303 remains in all the regions deposited by plasma CVD. , TFT
In the 312 region, the channel portion is located at a-8 of the semiconductor film 304.
t: The i-layer of the H film is exposed.

As mentioned above, in the case of this embodiment, basically the r-meter electrode i4? Turning process (a), drain electrode and TPT
It only requires three mask steps: the integrated patterning step (c), and the turning step (d) for display electrodes and TPT channels, eliminating the need for a mask for the conventional TFT mask IJ hook separation step. This results in a significant reduction in man-hours and manufacturing costs.

Furthermore, although the ITO film on the drain electrode is essentially unnecessary, if the above mask is used, the ITO film on the drain electrode 2
08, 308 and the drain terminal electrode 209. The drain terminal electrode 209 and the drain terminal electrode 309 are made of a three-layer film of an n''a-8T film, a Cr film, and an ITO film.
Contributes to lower wiring resistance and fewer disconnections. In addition, one drain electrode 208 and a TFT 31 connected to the 308 wiring.
The two semiconductor films 204 and 304 are individually separated,
As a result of the common presence under the drain electrode, the level difference and the number of level differences in the drain electrode wiring were significantly reduced. therefore,
Compared to the conventional method of insulating and separating each TPT, which causes a step of about 3000× of the semiconductor film thickness, in this example, the step is only about 1000× of the gate film thickness, which prevents disconnection of the drain electrode wiring. It can be done very little.

Further, since both the single semiconductor layer and the gate insulating film remain under the drain electrode wiring, the insulation at the matrix intersection between the gate electrode wiring and the drain electrode wiring is also high.

〔Effect of the invention〕

As explained in detail above, in the TPT matrix array/bus channel and the manufacturing method thereof of the present invention, the TPTs are not all independently insulated and separated, but the TPTs are aligned in the direction of one drain electrode wiring.
Since the PT semiconductor film is provided in common, the number of mask steps can be reduced and manufacturing costs can be reduced. In addition, since the level difference and the number of level differences in the drain electrode wiring are significantly reduced, there are extremely few disconnections, and it is possible to improve the manufacturing yield and the quality of display devices and the like. Furthermore, since the TPTs are not separated in the direction of the drain electrode and separated in the direction of the gate electrode, there is no influence between the TPTs in the matrix. Note that since both the single semiconductor layer and the gate insulating film remain under the drain electrode wiring, the insulation at the matrix intersection between the gate electrode wiring and the drain electrode wiring is also high.

[Brief explanation of drawings]

Figure 1 (,) is a schematic plan view of a part of an embodiment of the present invention, (b) is a schematic sectional view taken along the A-A' break line in (,), and Figures 2 (,) - (d) shows an example of the manufacturing method of the present invention in the order of manufacturing steps. A part of the motherboard is schematically shown, and is a sectional view taken along the line A-A' in FIGS. 3(a) to (d), respectively. FIGS. 3(a) to 3(d) are schematic plan views of a part of the panel in the process shown relative to FIGS. 2(a) to (d), and FIG. 4(, ) is a conventional example. A schematic plan view of a part of the panel for explaining the
- It is a schematic cross-sectional view seen from the A' break line. In the figure, 101, 201 are insulating substrates, 102°202, 302 are gate electrodes, 103, 203,
303 is a gate insulating film, 104, 204, 304 is a semiconductor film, 105°205, 305 is an n semiconductor layer, 1
06, 206, 306 are wiring metals, 107, 20
7, 307 is an I'rO film, 108, 208. 308 is a drain electrode, 109, 209, 309 are terminal electrodes, 110, 310 are source electrodes, 111,
311 is a display electrode, 112 and 312 are TPT, 1
13, 313 is a semiconductor film region, 314 is a plasma CV
D laminated deposition area, 415 indicates etching residue, respectively.

Claims (2)

[Claims] (1) In a panel in which a plurality of gate electrode wirings and drain electrode wirings are insulated from each other and arranged in a matrix array on an insulating substrate, and a thin film transistor is arranged near the intersection of the two wirings, one A thin film transistor matrix array panel characterized in that the semiconductor films of all the thin film transistors connected to the drain electrode wiring are provided in common with the drain electrode wiring without being isolated in a plane. (2) In a manufacturing method in which a plurality of gate electrode wirings and drain electrode wirings are insulated from each other and arranged in a matrix, and a thin film transistor is provided near the intersection of the two wirings, the surface of an insulating substrate on which the gate electrode wirings are formed. A process of sequentially stacking a gate insulating film, a semiconductor film, and a metal film for wiring, and wiring using a mask that includes a region where all thin film transistors to be connected to one drain electrode wiring are provided and a drain electrode wiring region. A thin film transistor matrix comprising: a step of sequentially etching away a metal film and a semiconductor film; and a step of etching an unnecessary film in a channel portion of the thin film transistor using a mask formed to separate a source electrode and a drain electrode. Method for manufacturing array panels.