WO2014176876A1

WO2014176876A1 - Display panel and manufacturing method therefor, and liquid crystal display

Info

Publication number: WO2014176876A1
Application number: PCT/CN2013/085497
Authority: WO
Inventors: 徐向阳
Original assignee: 合肥京东方光电科技有限公司; 京东方科技集团股份有限公司
Priority date: 2013-05-03
Filing date: 2013-10-18
Publication date: 2014-11-06
Also published as: CN103278989A; CN103278989B

Abstract

A display panel comprises a gate line peripheral routing area provided with a gate line peripheral routing, wherein the gate line peripheral routing comprises a first routing (201), a gate line insulation layer (202) and a second routing (203) which are formed on a substrate in sequence. The gate line insulation layer (202) is provided with at least one first opening (310), and the first routing (201) is electrically connected to the second routing (203) through the first opening (310). The display panel can reduce the resistance of the gate line peripheral routing, reduce the signal attenuation and delay, and improve the display effect.

Description

Display panel and manufacturing method thereof, liquid crystal display

Embodiments of the present invention relate to a display panel, a method of fabricating the same, and a liquid crystal display. Background technique

A thin film transistor liquid crystal display (TFT-LCD) is a liquid crystal display device driven by a semiconductor device. Depending on the panel driving electric field, TFT-LCD can be classified into a twisted nematic type, a vertical alignment type, an in-plane switching (IPS) type, and a fringe field conversion (FFS) type. Although the form of the electric field for driving the liquid crystal is different, the panel charges and discharges the pixel capacitance by progressive scanning, thereby deflecting the liquid crystal to control the light field of the backlight. The scan signal and the drive voltage are generated by the gate integrated circuit and the driver integrated circuit, respectively. The control signal of the gate integrated circuit is generated by a Timing Controller chip and transmitted to the gate integrated circuit via a panel Layout Gate.

At present, a single layer of metal traces is used for the peripheral traces of the TFT-LCD array substrate. For panels with low resolution and low frame refresh rate, the signal delay of the line has no effect on the display due to the lower frequency. As the requirements for display resolution continue to increase, the frequency of the signal is also increasing. For panels with high frame refresh rates, the delay and attenuation of the signal in the line cannot be ignored. There are two main reasons for the delay of the line: on the one hand, the signal trace resistance of the line; on the other hand, the coupling capacitance of the line. The coupling capacitance is generated between the different metal lines on the reverse side; and the resistance is determined by the characteristics of the metal trace itself, mainly depending on the resistivity, cross section and wiring length of the metal trace. Common wiring metal materials include: aluminum, molybdenum, copper, indium tin oxide (ITO), and the like. In terms of electrical conductivity, copper is the best but the highest cost, and the process is the most difficult.

Therefore, for panels with high resolution and high frame rate refresh, the resistance of the outer traces of the gate lines increases the attenuation and delay of the signal, reducing the display effect. Summary of the invention

Embodiments of the present invention provide a display panel, a manufacturing method thereof, and a liquid crystal display, which are used for The resistance of the traces on the periphery of the low gate line reduces signal attenuation and delay, improving display performance.

An embodiment of the present invention provides a display panel including a gate line peripheral trace region provided with a gate line peripheral trace, wherein the gate line peripheral trace includes a first trace sequentially formed on the base substrate a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening.

Another embodiment of the present invention provides a liquid crystal display including the display panel.

A further embodiment of the present invention provides a method for fabricating a display panel, the display panel including a display area and a gate line peripheral routing area, and the manufacturing method includes: on a base substrate in a peripheral line area of the gate line Forming a first trace for the gate line peripheral traces, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, the first trace and the second trace The wires are electrically connected through the first opening. DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in detail with reference to the accompanying drawings, in which FIG.

1 is a schematic diagram of an array of anti-peripheral circuits of a liquid crystal display panel;

2 is a schematic diagram of a peripheral trace of a gate line according to an embodiment of the present invention;

3 is a schematic structural diagram of a peripheral trace of a gate line according to an embodiment of the present invention; FIG. 4 is a schematic diagram of processing and forming of a mask provided by a specific embodiment of the present invention.

Reference mark:

100: electrostatic ring short circuit; 101: gate line; 102: terminal area; 103: common electrode; 104: electrostatic ring; 105: pixel drive chip; 106: gate integrated circuit; 107: data line; 108: gate line Peripheral routing; 109: Display area. detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, rather than all of the embodiments. Based on the described embodiments of the present invention, those of ordinary skill in the art can obtain without the need for creative labor. All other embodiments obtained are within the scope of the invention.

Unless otherwise defined, technical terms or scientific terms used herein shall be of the ordinary meaning understood by those of ordinary skill in the art to which the invention pertains. The words "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Similarly, the words "a", "an" or "the" do not mean a quantity limitation, but rather mean that there is at least one. The word "comprising" or "comprises" or the like means that the element or item preceding the word is intended to encompass the element or item recited after the word and its equivalent, and does not exclude other element or item. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "Down", "Left", "Right", etc. are only used to indicate relative positional relationship. When the absolute position of the object being described is changed, the relative positional relationship may also change accordingly.

Embodiments of the present invention provide a display panel and a method for fabricating the same, and a liquid crystal display for reducing resistance of a peripheral trace of a gate line, reducing signal attenuation and delay, and improving display performance.

1 is a schematic diagram of a peripheral circuit of an array substrate of a liquid crystal display panel (for example, a TFT-LCD panel). The primary function of the gate line outer traces 108 is to transmit control signals to the gate integrated circuit 106. The display panel includes a display area 109 at the center and a peripheral area outside the display area 109. The display area 109 includes a plurality of gate lines 101, a plurality of data lines 107, and a plurality of pixel units defined by the intersection of the gate lines 101 and the data lines 107. For example, each pixel unit includes a thin film transistor (TFT) as a switching element, and a gate of the thin film transistor is electrically connected or integrally formed with a corresponding gate line, and a source of the thin film transistor is electrically connected or integrally formed with a corresponding data line, and the thin film The drain of the transistor is electrically connected or integrally formed with the corresponding pixel electrode. The peripheral area includes the peripheral line of the gate line where the gate line outer trace 108 is located, and other areas in the vicinity (e.g., the terminal area 102, etc.). The gate integrated circuit 106 is for applying a gate scan signal to the gate lines in the display area 109. In addition, the liquid crystal panel may further include other components or structures such as the electrostatic ring short circuit 100, the terminal region 102, the common electrode 103, the electrostatic ring 104, and the pixel driving chip 105.

An embodiment of the present invention provides a structure of a gate line peripheral trace of a display panel, wherein a gate line peripheral trace of the liquid crystal panel includes a first trace sequentially formed on a base substrate for a peripheral trace of the gate line, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening. At least one first opening in the gate insulating layer is exposed to a first trace under the gate insulating layer to enable the first and second traces to Electrically connected to each other, thereby reducing the overall resistance of the outer traces of the gate lines.

Since the peripheral trace of the gate line is only used as a wire, the intermediate layer of the active layer in the peripheral trace area of the gate line is etched and removed during the fabrication process, or, for example, there are The intermediate layers of the source layer are all removed, for example by etching. In addition to the active layer, the intermediate layer may be, for example, an interlayer insulating layer separating the pixel electrode layer and the source/drain metal layer.

For example, the first trace may be formed simultaneously with the gate line, and the second trace may be formed simultaneously with the source drain electrode or the pixel electrode. When the second trace is formed simultaneously with the pixel electrode and the pixel electrode is formed on the intermediate layer, the first opening also passes through the intermediate layer to expose the first trace under the intermediate layer.

For example, the total length of the first opening may be greater than one-half of the length of the outer trace of the gate line, that is, more than half of the outer traces of the gate line are exposed. In order to maintain good electrical conductivity, sufficient contact is required between the first trace and the second trace, and the larger the contact area of the two, the lower the overall resistance of the resulting trace of the peripheral trace of the gate line. The first opening may be formed in the peripheral wiring area of the entire gate line, thereby exposing the entire peripheral line of the gate line; or the first opening may be formed continuously or at intervals only in the peripheral line area of the partial gate line, that is, The first opening may not be limited to one. When the first opening is formed only in the peripheral wiring region of the partial gate line, or the gate insulating layer in the peripheral wiring region of the partial gate line is not completely etched during the fabrication process, the peripheral trace of the gate line may be at least two points. One of the regions is formed such that the first trace and the second trace can be electrically connected directly.

For example, the display panel gate line peripheral trace region may further include an insulating protective layer formed on the base substrate and a third trace above the insulating protective layer. The third trace may be formed simultaneously with the pixel electrode formed on the insulating protective layer, and at this time, the second trace is formed, for example, simultaneously with the source and drain electrodes.

For example, at least one second opening may be formed in the insulating protective layer, and the third trace and the second trace are electrically connected through the second opening. The second opening is exposed to a second trace below the insulating protective layer. If the three conductive layers of the first trace, the second trace, and the third trace are electrically connected to each other, the obtained trace of the peripheral trace of the gate line is better, and the overall resistance is lower.

For example, the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line. Similar to the first opening, in order to maintain good electrical conductivity, sufficient contact is required between the second trace and the third trace. The second opening may also be not limited to one.

For example, in a direction perpendicular to a base substrate (eg, a glass substrate) of the display panel, the first opening and the second opening may be in the same position; that is, the second opening is located above the first opening. However, it is not required that the first opening and the second opening necessarily have the same outer shape. A liquid crystal display provided by an embodiment of the present invention includes the display panel; a gate line peripheral trace of the display panel connects the timing control chip and the gate integrated circuit.

Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:

S201, forming a gate line and a gate in a display area on the opposite side of the substrate, and forming a first trace in the peripheral line area of the gate line;

5202, sequentially forming a gate insulating layer and an active layer, and forming at least one first opening in the peripheral wiring region of the gate line to expose the first trace;

5203, forming a source/drain metal layer on the active layer, and forming a second trace at at least the first opening in the peripheral trace region of the gate line, wherein the second trace passes through the first opening and the first A wired electrical connection.

The base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate. The above embodiment has been described by taking a bottom gate type display panel as an example, but the present invention is not limited thereto.

In this embodiment, the first trace needs to be directly electrically connected to the second trace. Therefore, in the peripheral wiring region of the gate line, the gate insulating layer and the active layer between the first trace and the second trace need to be etched away to form the first opening of the first trace exposed The gate insulating layer and the active layer at other positions in the peripheral region of the gate line can be removed or etched as needed.

In one example, forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral line region of the gate line includes: forming a gate insulating layer and a gate in a peripheral region of the gate line Forming a first opening in the pole insulating layer; forming an active layer and removing the active layer or all active layers at the first opening in a peripheral wiring region of the gate line. That is, in the latter case, the gate insulating layer near the peripheral wiring region of the gate line is left, and the entire active layer of the gate wiring peripheral wiring region and its vicinity is etched away.

In one example, forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral wiring region of the gate line includes: forming a gate insulating layer; forming an active layer and surrounding the gate line The wiring region forms at least one first opening; the gate insulating layer and the active layer corresponding to the first opening are both removed by etching, for example. Etching the gate insulating layer and the active layer may include simultaneously etching away all of the gate insulating layer and the active layer of the gate wiring peripheral region and the vicinity thereof, or simultaneously etching away the gate wiring in the peripheral routing region a gate insulating layer and an active layer. In addition, you can also use the square of the gray scale mask. By successively performing the etching twice by the same gray-level mask, the gate insulating layer near the first opening in the peripheral wiring region of the gate line can be preserved while etching the active layer outside the display region.

For example, the total length of the first opening may be greater than one-half of the length of the outer trace of the gate line. When the second trace is formed through the pixel electrode layer, step S203 may be: forming a pixel electrode layer on the active layer, and then forming a second trace at at least the first opening in the peripheral trace region of the gate line, where The second trace is electrically connected to the first trace through the first opening. In this example, the source and drain electrodes may be formed before or after the pixel electrode, and the two may be in direct contact, or an insulating layer may be formed therebetween and electrically connected to each other through via holes in the insulating layer.

The method of the above embodiment using the source/drain metal layer to form the second trace can also continue as follows:

5204, forming an insulating protective layer on the source/drain metal layer;

5205. Form a pixel electrode layer on the insulating protective layer.

At this time, the pixel electrode is formed over the insulating protective layer, and is electrically connected to one of the source and drain electrodes through a via hole in the insulating protective layer. In an example, in step S204, after forming an insulating protective layer on the source/drain metal layer, at least one second opening is formed in the insulating protective layer in the peripheral wiring region of the gate line to expose the second trace below; When the pixel electrode layer is formed on the insulating protective layer, a third trace is formed at the second opening of the peripheral wiring region of the gate line.

Therefore, in the embodiment of the present invention, the two wires of the first wire and the second wire may be used to transmit signals, or the first wire, the second wire, and the third wire may be used. Transmission signal. The metal layers are in contact with each other, which can increase the cross-sectional area of the metal layer and reduce the trace resistance at the periphery of the gate line.

For example, the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line. 2 is a schematic diagram of a gate line peripheral trace of one embodiment of the present invention, and only the gate line peripheral trace shown in the figure includes three traces (wires) parallel to each other, but the present invention is not limited thereto. 3 is a cross-sectional view of a trace of FIG. 2 taken along the line AA of the drawing in an example, the structure of the trace comprising: a glass substrate 200 as a base substrate; a first walk formed on the glass substrate 200 a wire 201; a gate insulating layer 202 formed on the glass substrate 200, the gate insulating layer 202 having a first opening 310 to expose the first trace 201; and a second trace 203 passing through the first opening 310 and the first The wiring 201 is electrically connected; an insulating protective layer 204 is formed on the second trace 203, the insulating protective layer 204 has a second opening 320 to expose the second trace 203; and a third formed on the insulating protective layer 204 The trace 205 is electrically connected to the second trace 203 through the second opening 320. The gate line peripheral traces in this example include three layers of traces electrically connected to each other, and the active layer is completely removed in the gate line peripheral traces.

In the embodiment of the present invention, each layer pattern includes, but is not limited to, the form of FIG. 3. Each layer may also be patterned (eg, etched) into other graphic patterns, and only needs to ensure that the three layers of metal can be sufficiently contacted to form an electrical connection. .

For the example shown in FIG. 3 above, each layer of the peripheral line area of the gate line corresponds to the following steps in the production process of the display panel:

1. Forming a gate metal film on the base substrate, then patterning the gate metal film to form a gate line, a gate electrode of the thin film transistor in the display region, and forming a first trace 201 in the peripheral trace region of the gate line;

2. Forming a gate insulating film, and then patterning to form a first opening 310 in the gate insulating layer 202 in the peripheral wiring region of the gate line, the first opening 310 exposing at least a portion of the first trace 201;

3. forming an active layer film, then patterning the active layer film to form an active layer of the thin film transistor in the display region and removing the active layer film in the peripheral wiring region of the gate line, exposing the first opening 310 and First line 201;

4. Forming a source/drain metal film, then patterning the source/drain metal film to form a source/drain electrode and a data line of the thin film transistor in the display region, and forming a second trace 203 in the peripheral trace region of the gate line, the second The trace 203 is electrically connected to the first trace 201 through the first opening 310;

5. Forming an insulating protective film, and then patterning the insulating protective film to form a pixel electrode via hole in one of the source/drain electrodes in the display region, and forming a second opening in the insulating protective layer 204 in the peripheral wiring region of the gate line 320, the second opening 320 exposes at least a portion of the second trace 203;

6. Forming a pixel electrode film, then patterning the pixel electrode film to form a pixel electrode in the display region, forming a third trace 205 in the peripheral trace region of the gate line, the pixel electrode passing through the pixel electrode via and the source/drain electrode An electrical connection, the third trace 205 is electrically connected to the second trace 203 through the second opening 320.

Referring to Figure 4, a schematic diagram of the processing of the masks corresponding to steps 1-2 and 4-5 is performed. Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:

S301, forming an active layer on the base substrate;

S302, forming a source/drain metal layer on the base substrate, thereby forming an active region in the display region a source drain electrode and a data line on the layer, forming a first trace in a peripheral trace region of the gate line;

5303, forming a gate insulating layer on the source/drain metal layer, forming a first opening in the gate insulating layer of the peripheral portion of the gate line, the first opening exposing at least a portion of the first trace;

5304, forming a gate metal layer on the gate insulating layer, thereby forming a gate and a gate line in the display region, and forming a second trace in the peripheral trace region of the gate line, the second trace passing through the first opening The first trace is electrically connected.

The base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate. The above embodiment has been described by taking a top gate type display panel as an example, but the present invention is not limited thereto.

In the above example, the method of the embodiment of the present invention can etch all the active layer of the gate line and the active layer in the vicinity of the gate line when the active layer is patterned, and the same active process as that of the conventional display panel can be used. Layer mask. For example, the patterning of the active layer is performed between the patterning of the gate insulating layer and the source/drain metal layer. If the peripheral wiring region of the gate line only removes the active layer at the first opening, the active layer mask used is different from that used in the process of fabricating the conventional display panel, and remains in the periphery of the gate line in the corresponding patterning process. The active layer in the trace area.

In the above embodiment, the first opening is formed by changing the gate insulating layer to form the first opening therein and the second opening is formed therein by changing the insulating protective layer mask, and the first to the second opening are connected through the first and second openings The three-layer metal traces are used to obtain the peripheral traces of the gate lines, thereby achieving the purpose of reducing the trace resistance of the gate lines.

In summary, the embodiments of the present invention provide a display panel, a method for fabricating the same, and a liquid crystal display device, which can reduce the resistance of the peripheral lines of the gate line, reduce signal attenuation and delay, and improve the display effect.

The above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims.

Claims

Claim

11. One type of display panel panel, wherein the package comprises a grid line outside the grid line outside the grid line outside the gate line, and Wherein, the outer peripheral routing component of the gate line includes a first one of the first traces formed on the base substrate substrate in sequence, Gate gate is absolutely insulating layer layer and the first

55二二走线线;; The gate-gate insulating layer layer package includes at least one first first opening opening, wherein the first one is taken The wiring line is electrically connected to the second and second open traces of the second through the first open opening. .

11. The display panel of the display panel as recited in claim 11, wherein the outer circumference of the grid line is further included The insulating edge protection layer and the third third trace above the protective insulating layer on the insulating layer. .

33. The display panel of the display panel as recited in claim 22, wherein the insulating barrier layer comprises at least one less than one a second opening opening, wherein the third third walking line and the second second walking line pass through the second second opening The electrical connection is connected. .

44. The display panel of the display panel as recited in claim 33, wherein the total length of the second opening of the second opening is greater than One or two-half of the length of the long line is taken around the outer periphery of the grid line. .

55. The display panel of the display panel of any one of the preceding claims, wherein the first opening of the first opening is The total length of the total length is greater than one-half of the length of the length of the outer circumference of the grid line. .

1155. The display panel of the display panel as recited in claim 11, wherein the outer periphery of the grid line further comprises a package And a middle intermediate layer, wherein the first open opening further passes through the middle intermediate layer. .

77. A liquid crystal display device, wherein the package comprises a display panel panel as described in any one of claims 11-66. .

88. A method for manufacturing a display panel panel, wherein the display panel comprises a display area and a peripheral line of the grid line. District, the production method package includes:

2200 is formed on the base substrate substrate board in a peripheral line around the outer periphery of the gate line to form a space for the outer periphery of the gate line a first one of the wire, a gate gate insulating layer, and a second second wire; the gate gate insulating layer layer package includes Enclosing at least one of the first open openings, wherein the first first walking line and the second second walking line pass through the first One by one open the port electrical connection. .

99. According to the system of production rights according to the rights and interests of the claim, the package includes:

Forming gate gate lines and gate gates in the display display region on the base substrate substrate board, as described above The grid line outside the grid 2255 is formed in the middle of the walking line area to form the first first walking line;

Forming a gate-gate insulating insulating edge layer and an active source layer in sequence, and forming a central shape in a peripheral line region around the outer periphery of the gate line Up to at least one of the first open openings;

Forming a source/drain metal layer on the active source layer, and at the same time, in the outer line of the outer periphery of the gate line Forming a second second walking line at the first opening opening;

3300 * A pixel electrode layer is formed on the insulating protective layer.

10. The method according to claim 9, wherein, after the insulating protective layer is formed on the source/drain metal layer, at least one of the insulating protective layers is formed in a peripheral wiring region of the gate line Two openings,

When the pixel electrode layer is formed on the insulating protective layer, a third trace is formed at the second opening in the peripheral wiring region of the gate line.

The method of claim 10, wherein the total length of the second opening is greater than one-half of the length of the outer trace of the gate line.

12. The method of any of claims 9-11, wherein the total length of the first opening is greater than one-half of the length of the outer trace of the gate line.

The method according to any one of claims 9 to 12, wherein the gate insulating layer and the active layer are sequentially formed and at least one of the first openings is formed in a peripheral wiring region of the gate line , including:

Forming the gate insulating layer and forming at least one of the first openings in the gate insulating layer in a peripheral wiring region of the gate line;

Forming the active layer and removing an active layer at the first opening in the peripheral trace region of the gate line.

14. The method according to any one of claims 9 to 12, wherein the gate insulating layer and the active layer are sequentially formed and at least one of the first openings is formed in a peripheral wiring region of the gate line, The method includes: forming the gate insulating layer;

The active layer is formed, and at least one of the first openings is formed in a peripheral wiring region of the gate line, and both the gate insulating layer and the active layer at the first opening are removed.

15. The method of claim 8 comprising:

Forming an active layer on the base substrate;

Forming a source/drain metal layer on the base substrate, forming the first trace in a peripheral line region of the gate line;

Forming the gate insulating layer on the source/drain metal layer, and forming at least one of the first openings in the gate insulating layer in a peripheral wiring region of the gate line;

Forming a gate metal layer on the gate insulating layer, forming the second trace in a peripheral trace region of the gate line, wherein the second trace passes through the first opening and the first trace connection.