CN104835827B - Display panel - Google Patents
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- CN104835827B CN104835827B CN201410048562.3A CN201410048562A CN104835827B CN 104835827 B CN104835827 B CN 104835827B CN 201410048562 A CN201410048562 A CN 201410048562A CN 104835827 B CN104835827 B CN 104835827B
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Abstract
The present invention discloses a kind of display panel, and thin film transistor base plate includes bottom plate, grid layer, gate dielectric, semiconductor layer, first electrode layer, the first passivation layer, the second passivation layer, through hole and the second electrode lay.Grid layer is located on substrate.Gate dielectric is located on grid layer.Semiconductor layer is located on gate dielectric.First electrode layer is located on semiconductor layer.First passivation layer is located in first electrode layer.Second passivation layer is located on the first passivation layer.Through hole runs through the first passivation layer and the second passivation layer, with the first electrode layer of expose portion.The second electrode lay is electrically connected by through hole with first electrode layer.Wherein, the first passivation layer has the first inclination angle in through hole side, and the second passivation layer has the second inclination angle in through hole side, and the differential seat angle at the first inclination angle and the second inclination angle is less than 30 degree.
Description
Technical field
The invention relates to a kind of display panel, and in particular to a kind of display with thin film transistor base plate
Panel.
Background technology
In the manufacture craft of display panel, turn on, can design logical to the conductive layer for making way for both sides above and below insulating layer
Hole (via or contact hole), enables the conductive layer of upper and lower both sides to be electrically connected.For example, pixel in dot structure is made
The method that electrode is electrically connected with the drain electrode of thin film transistor (TFT) is exactly before pixel electrode is formed, first carries out patterning and make work
Skill forms through hole, the beneath drain electrode of exposure in insulating layer, then plates pixel electrode, then pixel electrode can pass through this with drain electrode
Through hole is electrically connected.
However, with the development of high-resolution display panel, structure and manufacture craft also all the more complicated, different conduction
Insulating layer between interlayer is possible more than alternating floor.Since the membrance casting condition of different insulative layer is different, when etching forms through hole, just
Easily form chamfering.Such chamfering easily makes through hole fill up incomplete or break when conductive layer is plated, and influences display surface
The quality of plate.
The content of the invention
It is an object of the invention to provide a kind of display panels, have the design of specific passivation layer, can make through-hole side wall
Passivation layer junction is gentle, the situation that its upper electrode layer is avoided to break.
According to the first aspect of the invention, a kind of display panel is proposed.Display panel include thin film transistor base plate, to
Substrate and positioned at display layer between the two.Thin film transistor base plate include bottom plate, grid layer, gate dielectric, semiconductor layer,
First electrode layer, the first passivation layer, the second passivation layer and the second electrode lay.Grid layer is located on bottom plate.Gate dielectric position
On grid layer.Semiconductor layer is located on gate dielectric.First electrode layer is located at semiconductor layer.First passivation layer
On first electrode layer.Second passivation layer is located on the first passivation layer, and with through hole through the first passivation layer, with sudden and violent
Reveal the first electrode layer of part.The second electrode lay is located on the second passivation layer, and passes through through hole and be electrically connected with first electrode layer.
Wherein, the first passivation layer has the first inclination angle in through hole side, and the second passivation layer has the second inclination angle in through hole side, and first inclines
The differential seat angle at angle and the second inclination angle is less than 30 degree.
According to the second aspect of the invention, a kind of display panel is proposed.Display panel include thin film transistor base plate, to
Substrate and positioned at display layer between the two.Thin film transistor base plate include bottom plate, grid layer, gate dielectric, semiconductor layer,
First electrode layer, the first passivation layer, the second passivation layer and the second electrode lay.Grid layer is located on bottom plate.Gate dielectric position
On grid layer.Semiconductor layer is located on gate dielectric.First electrode layer is located at semiconductor layer.First passivation layer
On first electrode layer.Second passivation layer is located on the first passivation layer, and with through hole through the first passivation layer, with sudden and violent
Reveal the first electrode layer of part.The second electrode lay is located on the second passivation layer, and passes through through hole and be electrically connected with first electrode layer.
Wherein, the second passivation layer be multilayer passivating film composition multilayered structure, and second passivation layer the through hole side have between
One second inclination angle of 10-80 degree.
Description of the drawings
Fig. 1 illustrates the schematic diagram of the display device according to one embodiment of the invention.
Fig. 2A illustrates the schematic diagram of the thin film transistor base plate according to one embodiment of the invention.
Fig. 2 B illustrate the enlarged diagram of the region A of Fig. 2A.
Fig. 3 illustrates the schematic diagram of the thin film transistor base plate according to another embodiment of the present invention.
Fig. 4 A- Fig. 4 D illustrate the schematic diagram of the manufacturing method of through hole in Fig. 2A and Fig. 3.
Symbol description
1：Display device
10、11、12：Thin film transistor base plate
100：Bottom plate
110：Grid layer
120：Gate dielectric
130：Semiconductor layer
135：Etching stopping layer
140：First electrode layer
141：First portion
142：Second portion
150：First passivation layer
151：First edge
160：Organic layer
161：Opening
170：Second passivation layer
171：First passivating film
172：Second passivating film
173：3rd passivating film
174：Second edge
180：The second electrode lay
190：Through hole
191：Through hole side
200：Common electrode layer
2：Display panel
20：Display layer
30：Opposite substrate
40：Backlight module
θ1：First inclination angle
θ2：Second inclination angle
d：Distance
Specific embodiment
The embodiment of the present invention is described in detail referring to appended attached drawing.In attached drawing identical label to indicate it is identical or
Similar part.It needs it is specifically intended that attached drawing is simplified clearly to illustrate the content of embodiment, and the size on attached drawing with profit
Ratio is not drawn according to actual product equal proportion, therefore is not intended as limiting the scope of the present invention and be used.
Fig. 1 is refer to, illustrates the display device according to one embodiment of the invention.Display device 1 include display panel 2 and
Backlight module 40.When display panel 2 is liquid crystal display panel, from thin film transistor base plate 10, display layer 20 and to base
Plate 30 forms, and display layer is liquid crystal layer.Display layer 20, can be by voltage between thin film transistor base plate 10 and opposite substrate 30
Driving and change its light transmittance.Opposite substrate 30 is designed compared with thin film transistor base plate 10, is, for example, colorized optical filtering chip base
Plate enables display panel 2 to show colour.It is worth noting that, when display panel 2 is organic LED panel, then
Can not have backlight module 40, and display layer 20 is organic luminous layer.
Thin film transistor base plate 10 is the main element of display panel 2, and division thereon has multiple pixel regions, each pixel
Region has corresponding thin film transistor (TFT), can adjust the light transmittance positioned at this region display layer.Thin film transistor base plate is according to its picture
The design of plain structure is different, and there are many types, are illustrated below with Fig. 2A and Fig. 2 B.
Fig. 2A is refer to, illustrates the thin film transistor base plate according to one embodiment of the invention.The thin film transistor (TFT) of Fig. 2A
Substrate 11 is rear channel etch (back channel etch, BCE) structure, including bottom plate 100, grid layer 110, gate dielectric
Layer 120, semiconductor layer 130, first electrode layer 140, the first passivation layer 150 (passivation layer), the second passivation layer
170th, the second electrode lay 180 and through hole 190.
As shown in Figure 2 A, grid layer 110 is located on bottom plate 100, and gate dielectric 120 is located on grid layer 110, and half
Conductor layer 130 is located on gate dielectric 120.That is, gate dielectric 120 separates grid layer 110 and semiconductor layer
130.In this example, grid layer is located under as the semiconductor layer 130 of active layers, so being known as lower grid (bottom gate)
Formula structure.First electrode layer 140 is located on semiconductor layer 130, and is electrically connected with semiconductor layer 130, forms a film crystal
Pipe, and using semiconductor layer 130 as the active layers of thin film transistor (TFT).Specifically, first electrode layer 140 is patterned as separating
First portion 141 and second portion 142, first portion 141 is electrically connected with semiconductor layer 130, formation source contact；Second
Divide 142 to be electrically connected with semiconductor layer 130, form drain contact.
As shown in Figure 2 A, the first passivation layer 150 is formed in first electrode layer 140, and organic layer 160 is formed at the first passivation
On layer 150, the second passivation layer 170 is then formed on organic layer 160.Common electrode layer 200 is formed at the second passivation layer 170 and has
Between machine layer 160.First passivation layer 150, the material of the second passivation layer 170 are related with the material of semiconductor layer 130, such as when half
When 130 indium gallium zinc of conductor layer (IGZO) is material, silica (SiO can be selected in the first passivation layer 150X), and the second passivation
Optional silicon nitride (the SiN of layerX).Passivation layer 150,170 has the characteristic of the gas that blocks water, insulation etc, can protective film transistor
Other structures on substrate.The material of organic layer 160 is, for example, acryl or PFA resins (Perfluoroalkoxy), to add
Big pixel electrode (the second electrode lay 180) and the distance of signal wire (not illustrating), are applied in high-resolution thin film transistor (TFT) base
The coupled interference of signal between the two can be substantially reduced in plate.In one embodiment, the first passivation layer 150 and the second passivation layer 170
Thickness is about And the thickness of organic layer 160 is aboutIt is worth noting that, in other realities
It applies in example, organic layer can be also not provided in thin film transistor base plate or be replaced with other elements, is not intended to limit.
As shown in Figure 2 A, through hole 190 has through hole side 191, and through the first passivation layer 150, organic layer 160 and second
Passivation layer 170, to expose the second portion 142 (drain contact) of first electrode layer 140.The second electrode lay 180 is, for example, pixel
Electrode is electrically connected on the second passivation layer 170, and through through hole 190 with first electrode layer 140.Although it is worth noting that,
With 160 interval of organic layer, right second passivation among the first passivation layer 150 and the second passivation layer 170 on thin film transistor (TFT)
Layer 170 is directly overlayed in through hole side 191 on first passivation layer 150 (region A).It is specifically intended that due to first blunt
It is heterogeneity to change layer 150 and second passivation layer 170, and when etching vias 190 has different etch-rates, therefore in through hole side
191 the first passivation layer 150 and the second passivation layer 170 differ surely in same straight line, such as can be stepped, such as Fig. 2A institutes
Show.
Fig. 2 B are refer to, illustrate the enlarged drawing of the region A (190 side wall of through hole) of Fig. 2A, for convenience of description, this Tu Zhong is saved
Slightly subelement.As shown in the figure, the first passivation layer 150 has 1 (taper of the first inclination angle theta at through hole side 191 (Fig. 2A)
Angle), the second passivation layer 170 has the second inclination angle theta 2 in through hole side 191.Due to the first passivation layer 150 and the second passivation layer
For heterogeneity, its etch-rate can be variant when forming through hole, therefore the value of the first inclination angle theta 1 and the second inclination angle theta 2 has differences,
Chamfering just may be generated when difference is too big, the second electrode lay 180 formed after being allowed to breaks.The present embodiment is by second
Passivation layer 170 is designed as 3 layers of passivation film structure, sequentially respectively the first passivating film 171, the second passivating film 172 and the 3rd passivation
Film 173, and adjustment its etch-rate under the conditions of same etch makes the first passivating film 171<Second passivating film 172<3rd passivation
Film 173, that is, there is slower etch-rate closer to the passivating film of the first passivation layer 150.Thus, it can significantly control
The size of second inclination angle theta 2.In one embodiment, the difference of the first inclination angle theta 1 and the second inclination angle theta 2 is less than 30 degree, however in other realities
It applies difference and is smaller than 3 degree.In another embodiment, the differential seat angle of first inclination angle theta 1 and second inclination angle theta 2 is between 3-10
Degree.In another embodiment, the second inclination angle is between 10-80 degree or between 45-60 degree.By adjusting in through hole side 191
The first passivation layer 150, the angle of the second passivation layer 170 it is close, can prevent the second electrode lay 180 from being disconnected in plated film, keep
The quality of thin film transistor base plate.
In addition in this example, since the second passivation layer 170 is formed after organic layer 160, it is impossible to use too high temperature (>250
DEG C) film-forming temperature, in order to avoid damage (film formation at low temp for usually adopting 200-220 DEG C) to organic layer 160.Therefore the second passivation layer
170 etch-rate can be more than the first passivation layer 150 (at least 2 times), make the first passivation layer 150 the first of through hole side 191
Edge 151 can not necessarily align with second edge 174 of second passivation layer 170 in through hole side 191, and second edge 174 is compared with
One edge 151 forms stepped, the edge formation distance d (figures of first edge 15 and second edge 174 away from the through hole 190
2B).In one embodiment, the scope of distance d between
Fig. 3 is refer to, illustrates the thin film transistor base plate 12 according to another embodiment of the present invention.Thin film transistor base plate
12 use etching stopping layer (etching stop layer, ESL) frameworks, with the difference of the thin film transistor base plate 11 of Fig. 2A it
It is in there is provided etching stopping layers 135 between first electrode layer 140 and semiconductor layer 130.The film of remaining element and Fig. 2A
Transistor base 11 is similar, and details are not described herein again.
The manufacturing method of figure 4 below A through holes 190 into 4D definition graphs 2A and Fig. 3.For convenience of description, attached drawing is only listed logical
The neighbouring element in hole 190, without illustrating entire thin film transistor base plate.
First, as shown in Figure 4 A, the first passivation layer 150 and organic layer 160 are sequentially deposited in first electrode layer 140.The
The material of one passivation layer 150 is silicon nitride or silica, and the material of organic layer is, for example, acryl.
Then, as shown in Figure 4 B, photoetching process is carried out with a photomask (not illustrating), on organic layer 160
Form opening 161, and the first passivation layer 150 of exposure.
Come again, as shown in Figure 4 C, form the second passivation layer 170 and cover the first passivation layer 150 and organic layer 160.Second is blunt
The material for changing layer 170 is silicon nitride.In this step, it is blunt with different etch-rates under the conditions of same etch to form multilayer
Change film, to form the second passivation layer 170, wherein the passivating film etch-rate of more lower section is slower, the first passivating film 171<Second is blunt
Change film 172<3rd passivating film 173.In one embodiment, the etch-rate of the first passivating film 171 is aboutSecond passivation
The etch-rate of film 172 is aboutThe etch-rate of 3rd passivating film 173 is aboutEtch-rate can pass through tune
Seamless power and the ratio change for being passed through gas.For example, pressure is higher, and the etch-rate of the passivating film of formation is faster；And
(NH is passed through in gas3/SiH4) bigger (the table NH of ratio3It is more), the etch-rate of the passivating film of formation is slower.The present embodiment
In be by taking the second passivation layer 170 that 3 layers of passivating film 171,172,173 form as an example, so in other embodiments, the second passivation layer
170 also can be the structure of 2 layers or more layers.
Then, as shown in Figure 4 D, it is passivated with a photomask (can be identical or different with the photomask used in Fig. 4 B) to second
170 and first passivation layer 150 of layer carries out photoetching process, forms through hole 190 to expose first electrode layer 140.Due to
It is slower close to the etch-rate of the passivating film of the first passivation layer 150 (lower section) in the second passivation layer, and away from the first passivation layer
The etch-rate of 150 (tops) is very fast, and it is not vertical that thus can make the second passivation layer 170 of through-hole side wall, and with less than 80
Second inclination angle theta 2 of degree, can also make the first inclination angle theta 1 close with the differential seat angle of the second inclination angle theta 2.Most after plating second in through hole
Electrode layer (does not illustrate), then completes the through hole 190 of Fig. 2A and Fig. 3.
The display panel of above-described embodiment by adjusting the etch-rate of the passivation layer in thin film transistor base plate, can make
The passivation layer of through-hole side wall is more gentle, has smaller differential seat angle.When pixel electrode is plated in through hole, just it is not easily formed
Broken string maintains Low ESR, promotes panel quality.Specifically, the difference of the first inclination angle theta 1 and the second inclination angle theta 2 is less than 30 degree, as
Plain electrode is 2286.1 ohm (Ω) in the contact impedance of drain contact, is compared to existing first inclination angle theta, 1 and second inclination angle theta 2
Difference to be more than 30 degree its contact impedances be 71930.6 ohm (Ω), have the effect that impedance is greatly reduced.
Though in conclusion disclose the present invention with reference to above example, however it is not limited to the present invention.The present invention
Those of ordinary skill in the art, without departing from the spirit and scope of the present invention, should can make various changes with
Retouching.Therefore, protection scope of the present invention should be subject to what the claim enclosed was defined.
Claims (14)
1. a kind of display panel, including：
Thin film transistor base plate, including：
Bottom plate；
Grid layer, on the bottom plate；
Gate dielectric, on the grid layer；
Semiconductor layer, on the gate dielectric；
First electrode layer, positioned at the semiconductor layer；
First passivation layer, on the first electrode layer；
Organic layer, on first passivation layer；
Second passivation layer, on the organic layer, wherein, a through hole through second passivation layer, the organic layer and this first
Passivation layer, the first electrode layer of expose portion and partial first passivation layer；And
The second electrode lay on second passivation layer, and passes through the through hole and is electrically connected with the first electrode layer,
Wherein, first passivation layer of exposure includes a first side edge and one first top edge, which includes one
Second side edge, first top edge are located between the first side edge and the second side edge, the width of first top edge
Between 500-2000 angstromsThe second electrode lay contacts first top edge of first passivation layer, which has
One first inclination angle, the second side edge have one second inclination angle, and the differential seat angle at first inclination angle and second inclination angle is less than 30 degree；
Opposite substrate is oppositely arranged with the thin film transistor base plate；And
Display layer, between the thin film transistor base plate and the opposite substrate.
2. display panel as described in claim 1, wherein in the through hole side, second passivation layer directly overlay this first
On passivation layer.
3. display panel as described in claim 1, wherein second passivation layer are by one first passivating film and one second passivating film
Composition, and first passivating film is located between first passivation layer and second passivating film.
4. display panel as claimed in claim 3, wherein the etch-rate of first passivating film is small under the conditions of same etch
In the etch-rate of second passivating film.
5. the material of display panel as described in claim 1, the wherein semiconductor layer is indium gallium zinc (IGZO), this first
The material of passivation layer is silica, and the material of second passivation layer is silicon nitride.
6. display panel as described in claim 1, the wherein first side edge, in the through hole side, the second side edge is at this
Through hole side, the second side edge is compared with the first side edge away from the through hole.
7. display panel as described in claim 1, wherein first inclination angle and the differential seat angle at second inclination angle are between 3-10 degree.
8. a kind of display panel, including：
Thin film transistor base plate, including：
Bottom plate；
Grid layer, on the bottom plate；
Gate dielectric, on the grid layer；
Semiconductor layer, on the gate dielectric；
First electrode layer, positioned at the semiconductor layer；
First passivation layer, on the first electrode layer；
Organic layer is formed on first passivation layer；
Second passivation layer, on the organic layer, wherein, a through hole through second passivation layer, the organic layer and this first
Passivation layer, the first electrode layer of expose portion and partial first passivation layer；And
The second electrode lay on second passivation layer, and passes through the through hole and is electrically connected with the first electrode layer,
Wherein, first passivation layer of exposure includes a first side edge and one first top edge, which includes one
Second side edge, first top edge are located between the first side edge and the second side edge, the width of first top edge
Between 500-2000 angstromsThe second electrode lay contacts first top edge of first passivation layer, which is more
The multilayered structure of layer passivating film composition, and the second side edge has between one second inclination angle of 10-80 degree；
Opposite substrate is oppositely arranged with the thin film transistor base plate；And
Display layer, between the thin film transistor base plate and the opposite substrate.
9. display panel as claimed in claim 8, wherein in the through hole side, second passivation layer directly overlay this first
On passivation layer.
10. display panel as claimed in claim 8, wherein second passivation layer are by one first passivating film and one second passivating film
Composition, and first passivating film is located between first passivation layer and second passivating film.
11. display panel as claimed in claim 10, wherein under the conditions of same etch first passivating film etch-rate
Less than the etch-rate of second passivating film.
12. the material of display panel as claimed in claim 8, the wherein semiconductor layer is indium gallium zinc (IGZO), this
The material of one passivation layer is silica, and the material of second passivation layer is silicon nitride.
13. display panel as claimed in claim 8, the wherein first side edge exist in the through hole side, the second side edge
The through hole side, the second side edge is compared with the first side edge away from the through hole.
14. display panel as claimed in claim 8, wherein the angle at second inclination angle is between 45-60 degree.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410048562.3A CN104835827B (en) | 2014-02-11 | 2014-02-11 | Display panel |
| CN201810447029.2A CN108666350A (en) | 2014-02-11 | 2014-02-11 | Display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410048562.3A CN104835827B (en) | 2014-02-11 | 2014-02-11 | Display panel |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810447029.2A Division CN108666350A (en) | 2014-02-11 | 2014-02-11 | Display panel |
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| CN104835827A CN104835827A (en) | 2015-08-12 |
| CN104835827B true CN104835827B (en) | 2018-06-05 |
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| CN105552091A (en) * | 2016-03-09 | 2016-05-04 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display panel |
| KR102383745B1 (en) * | 2016-11-11 | 2022-04-08 | 삼성디스플레이 주식회사 | Display device |
| CN109962078B (en) * | 2019-03-28 | 2021-02-09 | 合肥鑫晟光电科技有限公司 | Display substrate, preparation method thereof and display panel |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905199A (en) * | 2005-07-29 | 2007-01-31 | 三星电子株式会社 | Array substrate having enhanced aperture ratio, method of manufacturing the same and display device |
| CN102759824A (en) * | 2011-04-22 | 2012-10-31 | 株式会社日立显示器 | Liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7248317B2 (en) * | 2005-04-21 | 2007-07-24 | Toppoly Optoelectronics Corporation | Transflective display panels and methods for making the same |
| JP5234301B2 (en) * | 2005-10-03 | 2013-07-10 | Ｎｌｔテクノロジー株式会社 | Thin film transistor, thin film transistor array substrate, liquid crystal display device and manufacturing method thereof |
| CN101546746A (en) * | 2008-03-25 | 2009-09-30 | 上海广电Nec液晶显示器有限公司 | Insulating layer for guaranteeing cis-tapered contact holes and manufacturing method thereof |
| TWI743509B (en) * | 2011-05-05 | 2021-10-21 | 日商半導體能源研究所股份有限公司 | Semiconductor device and method for manufacturing the same |
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- 2014-02-11 CN CN201410048562.3A patent/CN104835827B/en active Active
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1905199A (en) * | 2005-07-29 | 2007-01-31 | 三星电子株式会社 | Array substrate having enhanced aperture ratio, method of manufacturing the same and display device |
| CN102759824A (en) * | 2011-04-22 | 2012-10-31 | 株式会社日立显示器 | Liquid crystal display device |
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| CN104835827A (en) | 2015-08-12 |
| CN108666350A (en) | 2018-10-16 |
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