WO2014176876A1 - Panneau d'affichage et son procédé de fabrication et afficheur à cristaux liquides - Google Patents

Panneau d'affichage et son procédé de fabrication et afficheur à cristaux liquides Download PDF

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Publication number
WO2014176876A1
WO2014176876A1 PCT/CN2013/085497 CN2013085497W WO2014176876A1 WO 2014176876 A1 WO2014176876 A1 WO 2014176876A1 CN 2013085497 W CN2013085497 W CN 2013085497W WO 2014176876 A1 WO2014176876 A1 WO 2014176876A1
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WO
WIPO (PCT)
Prior art keywords
gate
line
layer
opening
trace
Prior art date
Application number
PCT/CN2013/085497
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English (en)
Chinese (zh)
Inventor
徐向阳
Original Assignee
合肥京东方光电科技有限公司
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of WO2014176876A1 publication Critical patent/WO2014176876A1/fr

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13456—Cell terminals located on one side of the display only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings

Definitions

  • Embodiments of the present invention relate to a display panel, a method of fabricating the same, and a liquid crystal display. Background technique
  • a thin film transistor liquid crystal display is a liquid crystal display device driven by a semiconductor device.
  • TFT-LCD can be classified into a twisted nematic type, a vertical alignment type, an in-plane switching (IPS) type, and a fringe field conversion (FFS) type.
  • IPS in-plane switching
  • FFS fringe field conversion
  • the panel charges and discharges the pixel capacitance by progressive scanning, thereby deflecting the liquid crystal to control the light field of the backlight.
  • the scan signal and the drive voltage are generated by the gate integrated circuit and the driver integrated circuit, respectively.
  • the control signal of the gate integrated circuit is generated by a Timing Controller chip and transmitted to the gate integrated circuit via a panel Layout Gate.
  • a single layer of metal traces is used for the peripheral traces of the TFT-LCD array substrate.
  • the signal delay of the line has no effect on the display due to the lower frequency.
  • the frequency of the signal is also increasing.
  • the delay and attenuation of the signal in the line cannot be ignored.
  • There are two main reasons for the delay of the line on the one hand, the signal trace resistance of the line; on the other hand, the coupling capacitance of the line.
  • the coupling capacitance is generated between the different metal lines on the reverse side; and the resistance is determined by the characteristics of the metal trace itself, mainly depending on the resistivity, cross section and wiring length of the metal trace.
  • Common wiring metal materials include: aluminum, molybdenum, copper, indium tin oxide (ITO), and the like. In terms of electrical conductivity, copper is the best but the highest cost, and the process is the most difficult.
  • Embodiments of the present invention provide a display panel, a manufacturing method thereof, and a liquid crystal display, which are used for The resistance of the traces on the periphery of the low gate line reduces signal attenuation and delay, improving display performance.
  • An embodiment of the present invention provides a display panel including a gate line peripheral trace region provided with a gate line peripheral trace, wherein the gate line peripheral trace includes a first trace sequentially formed on the base substrate a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening.
  • Another embodiment of the present invention provides a liquid crystal display including the display panel.
  • a further embodiment of the present invention provides a method for fabricating a display panel, the display panel including a display area and a gate line peripheral routing area, and the manufacturing method includes: on a base substrate in a peripheral line area of the gate line Forming a first trace for the gate line peripheral traces, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, the first trace and the second trace The wires are electrically connected through the first opening.
  • FIG. 1 is a schematic diagram of an array of anti-peripheral circuits of a liquid crystal display panel
  • FIG. 2 is a schematic diagram of a peripheral trace of a gate line according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a peripheral trace of a gate line according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of processing and forming of a mask provided by a specific embodiment of the present invention.
  • 100 electrostatic ring short circuit; 101: gate line; 102: terminal area; 103: common electrode; 104: electrostatic ring; 105: pixel drive chip; 106: gate integrated circuit; 107: data line; 108: gate line Peripheral routing; 109: Display area.
  • Embodiments of the present invention provide a display panel and a method for fabricating the same, and a liquid crystal display for reducing resistance of a peripheral trace of a gate line, reducing signal attenuation and delay, and improving display performance.
  • the display panel includes a display area 109 at the center and a peripheral area outside the display area 109.
  • the display area 109 includes a plurality of gate lines 101, a plurality of data lines 107, and a plurality of pixel units defined by the intersection of the gate lines 101 and the data lines 107.
  • each pixel unit includes a thin film transistor (TFT) as a switching element, and a gate of the thin film transistor is electrically connected or integrally formed with a corresponding gate line, and a source of the thin film transistor is electrically connected or integrally formed with a corresponding data line, and the thin film
  • the drain of the transistor is electrically connected or integrally formed with the corresponding pixel electrode.
  • the peripheral area includes the peripheral line of the gate line where the gate line outer trace 108 is located, and other areas in the vicinity (e.g., the terminal area 102, etc.).
  • the gate integrated circuit 106 is for applying a gate scan signal to the gate lines in the display area 109.
  • the liquid crystal panel may further include other components or structures such as the electrostatic ring short circuit 100, the terminal region 102, the common electrode 103, the electrostatic ring 104, and the pixel driving chip 105.
  • An embodiment of the present invention provides a structure of a gate line peripheral trace of a display panel, wherein a gate line peripheral trace of the liquid crystal panel includes a first trace sequentially formed on a base substrate for a peripheral trace of the gate line, a gate insulating layer and a second trace; the gate insulating layer includes at least one first opening, and the first trace and the second trace are electrically connected through the first opening. At least one first opening in the gate insulating layer is exposed to a first trace under the gate insulating layer to enable the first and second traces to Electrically connected to each other, thereby reducing the overall resistance of the outer traces of the gate lines.
  • the intermediate layer of the active layer in the peripheral trace area of the gate line is etched and removed during the fabrication process, or, for example, there are The intermediate layers of the source layer are all removed, for example by etching.
  • the intermediate layer may be, for example, an interlayer insulating layer separating the pixel electrode layer and the source/drain metal layer.
  • the first trace may be formed simultaneously with the gate line, and the second trace may be formed simultaneously with the source drain electrode or the pixel electrode.
  • the first opening also passes through the intermediate layer to expose the first trace under the intermediate layer.
  • the total length of the first opening may be greater than one-half of the length of the outer trace of the gate line, that is, more than half of the outer traces of the gate line are exposed.
  • sufficient contact is required between the first trace and the second trace, and the larger the contact area of the two, the lower the overall resistance of the resulting trace of the peripheral trace of the gate line.
  • the first opening may be formed in the peripheral wiring area of the entire gate line, thereby exposing the entire peripheral line of the gate line; or the first opening may be formed continuously or at intervals only in the peripheral line area of the partial gate line, that is, The first opening may not be limited to one.
  • the peripheral trace of the gate line may be at least two points. One of the regions is formed such that the first trace and the second trace can be electrically connected directly.
  • the display panel gate line peripheral trace region may further include an insulating protective layer formed on the base substrate and a third trace above the insulating protective layer.
  • the third trace may be formed simultaneously with the pixel electrode formed on the insulating protective layer, and at this time, the second trace is formed, for example, simultaneously with the source and drain electrodes.
  • At least one second opening may be formed in the insulating protective layer, and the third trace and the second trace are electrically connected through the second opening.
  • the second opening is exposed to a second trace below the insulating protective layer. If the three conductive layers of the first trace, the second trace, and the third trace are electrically connected to each other, the obtained trace of the peripheral trace of the gate line is better, and the overall resistance is lower.
  • the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line. Similar to the first opening, in order to maintain good electrical conductivity, sufficient contact is required between the second trace and the third trace.
  • the second opening may also be not limited to one.
  • a liquid crystal display provided by an embodiment of the present invention includes the display panel; a gate line peripheral trace of the display panel connects the timing control chip and the gate integrated circuit.
  • Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:
  • the base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate.
  • the above embodiment has been described by taking a bottom gate type display panel as an example, but the present invention is not limited thereto.
  • the first trace needs to be directly electrically connected to the second trace. Therefore, in the peripheral wiring region of the gate line, the gate insulating layer and the active layer between the first trace and the second trace need to be etched away to form the first opening of the first trace exposed
  • the gate insulating layer and the active layer at other positions in the peripheral region of the gate line can be removed or etched as needed.
  • forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral line region of the gate line includes: forming a gate insulating layer and a gate in a peripheral region of the gate line Forming a first opening in the pole insulating layer; forming an active layer and removing the active layer or all active layers at the first opening in a peripheral wiring region of the gate line. That is, in the latter case, the gate insulating layer near the peripheral wiring region of the gate line is left, and the entire active layer of the gate wiring peripheral wiring region and its vicinity is etched away.
  • forming a gate insulating layer and an active layer in sequence in step S202 and forming at least one first opening in a peripheral wiring region of the gate line includes: forming a gate insulating layer; forming an active layer and surrounding the gate line The wiring region forms at least one first opening; the gate insulating layer and the active layer corresponding to the first opening are both removed by etching, for example.
  • Etching the gate insulating layer and the active layer may include simultaneously etching away all of the gate insulating layer and the active layer of the gate wiring peripheral region and the vicinity thereof, or simultaneously etching away the gate wiring in the peripheral routing region a gate insulating layer and an active layer.
  • step S203 may be: forming a pixel electrode layer on the active layer, and then forming a second trace at at least the first opening in the peripheral trace region of the gate line, where The second trace is electrically connected to the first trace through the first opening.
  • the source and drain electrodes may be formed before or after the pixel electrode, and the two may be in direct contact, or an insulating layer may be formed therebetween and electrically connected to each other through via holes in the insulating layer.
  • the method of the above embodiment using the source/drain metal layer to form the second trace can also continue as follows:
  • the pixel electrode is formed over the insulating protective layer, and is electrically connected to one of the source and drain electrodes through a via hole in the insulating protective layer.
  • step S204 after forming an insulating protective layer on the source/drain metal layer, at least one second opening is formed in the insulating protective layer in the peripheral wiring region of the gate line to expose the second trace below;
  • a third trace is formed at the second opening of the peripheral wiring region of the gate line.
  • the two wires of the first wire and the second wire may be used to transmit signals, or the first wire, the second wire, and the third wire may be used. Transmission signal.
  • the metal layers are in contact with each other, which can increase the cross-sectional area of the metal layer and reduce the trace resistance at the periphery of the gate line.
  • the total length of the second opening may be greater than one-half of the length of the outer trace of the gate line.
  • 2 is a schematic diagram of a gate line peripheral trace of one embodiment of the present invention, and only the gate line peripheral trace shown in the figure includes three traces (wires) parallel to each other, but the present invention is not limited thereto.
  • 3 is a cross-sectional view of a trace of FIG.
  • the structure of the trace comprising: a glass substrate 200 as a base substrate; a first walk formed on the glass substrate 200 a wire 201; a gate insulating layer 202 formed on the glass substrate 200, the gate insulating layer 202 having a first opening 310 to expose the first trace 201; and a second trace 203 passing through the first opening 310 and the first
  • the wiring 201 is electrically connected; an insulating protective layer 204 is formed on the second trace 203, the insulating protective layer 204 has a second opening 320 to expose the second trace 203; and a third formed on the insulating protective layer 204
  • the trace 205 is electrically connected to the second trace 203 through the second opening 320.
  • the gate line peripheral traces in this example include three layers of traces electrically connected to each other, and the active layer is completely removed in the gate line peripheral traces.
  • each layer pattern includes, but is not limited to, the form of FIG. 3.
  • Each layer may also be patterned (eg, etched) into other graphic patterns, and only needs to ensure that the three layers of metal can be sufficiently contacted to form an electrical connection. .
  • each layer of the peripheral line area of the gate line corresponds to the following steps in the production process of the display panel:
  • FIG. 4 a schematic diagram of the processing of the masks corresponding to steps 1-2 and 4-5 is performed.
  • Another embodiment of the present invention provides a method of fabricating a display panel, which can be performed as follows:
  • a gate insulating layer on the source/drain metal layer forming a gate insulating layer on the source/drain metal layer, forming a first opening in the gate insulating layer of the peripheral portion of the gate line, the first opening exposing at least a portion of the first trace;
  • a gate metal layer on the gate insulating layer thereby forming a gate and a gate line in the display region, and forming a second trace in the peripheral trace region of the gate line, the second trace passing through the first opening
  • the first trace is electrically connected.
  • the base substrate is, for example, a glass substrate, and the outer peripheral wiring region of the gate line is formed on the outer side of the display region, for example, on both sides or all four sides of the rectangular substrate.
  • the above embodiment has been described by taking a top gate type display panel as an example, but the present invention is not limited thereto.
  • the method of the embodiment of the present invention can etch all the active layer of the gate line and the active layer in the vicinity of the gate line when the active layer is patterned, and the same active process as that of the conventional display panel can be used.
  • Layer mask For example, the patterning of the active layer is performed between the patterning of the gate insulating layer and the source/drain metal layer. If the peripheral wiring region of the gate line only removes the active layer at the first opening, the active layer mask used is different from that used in the process of fabricating the conventional display panel, and remains in the periphery of the gate line in the corresponding patterning process. The active layer in the trace area.
  • the first opening is formed by changing the gate insulating layer to form the first opening therein and the second opening is formed therein by changing the insulating protective layer mask, and the first to the second opening are connected through the first and second openings
  • the three-layer metal traces are used to obtain the peripheral traces of the gate lines, thereby achieving the purpose of reducing the trace resistance of the gate lines.
  • the embodiments of the present invention provide a display panel, a method for fabricating the same, and a liquid crystal display device, which can reduce the resistance of the peripheral lines of the gate line, reduce signal attenuation and delay, and improve the display effect.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un panneau d'affichage comprenant une zone de détourage périphérique de ligne de porte munie d'un détourage périphérique de ligne de porte, le détourage périphérique de ligne de porte comprenant un premier détourage (201), une couche d'isolation de porte (202) et un deuxième détourage (203) qui sont formés séquentiellement sur un substrat. La couche d'isolation de porte (202) est munie d'au moins une première ouverture (310) et le premier détourage (201) est relié électriquement au deuxième détourage (203) à travers la première ouverture (310). Le panneau d'affichage peut réduire la résistance du détourage périphérique de ligne de porte, réduire l'atténuation et le retard du signal et améliorer l'effet d'affichage.
PCT/CN2013/085497 2013-05-03 2013-10-18 Panneau d'affichage et son procédé de fabrication et afficheur à cristaux liquides WO2014176876A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310161321.5A CN103278989B (zh) 2013-05-03 2013-05-03 一种显示面板及其制作方法、液晶显示器
CN201310161321.5 2013-05-03

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WO2014176876A1 true WO2014176876A1 (fr) 2014-11-06

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CN103278989B (zh) * 2013-05-03 2015-08-05 合肥京东方光电科技有限公司 一种显示面板及其制作方法、液晶显示器
CN106094373A (zh) * 2016-06-02 2016-11-09 武汉华星光电技术有限公司 Tft基板及其制作方法
CN106094272B (zh) * 2016-06-22 2019-06-07 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置
CN106206617A (zh) * 2016-08-29 2016-12-07 武汉华星光电技术有限公司 基于低温多晶硅的阵列基板及其制作方法
CN112086424B (zh) 2019-06-14 2023-06-23 群创光电股份有限公司 接合垫结构
CN114994994B (zh) * 2022-06-17 2024-06-07 北海惠科光电技术有限公司 液晶显示面板和液晶显示面板制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7787089B2 (en) * 2008-09-26 2010-08-31 Hitachi Displays, Ltd. Transparent type liquid crystal display device
CN102569186A (zh) * 2010-12-17 2012-07-11 奇美电子股份有限公司 阵列基板及其形成方法
CN102651401A (zh) * 2011-12-31 2012-08-29 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制造方法和显示器件
CN103278989A (zh) * 2013-05-03 2013-09-04 合肥京东方光电科技有限公司 一种显示面板及其制作方法、液晶显示器

Family Cites Families (1)

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Publication number Priority date Publication date Assignee Title
JP4266768B2 (ja) * 2003-10-17 2009-05-20 Ｎｅｃ液晶テクノロジー株式会社 画像表示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7787089B2 (en) * 2008-09-26 2010-08-31 Hitachi Displays, Ltd. Transparent type liquid crystal display device
CN102569186A (zh) * 2010-12-17 2012-07-11 奇美电子股份有限公司 阵列基板及其形成方法
CN102651401A (zh) * 2011-12-31 2012-08-29 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制造方法和显示器件
CN103278989A (zh) * 2013-05-03 2013-09-04 合肥京东方光电科技有限公司 一种显示面板及其制作方法、液晶显示器

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CN103278989A (zh) 2013-09-04

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