1249微一 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體的製造方法，且特別 是有關於一種多晶矽層與多晶矽薄膜電晶體的製造方法。 【先前技術】 隨著高科技之發展，數位化之視訊或影像裝置已經成 為在一般日常生活中所常見的產品。這歧數位化 影像裝置巾，顯示ϋ是-個重要元件。賴者可 讀取資訊，或進而控制裝置的運作。 而薄膜電晶體(Thin Film Transistor，TFT)可應用於液 晶顯示器(Liquid Crystal Display，LCD)之驅動元件，使得此 項產品成為桌上直式型平面顯示器之主流，於個人電腦、 遊樂器、監視器等市場成為未來主導性產品。目前，在薄 膜電晶體液晶顯示器中有一種利用多晶矽技術所製得的薄 膜電晶體，其載子遷料較-般傳統的非晶碎(Am()rph〇us Silicon，簡稱a-Si)薄膜電晶體之載子遷移率大得多，因此 可使薄膜電晶體元件做得更小，開口率增加(Ap論reRati〇) 進而增加顯示器亮度，減少功率的消耗。另外，由於多晶 石夕薄膜電晶體與目前金氧半導體（Metal 〇xide Semiconductor，M〇S)的製程相容，可以將部份驅動電路 (Driving Circuit)隨同薄膜電晶體製程同時製造於玻璃基 板上，大幅提升液晶顯示面板的特性及可靠度，並且降低 面板的製造成本，在價格上較非晶矽薄膜電晶體液晶顯示 器便宜許多。再加上多晶矽具有厚度薄、重量輕、解析度 I24981^4wf.doc/m 佳等特點’特別適合應用於要求輕巧省電的行動終端產品 上。 然而’雖然多晶矽薄膜電晶體具有高載子遷移率 以及尚驅動電流（約為1 〇-4微安培）的優異特性。但 另方面’由於多晶石夕薄膜電晶體具有較多的缺陷密 度’導致其亦具有較高的漏電流（Leakage current) (約為10 9微安培），而且容易因通道汲極（Drain) 端橫向電場誘發熱載子效應（Hot Carrier Effect)，進 而導致元件退化。 【發明内容】 ,有鑑於此，本發明的目的就是在提供一種多晶矽層的 製造方法，不但步驟簡單，且可以增大多晶矽層的晶粒尺 寸，進而提高載子的遷移率，以改善多晶矽層漏電流太大 的缺點。 ，』本兔明的另一目的就是在提供一種多晶石夕薄膜電晶體 的製造方法，可以獲得晶粒尺寸較大的多晶矽薄膜電晶 體改善漏電流的問題，進而提高元件的導通特性以及元 件的可靠度。 本發明提出一種多晶矽層的製造方法，此方法係先提 供一基板。然後，形成一非晶矽層於基板上。接著，對非 日日石夕層進行一離子佈植製程（ΐ〇η ΐπ1ρΐΜ^〇η p叩⑽$ )， 之後，進行一再結晶製程，將非晶矽層轉化成一多晶矽層。 依照本發明的較佳實施例所述之多晶矽層的製造方 法，上述之基板包括一玻璃基板或一石英基板。 1249856 1543 8twf.doc/m 、依照本發明的較佳實施例所述之多晶矽層的製造方 法’上述形成非晶矽層的方法包括一低壓化學氣相沈積法。 、依照本發明的較佳實施例所述之多晶矽層的製^方 法，上述之非晶矽層的厚度是介於3〇〇埃至1〇〇〇埃。 、依照本發明的較佳實施例所述之多晶矽層的製 法，上述之離子佈植製程包括是使用一離子佈植機^、 、、依照本發明的較佳實施例所述之多晶矽層的製造 ^上述讀子佈植製程職人的料包域離子錢離 依照本發明的較佳實施例所述之多晶石夕層 /旦離子佈植製程之佈植能量為10〜50keV、佈“ 里為1x10〜1χ1〇16個/咖2。 法 依照本發明的難實施綱狀多晶⑪層的製造方 上述之再結晶製程包括一熱爐管退火製程。 法 Γί ίη的較佳實卿㈣之？晶⑪層的製造方 上述之熱爐管退火製程的溫度在450〜550¾。 ，照本發_較佳實施綱述 製^述之再結嫩包括_準分子雷射（Εχ==) 方法二”轉的製造方法，此 接著，對非然後，形成—非轉層於基板上， -再層初—第—離子佈植製程。繼而，進行 多tr將非轉層轉化成—多糾層。之後，於 日日曰上形成-間絕緣層。接下來，於多晶石夕層上方的 doc/m 1249微_ 閘絕緣層上开>成一閘極，然後進行第二離子佈植製程，以 於閘極側邊之多晶矽層中形成一源極區和一汲極區。 依照本發明的較佳實施例所述之多晶矽薄膜電晶體的 製造方法，上述形成非晶矽層的方法包括一低壓化學氣相 沈積法。 ，依照本發明的較佳實施例所述之多晶石夕薄膜電晶體的 製造方法，上述之非晶石夕層的厚度是介於3GG埃至1000 埃0 、依知本發明的較佳實施例所述之多晶⑦薄膜電晶體的 裝k方法，上述之第一離子佈植製程包括是使用一離子佈 植機。 、依照本發明的較佳實施例所述之多晶㈣膜電晶體的 製造方法’上述之第—離子佈植製程所植人的離子包括氣 雜手或氮雛早、 =本發明的較佳實施觸述之多晶㈣膜電晶體的 製^ ί ’上述之第—離子佈植製程之佈植能量為 10〜5〇keV、佈植劑量為 lxl〇12〜lxl〇16個/cm2。 # S發明的較佳實施_述之多砂薄膜電晶體的 象"\ πϋ述之再結晶製程包括—熱爐管退火製程。 制明的較佳!施例所述之多晶矽薄膜電晶體的 ^ 述之熱爐官退火製程的溫度在450〜550。(：。 n明的較佳實施例所述之多晶㈣膜電晶體的 製这方法’上述之再結晶製程包括—準分 本發明因採用離子佈植的方法將氟離子或者氣離子植 I249H/m 入到非晶石夕層内，再經由熱退火的方法如固態、社曰 準分子雷射再結晶的方法形成多晶矽層。不但步:門=及 且可以增大晶粒的尺寸大小，進而提高載子的^移:早 改善多晶石夕層漏電流太大的缺點，並且亦得以古-、人 導通特性以及元件的可靠度。 呵凡件的 4為讓本發明之上述和其他目的、特徵和優點能更 易懂，下文特舉較佳實施例，並配合所附圖式、 明如下。 7口式作砰細說 【實施方式】 種多晶發層之製 圖1是依照本發明一較佳實施例的一 造流程步驟圖。 請參照圖1 ’此方法係先提供一基板（步驟1〇1)，其 板的材質例如是玻璃基板或石英基板。接著，形成一非= 石夕，於基板上（步驟1G3)，其中形成非轉層的方法= 如是在壓力100〜200mmtorr、溫度450〜50(rc的環境下進 行低塵化學餘沈積法，·成_晶韻厚度例二 於300埃至1〇〇〇埃。 & η 然後，對非晶石夕層進行-離子佈植製程（步驟1〇5)。 在-實施财，離子佈植製程例如包括是使用—離子佈植 機。離子佈植製程所植人的離子包括氟離子、氮離子或其 餘可與料騎發生鍵結之離子。再者，料佈植紫程之 佈植的能量例如約在1G〜爾eV，佈植的劑量例㈣是 1x10 〜lxl〇16個/cjq2。 上述離子佈植的能量與劑量係根據植入的離子，離子 1249微 8twf.doc/m 佈植機的種類、型號或其他操作參數如離子源、離 二Hi等的不同而可能有不同的設定，故而此 離子佈植的月b夏與劑量並非限定於本實施例所述。由 離子或氮離子能夠與石夕的懸鍵發生鍵結，減少帶電粒子在 晶界（gram boundary )被侷限的機會，致使晶界 可以減少漏電流發生的機會。 干中必 夕曰ίί =晶Λ層進行—再結晶製程’將非晶料轉化成 夕曰曰夕層（>驟107)。其中’再結晶製程可以是一熱爐管退 火製程，其溫度例如是控制在伽〜5抑之間以^非晶 矽層，使非晶矽層再結晶成為多晶矽層。 在另-實例中，步驟1〇7中的再^晶製程還可以是一 f分子雷射製程’例如以氟域準分子雷射照射非晶石夕 層，使非晶矽層熔融後再結晶成為多晶矽層。 圖2A至圖2F是依照本發明另一較佳^施例的一種多 晶石夕薄膜電晶體之製造流程剖面示意圖。 請參闕2A，此方法係先提供一基板2〇〇，基板2〇〇 例如是玻璃基板或石英基板。接著，形成一非晶韻施 於基板200上，其中形成非晶石夕層2〇1的方法例如是在麗 力100〜20〇mmtorr、溫度45〇〜·。c的環境下進行健化 學氣相沈積法’所形成的非晶矽層2〇1厚度例如是介於3〇〇 埃至1000埃。 、 然後，請參照圖2B，對非晶矽層2〇1進行苐一離子佈 植製程203。在-實施例巾’離子佈植製程2〇3例如包括 是使用-離子佈植機。離子佈植製程2〇3所植入的離子包 1249856 15438twf.doc/m 括氟離子、氮離子或其餘可與矽的懸鍵發生鍵結之離子。 再者，離子佈植的能量例如約在1〇〜5〇keV，佈植的劑量 如約是 lxlO12〜lxlO16個/cm2。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a thin film transistor, and more particularly to a method of fabricating a polycrystalline germanium layer and a polycrystalline germanium thin film transistor. [Prior Art] With the development of high technology, digital video or video devices have become a common product in everyday life. This disproportionate image device wipes the display to be an important component. The viewer can read the information or control the operation of the device. Thin Film Transistor (TFT) can be applied to the driving components of liquid crystal displays (LCDs), making this product the mainstream of desktop flat-panel display, for personal computers, game instruments, surveillance. Markets such as the market will become the dominant products in the future. At present, in a thin film transistor liquid crystal display, there is a thin film transistor which is obtained by using a polycrystalline germanium technique, and the carrier is relocated to a conventional amorphous (Am()rph〇us Silicon, a-Si) film. The mobility of the carrier of the transistor is much larger, so that the thin film transistor element can be made smaller and the aperture ratio is increased (Ap on reRati〇), thereby increasing the brightness of the display and reducing the power consumption. In addition, since the polycrystalline silicon thin film transistor is compatible with the current process of metal oxide semiconductor (M〇S), a part of the driving circuit (Driving Circuit) can be simultaneously fabricated on the glass substrate along with the thin film transistor process. In addition, the characteristics and reliability of the liquid crystal display panel are greatly improved, and the manufacturing cost of the panel is lowered, which is much cheaper than the amorphous germanium thin film transistor liquid crystal display. In addition, the polycrystalline silicon has the characteristics of thin thickness, light weight, and excellent resolution I24981^4wf.doc/m. It is especially suitable for mobile terminal products that require light and power saving. However, the polycrystalline germanium film transistor has excellent characteristics of high carrier mobility and still driving current (about 1 〇 -4 microamperes). However, in addition, 'the polycrystalline thin film transistor has more defect density', it also has a higher Leakage current (about 10 9 microamperes), and is easy to pass the channel drain (Drain) The lateral transverse electric field induces a hot carrier effect, which in turn leads to component degradation. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a method for manufacturing a polycrystalline germanium layer, which not only has a simple step, but also can increase the grain size of the polycrystalline germanium layer, thereby improving the mobility of the carrier to improve the polycrystalline germanium layer. The disadvantage of too much leakage current. Another purpose of the present invention is to provide a method for manufacturing a polycrystalline silicon thin film transistor, which can obtain a polycrystalline germanium thin film transistor having a large crystal grain size to improve the leakage current, thereby improving the conduction characteristics and components of the element. Reliability. The present invention proposes a method of producing a polycrystalline germanium layer which first provides a substrate. Then, an amorphous germanium layer is formed on the substrate. Next, an ion implantation process (ΐ〇η ΐπ1ρΐΜ^〇η p叩(10)$) is performed on the non-Japanese solar layer, and then a recrystallization process is performed to convert the amorphous germanium layer into a polycrystalline germanium layer. According to a method of fabricating a polysilicon layer according to a preferred embodiment of the present invention, the substrate comprises a glass substrate or a quartz substrate. 1249856 1543 8 twf.doc/m A method of fabricating a polysilicon layer according to a preferred embodiment of the present invention The above method of forming an amorphous germanium layer comprises a low pressure chemical vapor deposition method. According to a preferred embodiment of the preferred embodiment of the present invention, the amorphous germanium layer has a thickness of between 3 Å and 1 Å. According to a preferred embodiment of the preferred embodiment of the present invention, the ion implantation process includes the use of an ion implanter, and the fabrication of a polysilicon layer according to a preferred embodiment of the present invention. ^ The material of the above-mentioned reader-distributing agent is ion-charged from the polycrystalline stone layer/denier ion implantation process according to the preferred embodiment of the present invention, and the cloth energy is 10 to 50 keV, and the cloth is 1x10~1χ1〇16/coffee 2. The method for manufacturing the polycrystalline 11 layer which is difficult to implement according to the present invention The above recrystallization process includes a hot tube annealing process. What is the better case of the method 四 ί ίη (4)? The manufacturer of the crystal 11 layer has a temperature of 450 to 5503⁄4 in the annealing process of the hot tube, and the re-fabrication according to the present invention includes a _ excimer laser (Εχ==) method 2 "Transfer manufacturing method, and then, right and then, forming - non-transfer on the substrate, - re-layering - first - ion implantation process. Then, multi-tr is converted into a multi-deformation layer. After that, an insulating layer is formed on the crucible. Next, on the doc/m 1249 micro-gate insulating layer above the polycrystalline layer, a gate is formed, and then a second ion implantation process is performed to form a source in the polysilicon layer on the side of the gate. Polar zone and a bungee zone. According to a method of fabricating a polysilicon thin film transistor according to a preferred embodiment of the present invention, the method for forming an amorphous germanium layer comprises a low pressure chemical vapor deposition method. According to a preferred embodiment of the present invention, in the method for producing a polycrystalline silicon film, the thickness of the amorphous layer is between 3 GG and 1000 Å, and a preferred embodiment of the present invention is known. For the method of mounting a polycrystalline 7 thin film transistor as described in the above, the first ion implantation process includes using an ion implanter. The method for manufacturing a polycrystalline (tetra) film transistor according to the preferred embodiment of the present invention is characterized in that the ion implanted in the first ion implantation process includes a gas hand or a nitrogen early, and is preferably a preferred embodiment of the present invention. The implementation of the above-mentioned polycrystalline (tetra) film transistor is carried out. The above-mentioned first-ion implantation process has an implantation energy of 10 to 5 〇 keV and a planting dose of lxl 〇 12 to lxl 〇 16 / cm 2 . The preferred embodiment of the invention of the invention has the recrystallization process of the image of the multi-sand film transistor. Preferably, the temperature of the polycrystalline tantalum film transistor described in the embodiment is 450 to 550. (: The method for producing a polycrystalline (tetra) film transistor according to the preferred embodiment of the present invention' The recrystallization process described above includes - quasi-division. The present invention employs ion implantation to implant fluoride ions or gas ions into I249H. /m into the amorphous layer, and then through the thermal annealing method such as solid state, community excimer laser recrystallization method to form polycrystalline germanium layer. Not only step: door = and can increase the size of the grain, In turn, the carrier shift is improved: the short-term improvement of the leakage current of the polycrystalline stone layer is too large, and the ancient-, human-conducting characteristics and the reliability of the component are also obtained. The objects, features, and advantages will be more apparent, and the preferred embodiments are described below in conjunction with the accompanying drawings, which are set forth below. Figure 7 is a schematic diagram of a polycrystalline layer. Figure 1 is in accordance with the present invention. A process flow diagram of a preferred embodiment. Please refer to FIG. 1 'This method provides a substrate (step 1〇1), the material of which is, for example, a glass substrate or a quartz substrate. Then, a non-stone is formed. Even on the substrate (step 1G3), where the shape Non-transfer method = If the pressure is 100~200mmtorr, the temperature is 450~50 (rc environment is low dust chemical deposition method, and the thickness of the crystal is 2 angstroms to 1 angstrom.) η Then, the amorphous ion layer is subjected to an ion implantation process (step 1〇5). In the implementation, the ion implantation process includes, for example, using an ion implanter. The ions implanted by the ion implantation process Including fluoride ions, nitrogen ions or the rest of the ions that can be bonded to the material. In addition, the energy of the planting purple planting is, for example, about 1G~er eV, and the dose of the planting (4) is 1x10~lxl〇 16 /cjq2. The energy and dose of the above ion implantation are based on the type of implanted ions, ion type 1249 micro 8twf.doc / m planter, model or other operating parameters such as ion source, off-Hi, etc. There may be different settings, so the monthly b-sum and dose of the ion implant are not limited to the embodiment. The ion or nitrogen ion can be bonded to the dangling bond of the stone, reducing the charged particles at the grain boundary (gram Boundary) is a limited opportunity to reduce the leakage of grain boundaries The chance of occurrence. The middle of the crystallization process - the recrystallization process 'converts the amorphous material into a layer (> 107). The 'recrystallization process can be a hot tube annealing For the process, the temperature is controlled, for example, between gamma and 5, and the amorphous germanium layer is recrystallized into a polycrystalline germanium layer. In another example, the recrystallization process in step 1〇7 can also be performed. Is a f-molecular laser process 'for example, irradiating an amorphous layer with a fluorine-domain excimer laser, and melting the amorphous germanium layer to recrystallize into a polycrystalline germanium layer. FIG. 2A to FIG. 2F are another preferred method according to the present invention. A schematic cross-sectional view of a manufacturing process of a polycrystalline silicon thin film transistor according to an embodiment. Referring to FIG. 2A, the method first provides a substrate 2, for example, a glass substrate or a quartz substrate. Next, an amorphous crystal is formed on the substrate 200, and the method for forming the amorphous slab layer 2 〇 1 is, for example, at 100 to 20 mm torror and at a temperature of 45 Torr. The thickness of the amorphous germanium layer 2'1 formed by the chemical vapor deposition method in the environment of c is, for example, 3 Å to 1000 Å. Then, referring to FIG. 2B, the amorphous germanium layer 2〇1 is subjected to a monolithic ion implantation process 203. The -implantation' ion implantation process 2〇3 includes, for example, the use of an ion implanter. Ion implantation process 2〇3 implanted ion package 1249856 15438twf.doc/m Includes fluoride ions, nitrogen ions or other ions that can bond with the dangling bonds of ruthenium. Further, the energy of the ion implantation is, for example, about 1 〇 to 5 〇 keV, and the implantation dose is about lxlO12 to lxlO16/cm2.
上述離子佈植的能量與劑量係根據植入的離子，離子 佈植機的種類、型號或其他操作參數如離子源、離子束的 電流大小、加速器等的不同而可能有不同的設定，故而離 子佈植的能量與劑量並非限定於本實施例所述。由於氟離 子或氮離子能夠與矽的懸鍵發生鍵結，減少帶電粒子在曰曰 界被侷限的齡，致使晶界能障降低，可喊少漏電流^ 之後’請參考圖2C ’對非晶矽層201進行一再結晶製程， 將非晶矽層201轉化成多晶矽層201a。其中，再結晶製程可 以是一熱爐管退火製程，其溫度例如是控制在450〜550它 3 ’ ^融非Μ層2〇卜使非晶石夕層2〇1躲晶成為 夕晶石夕層201a。The energy and dose of the above ion implantation may be different according to the implanted ions, the type, model or other operating parameters of the ion implanter, such as the ion source, the current of the ion beam, the accelerator, etc., so the ions The energy and dose of the implant are not limited to those described in this embodiment. Since fluoride ions or nitrogen ions can bond with the dangling bonds of ruthenium, reducing the age at which the charged particles are confined in the boundary, causing the grain boundary energy barrier to decrease, and shouting less leakage current ^ after 'Please refer to Figure 2C' The wafer layer 201 is subjected to a recrystallization process to convert the amorphous germanium layer 201 into a polycrystalline germanium layer 201a. Wherein, the recrystallization process can be a hot furnace tube annealing process, and the temperature thereof is, for example, controlled at 450 to 550. It is 3' ^ melting non-Μ layer 2 〇 使 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶 非晶Layer 201a.
^在另較佳一實施例中，再結晶製程還可以是一準分子 雷射製程，例如以氟化氪準分子雷射照射非晶矽層201， 使非晶矽層201熔融後再結晶成為多晶矽層2〇u。 ㈠叫木丨匕夕日日，以^ 狀多晶石夕層201b。其中，圖案化多晶石夕層2〇la的， 例如是微影、侧製程。接著，於島狀多晶石夕層201b ^ ，一閘絕緣層205。閘絕緣層2〇5的材質例如是氧化; =石夕’其形成方法例如是化學氣相沈積法或其他合: 灰程。 11 1249856 15438twf.doc/m 之後，凊參照圖2E，於多晶矽層2〇lb上方的閘絕緣 層205上形成一閘極207。閘極2〇7的材質例如是鉻或鈕， 其形成方法例如是先沈積一層金屬薄膜，再以微影、蝕刻 製程疋義出閉極207。 然後，以閘極207為罩幕，進行第二離子佈植製程 209，以於閘極207側邊之多晶石夕層2〇lb中形成一源極區 211a和一汲極區211b，如圖2F所示。植入的離子可以是 P型離子或N型離子，其係端視所欲形成之元件的型態而 定。 、綜上所述，本發明由於採用離子佈植的方法將氟離子· 或者氮離子植入到非晶矽薄膜内，由於氟離子或氪離子能 夠與矽的懸鍵發生鍵結，可以減少漏電流發生的機會。 之後，本發明再經由熱退火的方法將非晶矽層轉化為 多晶矽層。前述多晶矽層的製造方法不但步驟簡單，且可 以增大晶粒的尺寸大小，進而提高載子的遷移率，以改善 多晶石夕層漏電流太大的缺點，並且亦得提高元件的導通特 性以及元件的可靠度。 、 雖然本發明已以較佳實施例揭露如上，然其並非用以 魯 限^發明，，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為依照本發明-較佳實施例的一種多晶石夕層之 造流程步驟圖。 12 1249微 8twf.doc/m 圖2A至圖2F為依照本發明另一較佳實施例的一種多 晶矽薄膜電晶體之製造流程剖面圖。 【主要元件符號說明】 101、103、105、107 :步驟 200 :基板 201 :非晶矽層 201a :多晶砍層 201b:島狀多晶矽層 203 :第一離子佈植製程 鲁 205 :閘絕緣層 207 :閘極 209 :第二離子佈植製程 211a :源極區 211 b · >及極區 13In another preferred embodiment, the recrystallization process may also be a quasi-molecular laser process, for example, irradiating the amorphous germanium layer 201 with a fluorinated fluorene excimer laser to melt the amorphous germanium layer 201 and then recrystallize it. Polycrystalline germanium layer 2〇u. (1) Calling the day of the wood, the polycrystalline stone layer 201b. Wherein, the patterned polycrystalline stone layer 2〇la is, for example, a lithography or a side process. Next, an island insulating layer 205 is formed on the island-shaped polycrystalline layer 201b. The material of the gate insulating layer 2〇5 is, for example, oxidized; the method of forming the stone etch is, for example, a chemical vapor deposition method or the like: a ash process. After 12 1249856 15438 twf.doc/m, referring to FIG. 2E, a gate 207 is formed on the gate insulating layer 205 above the polysilicon layer 2 〇 lb. The material of the gate 2〇7 is, for example, chrome or a button, and is formed by, for example, depositing a metal thin film, and then opening and closing the electrode 207 by lithography and etching. Then, using the gate 207 as a mask, a second ion implantation process 209 is performed to form a source region 211a and a drain region 211b in the polycrystalline layer 2〇1b on the side of the gate 207, such as Figure 2F shows. The implanted ions can be P-type ions or N-type ions depending on the type of element desired to be formed. In summary, the present invention implants fluoride ions or nitrogen ions into the amorphous germanium film by ion implantation, and the fluorine ions or germanium ions can be bonded to the dangling bonds of the germanium to reduce leakage. The opportunity for current to occur. Thereafter, the present invention converts the amorphous germanium layer into a polycrystalline germanium layer by thermal annealing. The manufacturing method of the polycrystalline germanium layer is not only simple in steps, but also can increase the size of the crystal grains, thereby improving the mobility of the carrier, thereby improving the shortcoming of the polycrystalline silicon layer leakage current, and also improving the conduction characteristics of the element. And the reliability of the components. While the invention has been described above in terms of a preferred embodiment, it is not intended to be limited to the invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the steps of a polycrystalline stone layer in accordance with a preferred embodiment of the present invention. 12 1249 micro 8twf.doc/m FIGS. 2A to 2F are cross-sectional views showing a manufacturing process of a polysilicon thin film transistor according to another preferred embodiment of the present invention. [Main component symbol description] 101, 103, 105, 107: Step 200: Substrate 201: Amorphous germanium layer 201a: Polycrystalline chopped layer 201b: Island polycrystalline germanium layer 203: First ion implantation process Lu 205: Gate insulating layer 207: gate 209: second ion implantation process 211a: source region 211 b · > and polar region 13